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Background debug controller (BDC)
BKGD is a pseudo-open-drain pin and there is an on-chip pullup so no external pullup
resistor is required. Unlike typical open-drain pins, the external RC time constant on this
pin, which is influenced by external capacitance, plays almost no role in signal rise time.
The custom protocol provides for brief, actively driven speedup pulses to force rapid rise
times on this pin without risking harmful drive level conflicts. Refer to
Communication
details
for more detail.
When no debugger pod is connected to the 6-pin BDM interface connector, the internal
pullup on BKGD chooses normal operating mode. When a debug pod is connected to
BKGD it is possible to force the MCU into active background mode after reset. The
specific conditions for forcing active background depend upon the HCS08 derivative
(refer to the introduction to this Development Support section). It is not necessary to reset
the target MCU to communicate with it through the background debug interface.
27.2.2 Communication details
The BDC serial interface requires the external controller to generate a falling edge on the
BKGD pin to indicate the start of each bit time. The external controller provides this
falling edge whether data is transmitted or received.
BKGD is a pseudo-open-drain pin that can be driven either by an external controller or
by the MCU. Data is transferred MSB first at 16 BDC clock cycles per bit (nominal
speed). The interface times out if 512 BDC clock cycles occur between falling edges
from the host. Any BDC command that was in progress when this timeout occurs is
aborted without affecting the memory or operating mode of the target MCU system.
The custom serial protocol requires the debug pod to know the target BDC
communication clock speed.
The clock switch (CLKSW) control bit in the BDC status and control register allows the
user to select the BDC clock source. The BDC clock source can either be the MSTRCLK
or the alternate BDC clock source.
The BKGD pin can receive a high or low level or transmit a high or low level. The
following diagrams show timing for each of these cases. Interface timing is synchronous
to clocks in the target BDC, but asynchronous to the external host. The internal BDC
clock signal is shown for reference in counting cycles.
The following figure shows an external host transmitting a logic 1 or 0 to the BKGD pin
of a target HCS08 MCU. The host is asynchronous to the target so there is a 0-to-1 cycle
delay from the host-generated falling edge to where the target perceives the beginning of
the bit time. Ten target BDC clock cycles later, the target senses the bit level on the
BKGD pin. Typically, the host actively drives the pseudo-open-drain BKGD pin during
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
532
NXP Semiconductors
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