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26.3.2.2 Period
The PWM period is determined by the value written to the counter modulo (CMOD)
registers. The PWM counter is an up/down counter in a center-aligned operation. In this
mode the PWM highest output resolution is two 2× system clock cycles if the PWM
clock inputs from 2× system clock. The modulus is one-half of the PWM output period in
PWM clock cycles.
PWM period = (PWM modulus) × (PWM clock period) × 2
PWM Period = 8 ×
The PWM counter is an up-counter during an edge-aligned operation. In this mode, the
PWM highest output resolution is one 2× system clock cycle if the PWM clock inputs
from 2× system clock. The modulus is the period of the PWM output in PWM clock
cycles.
PWM period = (PWM modulus) × (PWM clock period)
26.3.2.3 Pulse width duty cycle
The signed 16-bit number written to the PWM value registers is the pulse width in PWM
clock periods of the PWM prescaler output (or period minus the pulse width if
CINVx=1).
NXP Semiconductors
Up/Down Counter Modulus = 4
PWM Clock Period
PWM Clock Period
Figure 26-5. Center-Aligned PWM period
Up Counter Modulus = 4
PWM Clock Period
PWM Period = 4 × PWM Clock Period
Figure 26-6. Edge-Aligned PWM period
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 26 Pulse Width Modulator (PWM)
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