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Memory map and register definition
Field
0
Interrupt disabled.
1
Interrupt enabled.
2
Analog Comparator Flag Rising
CFR
During normal operation, the CFR bit is set when a rising edge on COUT has been detected. The CFR bit
is cleared by writing a logic one to the bit.
0
Rising edge on COUT has not been detected.
1
Rising edge on COUT has occurred.
1
Analog Comparator Flag Falling
CFF
During normal operation, the CFF bit is set when a falling edge on COUT has been detected. The CFF bit
is cleared by writing a logic one to the bit.
0
Falling edge on COUT has not been detected.
1
Falling edge on COUT has occurred.
0
Analog Comparator Output
COUT
Reading the COUT bit will return the current value of the analog comparator output. The register bit is
reset to zero and will read as CR1[INV] when the Analog Comparator module is disabled (CR1[EN] = 0).
Writes to this bit are ignored.
25.6.5 PHCMP1 Control Register 0 (GDU_PHCMP1CR0)
Address: 20h base + 4h offset = 24h
Bit
7
Read
0
Write
Reset
0
Field
7
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
6–4
Filter Sample Count
FILTER_CNT
These bits represent the number of consecutive samples that must agree prior to the comparator ouput
filter accepting a new output state. For information regarding filter programming and latency reference the
Functional Description.
000
Filter is disabled. If SE = 1, then COUT is a logic zero (this is not a legal state, and is not
recommended). If SE = 0, COUT = COUTA.
001
1 consecutive sample must agree (comparator output is simply sampled).
010
2 consecutive samples must agree.
011
3 consecutive samples must agree.
100
4 consecutive samples must agree.
101
5 consecutive samples must agree.
442
GDU_PHCMP0SCR field descriptions (continued)
6
5
FILTER_CNT
0
0
GDU_PHCMP1CR0 field descriptions
Table continues on the next page...
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Description
4
3
0
0
Description
2
1
0
HYSTCTR
0
0
NXP Semiconductors
0
0
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