NXP Semiconductors MC9S08SU16 Reference Manual page 490

Functional description
The complementary channel operation drives top and bottom transistors in an inverter
circuit, such as the one in the following figure.
AC
Inputs
In complementary channel operation, there are three additional features:
• Deadtime insertion
• Separate top and bottom pulse width correction for distortions caused by deadtime
inserted and reactive load characteristics
• Separate top and bottom output polarity control
490
VAL0 VAL1
Register Register
PWM CHANNELS 0 AND 1
VAL2 VAL3
Register Register
PWM CHANNELS 2 AND 3
VAL4 VAL5
Register Register
PWM CHANNELS 4 AND 5
Figure 26-9. Complementary channel pairs
PWM
0
PWM
1
Figure 26-10. Typical 3-phase inverter
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
TOP
BOTTOM
TOP
BOTTOM
TOP
BOTTOM
PWM PWM
2 4
PWM PWM
3 5
3-Phase
Load
NXP Semiconductors