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Chapter 8
Port Control (PORT)
8.1 Introduction
This device has three sets of I/O ports, which include up to 17 general-purpose I/O pins.
To enable the GPIO function, SIM_MUXPTxL/SIM_MUXPTxH (x=A, B, or C)
registers need be adjusted to select ALT3.
The pin control register configures the following functions for each pin within the 8-bit
port.
• Out data on selected pins
• In/out direction on selected pins
• Pullup/pulldown enable on selected pins
KBI shares with PTA on ALT3, so PTA function works only when KBI_PE is disabled;
The following figure show the structure of normal I/O pin(PTA0 as example).
MUXPTA0
ALT0 in en
ALT1 in en
ALT2 in en
PTADD0=0
Digital peripheral
or CPU read
Analog peripheral
NXP Semiconductors
ALT0 out en
ALT1 out en
ALT2 out en
PTADD0=1
ALT0 out data
ALT1 out data
ALT2 out data
PTAD0
0/1/PTAD0
0
1
Synchronizer &
Glitch filter
Figure 8-1. Normal I/O structure
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
PTAPE0
(is '0' when analog or output,
'1' when BKGD/RESET)
BUS clock
PTA0
FLTDIV1
FLTDIV2
FLTDIV3
83
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