Asymmetric Pwm Output - NXP Semiconductors MC9S08SU16 Reference Manual

The waveform at the output pin is delayed by two PWM
Operation Clock cycles for deadtime insertion.

26.3.5 Asymmetric PWM output

In complementary mode with center-align operation, the PWM duty cycle is able to
change alternatively at every half cycle. The count direction of the PWM counter selects
either the odd or the even PWM value registers to use in the PWM cycle. For counting
up, select even PWM value registers to use in the PWM cycle. For counting down, select
odd PWM value registers to use in the PWM cycle.
Up/Down Counter
Modulus = 4
Even PWM
Value = 1
Odd PWM
Value = 3
Even PWM
Value = 3
Odd PWM
Value = 1
Figure 26-15. Asymmetric waveform - phase shift PWM output
26.3.6 Variable edge placement PWM output
In complementary mode with edge-aligned mode, the timing of both edges of the PWM
output can be controlled using the PECn bits in the PECTRL register and the CINVn bits
in the CINV register. The edge aligned pulse created by the even value register and the
associated CINV bit is XORed with the pulse created by the odd value register and its
associated CINV. The results of the XOR are fed into the complement and dead-time
logic. In contrast to asymmetric PWM output mode, the PWM phase shift can pass the
PWM cycle boundary, as shown in the following figure.
NXP Semiconductors
NOTE
4
3
2
1
0
Even PWM Odd PWM
Value
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 26 Pulse Width Modulator (PWM)
Even PWM
Value Value
Odd PWM
Value
493