Bit Address - NXP Semiconductors MC9S08SU16 Reference Manual

Functional description
Table 21-3. I2C divider and hold values (continued)
ICR SCL SDA hold
divider
(hex)
14 80
15 88
16 104
17 128
18 80
19 96
1A 112
1B 128
1C 144
1D 160
1E 192
1F 240

21.5.2 10-bit address

For 10-bit addressing, 0x11110 is used for the first 5 bits of the first address byte.
Various combinations of read/write formats are possible within a transfer that includes
10-bit addressing.
21.5.2.1 Master-transmitter addresses a slave-receiver
The transfer direction is not changed. When a 10-bit address follows a START condition,
each slave compares the first 7 bits of the first byte of the slave address (11110XX) with
its own address and tests whether the eighth bit (R/W direction bit) is 0. It is possible that
more than one device finds a match and generates an acknowledge (A1). Each slave that
finds a match compares the 8 bits of the second byte of the slave address with its own
address, but only one slave finds a match and generates an acknowledge (A2). The
matching slave remains addressed by the master until it receives a STOP condition (P) or
a repeated START condition (Sr) followed by a different slave address.
Table 21-4. Master-transmitter addresses slave-receiver with a 10-bit address
Slave R/W
S
address 0
first 7 bits
11110 +
AD10 +
AD9
382
SCL hold SCL hold
value (start) (stop)
value value
17 34 41
17 38 45
21 46 53
21 58 65
9 38 41
9 46 49
17 54 57
17 62 65
25 70 73
25 78 81
33 94 97
33 118 121
Slave
A1
address
second
byte
AD[8:1]
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
ICR SCL
divider
(hex)
(clocks)
34 1152
35 1280
36 1536
37 1920
38 1280
39 1536
3A 1792
3B 2048
3C 2304
3D 2560
3E 3072
3F 3840
A2 Data A
SDA hold SCL hold SCL hold
(clocks) (start) (stop)
value value
193 574
193 638
257 766
257 958
129 638
129 766
257 894
257 1022 1025
385 1150 1153
385 1278 1281
513 1534 1537
513 1918 1921
... Data A/A
NXP Semiconductors
577
641
769
961
641
769
897
P