Block Diagram - NXP Semiconductors MC9S08SU16 Reference Manual

20.2.3 Block diagram

The following figure show the block diagram of the PWT.
BUS_CLK
SYNC
ALT_CLK
PCLKS
PWTEN
PWTIN0
PWTIN1
PWTIN2
PWTIN3 PWTIN
PINSEL[1:0]
PINEN0
PINEN1
PINEN2
PINEN3
Figure 20-1. Pulse width timer (PWT) block diagram
20.3 External signal description
20.3.1 Overview
PWT has the following signal.
NXP Semiconductors
Clock Pre-scaler(CLKPRE)
/2 /2 /2
MUX
16 bit free running counter PWTCNT[15:0]
PWTNPW[15:0]
Edge Detect and Capture Control Logic
PWTTOG
PWTLVL
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
/2 /2 /2 /2
PWTCLK
16
PWTPPW[15:0]
PWTRDY
PWTIE
PRDYIE
Chapter 20 Pules Width Timer (PWT)
PRE[2:0]
PWTSR
PWTOV
POVIE
Data
Interrupt
Overflow
Interrupt
345