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Introduction
26.2
Introduction
26.2.1 Overview
This chapter describes the pulse width modulator (PWM) module. The PWM can be
configured as three complementary pairs, six independent PWM signals, or their
combinations (such as one complementary pair and four independent signals). Both edge-
and center-aligned synchronous pulse-width control, from zero to 100 percent
modulation, are supported.
A 15-bit common PWM counter is applied to all six channels. PWM resolution is one
clock period for edge-aligned operation and two clock periods for center-aligned
operation. The clock period is dependent on system clock frequency and a programmable
prescaler.
When generating complementary PWM signals, the module features automatic deadtime
insertion to PWM output pairs. Each PWM output can be controlled manually by a PWM
generator or software, and separate top and bottom output-polarity control. Asymmetric
PWM output is able to change the PWM duty cycle alternatively at every half cycle
without software involvement.
26.2.2 Features
The PWM has the following features:
• PWM operation clock runs at system clock
• Six PWM signals
• all independent
• complementary pairs
• mix independent and complementary
• Features of complementary channel operation
• separate deadtime insertions for rising and falling edges
• separate top and bottom pulse-width correction via software
• asymmetric PWM output within center align operation
• separate top and bottom polarity control
• Edge- or center-aligned PWM signals
• 15 bits of resolution
• Half-cycle reload capability
• Integral reload rates from 1 to 16
• Individual software controlled PWM output
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MC9S08SU16 Reference Manual, Rev. 5, 4/2017
NXP Semiconductors
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