Pwm Compare Invert Register: High (Pwm_Cinvh) - NXP Semiconductors MC9S08SU16 Reference Manual

Address: 40h base + 17E6h offset = 1826h
Bit 7
Read 0
Write
Reset 0
Field
7–6 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
5 Pulse Edge Control 2
PEC2
This bit controls PWM4/PWM5 pair.
0 Normal operation.
1 Allow one of VAL4 and VAL5 to activate the PWM pulse and the other to deactivate the pulse.
4 Pulse Edge Control 1
PEC1
This bit controls PWM2/PWM3 pair.
0 Normal operation.
1 Allow one of VAL2 and VAL3 to activate the PWM pulse and the other to deactivate the pulse.
3 Pulse Edge Control 0
PEC0
This bit controls PWM0/PWM1 pair.
0 Normal operation.
1 Allow one of VAL0 and VAL1 to activate the PWM pulse and the other to deactivate the pulse.
Reserved This field is reserved.
This read-only field is reserved and always has the value 1.

26.4.25 PWM Compare Invert Register: High (PWM_CINVH)

This register is affected by the WP bit in the CNFG register. It can only be written when
that bit is clear.
Address: 40h base + 17E9h offset = 1829h
Bit 7
Read 0
Write
Reset 0
Field
7–6 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
NXP Semiconductors
6 5
PEC2 PEC1
0 0
PWM_PECTRLL field descriptions
6 5
CINV5 CINV4
0 0
PWM_CINVH field descriptions
Table continues on the next page...
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 26 Pulse Width Modulator (PWM)
4 3
PEC0
0 0
Description
4 3
CINV3 CINV2
0 0
Description
2 1
1
0 1
2 1
CINV1 CINV0
0 0
0
1
0
0
525