NXP Semiconductors P89LPC952 Manuals

Manuals and User Guides for NXP Semiconductors P89LPC952. We have 1 NXP Semiconductors P89LPC952 manual available for free PDF download: User Manual

NXP Semiconductors P89LPC952 User Manual

NXP Semiconductors P89LPC952 User Manual (134 pages)

Brand: NXP Semiconductors | Category: Microcontrollers | Size: 0 MB

Table of Contents

1 Introduction

3
- Pin Configuration
  3
- Pin Description
  5
- Special Function Registers
  11
- Memory Organization
  20
2 Clocks

22
- Enhanced CPU
  22
- Clock Definitions
  22
- Oscillator Clock (OSCCLK)
  22
- Low Speed Oscillator Option
  22
- Medium Speed Oscillator Option
  22
- High Speed Oscillator Option
  22
- Clock Output
  23
- On-Chip RC Oscillator Option
  23
- Watchdog Oscillator Option
  24
- External Clock Input Option
  24
- Oscillator Clock (OSCCLK) Wake-Up Delay
  25
- CPU Clock (CCLK) Modification: DIVM Register
  26
- Low Power Select
  26
3 A/D Converter

26
- General Description
  26
- A/D Features
  26
- A/D Operating Modes
  27
- Fixed Channel, Single Conversion Mode
  27
- Fixed Channel, Continuous Conversion Mode
  27
- Auto Scan, Single Conversion Mode
  28
- Auto Scan, Continuous Conversion Mode
  28
- Dual Channel, Continuous Conversion Mode
  28
- Single Step Mode
  29
- Conversion Mode Selection Bits
  29
- Conversion Start Modes
  30
- Timer Triggered Start
  30
- Start Immediately
  30
- Edge Triggered
  30
- Stopping and Restarting Conversions
  30
- Boundary Limits Interrupt
  30
- Clock Divider
  30
- I/O Pins Used with ADC Functions
  31
- Power-Down and Idle Mode
  31
4 Interrupts

33
- Interrupt Priority Structure
  34
- External Interrupt Pin Glitch Suppression
  35
5 I/O Ports

36
6 Power Monitoring Functions

42
- Brownout Detection
  42
- Power-On Detection
  43
- Power Reduction Modes
  43
7 Reset

46
- Reset Vector
  48
8 Timers 0 and 1

48
- Mode 0
  49
- Mode 1
  50
- Mode 2
  50
- Mode 3
  50
- Mode 6
  50
- Timer Overflow Toggle Output
  52
9 Real-Time Clock System Timer

53
10 Uarts

56
- Mode 0
  56
- Mode 1
  56
- Mode 2
  56
- Mode 3
  57
- SFR Space
  57
- Baud Rate Generator and Selection
  57
- Updating the BRGR1 and BRGR0 Sfrs
  58
- Framing Error
  59
- Break Detect
  59
- More about UART Mode 0
  62
- More about UART Mode 1
  63
- More about UART Modes 2 and 3
  64
- Framing Error and Ri_N in Modes 2 and 3 with Sm2_N = 1
  64
- Break Detect
  65
- Double Buffering
  65
- Double Buffering in Different Modes
  65
- Transmit Interrupts with Double Buffering Enabled (Modes 1, 2, and 3)
  65
- The 9Th Bit (Bit 8) in Double Buffering (Modes 1, 2, and 3)
  66
- Multiprocessor Communications
  67
- Automatic Address Recognition
  68
- C Interface
  
  69
  - C Data Register
    70
  - C Slave Address Register
    70
  - C Control Register
    71
  - C SCL Duty Cycle Registers I2SCLH and I2SCLL
    72
  - C Status Register
    72
  - C Operation Modes
    73
  - Master Transmitter Mode
    73
  - Master Receiver Mode
    74
  - Slave Receiver Mode
    75
  - Slave Transmitter Mode
    76
12 Serial Peripheral Interface (SPI)

83
- Configuring the SPI
  87
- Additional Considerations for a Slave
  88
- Additional Considerations for a Master
  88
- Mode Change on SS
  88
- Write Collision
  89
- Data Mode
  89
- SPI Clock Prescaler Select
  93
13 Analog Comparators

93
14 Keypad Interrupt (KBI)

97
15 Watchdog Timer (WDT)

98
- Watchdog Function
  98
- Feed Sequence
  99
- Watchdog Clock Source
  102
- Watchdog Timer in Timer Mode
  103
- Power-Down Operation
  104
- Periodic Wake-Up from Power-Down Without an External Oscillator
  104
16 Additional Features

104
- Software Reset
  105
- Dual Data Pointers
  105
- Debugger Interface
  105
- Debugger Connections
  106
17 Flash Memory

107
- General Description
  107
- Features
  107
- Flash Programming and Erase
  107
- Using Flash as Data Storage: IAP-Lite
  108
- In-Circuit Programming (ICP)
  111
- ISP and IAP Capabilities of the P89LPC952/954
  112
- Boot ROM
  112
- Power on Reset Code Execution
  112
- Hardware Activation of Boot Loader
  112
- In-System Programming (ISP)
  113
- Using the In-System Programming (ISP)
  113
- In-Application Programming (IAP)
  117
- IAP Authorization Key
  117
- Flash Write Enable
  117
- Configuration Byte Protection
  118
- IAP Error Status
  118
- User Configuration Bytes
  122
- User Security Bytes
  123
- Boot Vector Register
  124
- Boot Status Register
  125
18 Instruction Set

126
20 Tables

130
21 Figures

132

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