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Memory map/register definition
Field
4
Timeout Counter Clock Select
TCKSEL
Selects the clock source of the timeout counter.
0
Timeout counter counts at the frequency of the I2C module clock / 64
1
Timeout counter counts at the frequency of the I2C module clock
3
SCL Low Timeout Flag
SLTF
This bit is set when the SLT register (consisting of the SLTH and SLTL registers) is loaded with a non-zero
value (LoValue) and an SCL low timeout occurs. Software clears this bit by writing a logic 1 to it.
NOTE: The low timeout function is disabled when the SLT register's value is 0.
0
No low timeout occurs
1
Low timeout occurs
2
SCL High Timeout Flag 1
SHTF1
This read-only bit sets when SCL and SDA are held high more than clock × LoValue / 512, which indicates
the bus is free. This bit is cleared automatically.
0
No SCL high and SDA high timeout occurs
1
SCL high and SDA high timeout occurs
1
SCL High Timeout Flag 2
SHTF2
This bit sets when SCL is held high and SDA is held low more than clock × LoValue / 512. Software clears
this bit by writing 1 to it.
0
No SCL high and SDA low timeout occurs
1
SCL high and SDA low timeout occurs
0
SHTF2 Interrupt Enable
SHTF2IE
Enables SCL high and SDA low timeout interrupt.
0
SHTF2 interrupt is disabled
1
SHTF2 interrupt is enabled
21.4.10 I2C Address Register 2 (I2C_A2)
Address: 18B0h base + 9h offset = 18B9h
Bit
7
Read
Write
Reset
1
Field
7–1
SMBus Address
SAD
374
I2C_SMB field descriptions (continued)
6
5
SAD
1
0
I2C_A2 field descriptions
Table continues on the next page...
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Description
4
3
0
0
Description
2
1
0
1
NXP Semiconductors
0
0
0
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