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Memory map and register definition
Field
6
Windowing Enable
WE
At any given time, either SE or WE can be set. If a write to this register attempts to set both, then SE is set
and WE is cleared. However, avoid writing 1 to both bits because this "11" case is reserved and may
change in future implementations.
NOTE: Set this bit to zero, because the window input is connected to the logic 1.
5
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
4
Power Mode select
PMODE
0
Low-speed (LS) comparison mode is selected.
1
High-speed (HS) comparison mode is selected.
3
Comparator Invert
INV
This bit allows to select the polarity of the analog comparator function. It is also driven to the COUT output
(on both the device pin and as GDU_USCR[COUT]) when GDU_UCR1[OPE]=0.
0
Does not invert the comparator output.
1
Inverts the comparator output.
2
Comparator Output Select
COS
NOTE: This field is always disabled in this device, writing 1 to this field does not take effect.
0
Sets CMPO to equal to COUT (filtered comparator output).
1
Sets CMPO to equal to COUTA (unfiltered comparator output).
1
Comparator Output Pin Enable
OPE
NOTE: This field is always disabled in this device, writing 1 to this field does not take effect.
0
The comparator output (CMPO) is not available on the associated CMPO output pin.
The pin is available for use by other on-chip functions.
1
The comparator output (CMPO) is available on the associated CMPO output pin.
The comparator output (CMPO) is driven out on the associated CMPO output pin.
0
Comparator Enable
EN
0
Analog Comparator is disabled.
1
Analog Comparator is enabled.
25.6.19 LIMIT0 CMP Filter Period Register (GDU_LIMIT0FPR)
Address: 20h base + 1856h offset = 1876h
Bit
7
Read
Write
Reset
0
454
GDU_LIMIT0CR1 field descriptions (continued)
6
5
0
0
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Description
4
3
FLTPER
0
0
2
1
0
0
NXP Semiconductors
0
0
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