Table of Contents
Advertisement
Memory Map and Register Descriptions
26.4.15 PWM Deadtime Register: Low (PWM_DTIMnL)
Deadtime operation is only applicable to complementary channel operation. The 12-bit
value written to this write-protected registers is in terms of PWM clock cycles. Reset sets
the PWM deadtime register to a default value of 0x0FFF, selecting a deadtime of 4096-
PWM clock cycles minus one PWM clock cycle. This register is write protected after the
WP bit in the PWM configuration register is set. Reserved bits 15–12 cannot be modified.
They are read as zero.
Deadtime is affected by changes to the prescaler value. The
deadtime duration is determined as follows: DT = P × PWMDT
– 1, where DT is deadtime, P is the prescaler value, PWMDT is
the programmed value of dead time. For example: if the
prescaler is programmed for a divide-by-two and PWMDT is
set to five, then P = 2 and the deadtime value is equal to DT = 2
× 5 – 1 = 9 PWM clock cycles. A special case exists when the P
= 1, DT = PWMDT
The PWMDT field is used to control the deadtime during transitions of the even PWM
output.
Address: 40h base + 18h offset + (2d × i), where i=0d to 1d
Bit
7
Read
Write
Reset
1
Field
PWMDT7_0
PWM Pulse Width Value7:0
26.4.16 PWM Deadtime Register: High (PWM_DTIMnH)
Deadtime operation is only applicable to complementary channel operation. The 12-bit
value written to this write-protected registers is in terms of PWM clock cycles. Reset sets
the PWM deadtime register to a default value of 0x0FFF, selecting a deadtime of 4096-
PWM clock cycles minus one PWM clock cycle. This register is write protected after the
WP bit in the PWM configuration register is set. Reserved bits 15–12 cannot be modified.
They are read as zero.
518
NOTE
6
5
1
1
PWM_DTIMnL field descriptions
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
4
3
PWMDT7_0
1
1
Description
2
1
1
1
NXP Semiconductors
0
1
Advertisement
Table of Contents
