Debug Comparator B High Register (Dbg_Cbh) - NXP Semiconductors MC9S08SU16 Reference Manual

Memory map and registers

28.3.3 Debug Comparator B High Register (DBG_CBH)

All the bits in this register reset to 0 in POR or non-end-run
reset. The bits are undefined in end-run reset. In the case of an
end-trace to reset where DBGEN = 1 and BEGIN = 0, the bits
in this register do not change after reset.
Address: 18C0h base + 2h offset = 18C2h
Bit 7
Read
Write
Reset
0
Field
CB[15:8] Comparator B High Compare Bits
The Comparator B High compare bits control whether Comparator B will compare the address bus bits
[15:8] to a logic 1 or logic 0.Not used in full mode.
0 Compare corresponding address bit to a logic 0.
1 Compare corresponding address bit to a logic 1.
28.3.4 Debug Comparator B Low Register (DBG_CBL)
All the bits in this register reset to 0 in POR or non-end-run
reset. The bits are undefined in end-run reset. In the case of an
end-trace to reset where DBGEN = 1 and BEGIN = 0, the bits
in this register do not change after reset.
Address: 18C0h base + 3h offset = 18C3h
Bit 7
Read
Write
Reset 0
554
NOTE
6 5
0 0
DBG_CBH field descriptions
NOTE
6 5
0 0
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
4 3
CB[15:8]
0 0
Description
4 3
CB[7:0]
0 0
2 1
0 0
2 1
0 0
NXP Semiconductors
0
0
0
0