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Register definition
Field
110
Encoding 6—Divides the selected clock by 64.
111
Encoding 7—Divides the selected clock by 128.
4
Low Power Select
LP
Controls whether the FLL is disabled in FLL bypassed modes.
0
FLL is not disabled in bypass mode.
1
FLL is disabled in bypass modes unless debug is active.
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
12.3.3 ICS Control Register 3 (ICS_C3)
Address: 1848h base + 2h offset = 184Ah
Bit
7
Read
Write
Reset
x*
* Notes:
•
SCTRIM is loaded during reset from a factory programmed location when not in BDM mode. If in a BDM mode, SCTRIM
gets loaded with a value of 0x80. x = Undefined at reset.
Field
SCTRIM
Slow Internal Reference Clock Trim Setting
Controls the slow internal reference clock frequency by controlling the internal reference clock period. The
bits are binary weighted. In other words, bit 1 adjusts twice as much as bit 0. Increasing the binary value of
SCTRIM will increase the period, and decreasing the value will decrease the period. An additional fine trim
bit is available as the ICS_C4[SCFTRIM].
ICS_C3 is automatically loaded during reset from a factory programmed location when not in a debug
mode. The factory programmed trim value adjusts the internal oscillator frequency to fint_ft as specified in
the datasheet. The user can provide a custom trim value to attain other internal reference clock
frequencies within the fint_t range. The custom trim value must be programmed into reserved flash
location 0x0000_FF6F and copied to ICS_C3 during code initialization.
194
ICS_C2 field descriptions (continued)
6
5
x*
x*
ICS_C3 field descriptions
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Description
4
3
SCTRIM
x*
x*
Description
2
1
x*
x*
NXP Semiconductors
0
x*
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