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I2C signal descriptions
2
21.3 I
C signal descriptions
The signal properties of I
Signal
Description
SCL
Bidirectional serial clock line of the I
SDA
Bidirectional serial data line of the I
21.4 Memory map/register definition
This section describes in detail all I2C registers accessible to the end user.
Absolute
address
(hex)
18B0
I2C Address Register 1 (I2C_A1)
18B1
I2C Frequency Divider register (I2C_F)
18B2
I2C Control Register 1 (I2C_C1)
18B3
I2C Status register (I2C_S)
18B4
I2C Data I/O register (I2C_D)
18B5
I2C Control Register 2 (I2C_C2)
18B6
I2C Stop Control and Status Register (I2C_SCS)
18B7
I2C Range Address register (I2C_RA)
18B8
I2C SMBus Control and Status register (I2C_SMB)
18B9
I2C Address Register 2 (I2C_A2)
18BA
I2C SCL Low Timeout Register High (I2C_SLTH)
18BB
I2C SCL Low Timeout Register Low (I2C_SLTL)
18BC
I2C Status register 2 (I2C_S2)
364
2
C are shown in the table found here.
2
Table 21-2. I
C signal descriptions
2
C system.
2
C system.
I2C memory map
Register name
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Width
Access
Reset value
(in bits)
8
R/W
00h
8
R/W
00h
8
R/W
00h
8
R/W
80h
8
R/W
00h
8
R/W
00h
8
R/W
00h
8
R/W
00h
8
R/W
00h
8
R/W
C2h
8
R/W
00h
8
R/W
00h
8
R/W
01h
NXP Semiconductors
I/O
I/O
I/O
Section/
page
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