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Functional description
Table 17-5. Total conversion time vs. control conditions (continued)
Conversion type
Single or first continuous 8-bit
Single or first continuous 10-bit or 12-bit
Subsequent continuous 8-bit;
f
> f
BUS
ADCK
Subsequent continuous 10-bit or 12-bit;
f
> f
BUS
ADCK
Subsequent continuous 8-bit;
f
> f
BUS
ADCK
Subsequent continuous 10-bit or 12-bit;
f
> f
BUS
ADCK
The maximum total conversion time is determined by the selected clock source and the
divide ratio. The clock source is selectable by the ADC_SC3[ADICLK] bits, and the
divide ratio is specified by the ADC_SC3[ADIV] bits. For example, in 10-bit mode, with
the bus clock selected as the input clock source, the input clock divide-by-1 ratio
selected, and a bus frequency of 8 MHz, then the conversion time for a single conversion
as given below:
The number of bus cycles at 8 MHz is:
The ADCK frequency must be between f
f
maximum to meet ADC specifications.
ADCK
17.5.4 Automatic compare function
The compare function can be configured to check for an upper or lower limit. After the
input is sampled and converted, the result is added to the complement of the compare
value (ADC_CV). When comparing to an upper limit (ADC_SC2[ACFGT] = 1), if the
result is greater-than or equal-to the compare value, ADC_SC1[COCO] is set. When
comparing to a lower limit (ADC_SC2[ACFGT] = 0), if the result is less than the
compare value, ADC_SC1[COCO] is set. The value generated by the addition of the
conversion result and the complement of the compare value is transferred to ADC_R.
274
ADICLK
11
11
xx
xx
xx
/11
xx
/11
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
ADLSMP
1
5 µs + 40 ADCK + 5 bus clock cycles
1
5 µs + 43 ADCK + 5 bus clock cycles
0
0
1
1
Note
minimum and
ADCK
Max total conversion time
17 ADCK cycles
20 ADCK cycles
37 ADCK cycles
40 ADCK cycles
NXP Semiconductors
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