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Register definition
Field
PF is set at the same time as RDRF when parity is enabled (PE = 1) and the parity bit in the received
character does not agree with the expected parity value. To clear PF, read SCI_S1 and then read the SCI
data register (SCI_D).
0
No parity error.
1
Parity error.
22.4.6 SCI Status Register 2 (SCIx_S2)
This register contains one read-only status flag.
When using an internal oscillator in a LIN system, it is necessary to raise the break
detection threshold one bit time. Under the worst case timing conditions allowed in LIN,
it is possible that a 0x00 data character can appear to be 10.26 bit times long at a slave
running 14% faster than the master. This would trigger normal break detection circuitry
designed to detect a 10-bit break symbol. When the LBKDE bit is set, framing errors are
inhibited and the break detection threshold changes from 10 bits to 11 bits, preventing
false detection of a 0x00 data character as a LIN break symbol.
Address: 1868h base + 5h offset = 186Dh
Bit
7
Read
LBKDIF
Write
Reset
0
Field
7
LIN Break Detect Interrupt Flag
LBKDIF
LBKDIF is set when the LIN break detect circuitry is enabled and a LIN break character is detected.
LBKDIF is cleared by writing a 1 to it.
0
No LIN break character has been detected.
1
LIN break character has been detected.
6
RxD Pin Active Edge Interrupt Flag
RXEDGIF
RXEDGIF is set when an active edge, falling if RXINV = 0, rising if RXINV=1, on the RxD pin occurs.
RXEDGIF is cleared by writing a 1 to it.
0
No active edge on the receive pin has occurred.
1
An active edge on the receive pin has occurred.
5
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
406
SCIx_S1 field descriptions (continued)
6
5
0
RXEDGIF
0
0
SCIx_S2 field descriptions
Table continues on the next page...
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Description
4
3
RXINV
RWUID
0
0
Description
2
1
BRK13
LBKDE
0
0
NXP Semiconductors
0
RAF
0
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