Port Filter Register 0 (Port_Ioflt0) - NXP Semiconductors MC9S08SU16 Reference Manual

Field
Port Filter Division Set 3
000 LPOCLK.
001 LPOCLK/2.
010 LPOCLK/4.
011 LPOCLK/8.
100 LPOCLK/16.
101 LPOCLK/32.
110 LPOCLK/64.
111 LPOCLK/128.
4–2 Filter Division Set 2
FLTDIV2
Port Filter Division Set 2
000 BUSCLK/32.
001 BUSCLK/64.
010 BUSCLK/128.
011 BUSCLK/256.
100 BUSCLK/512.
101 BUSCLK/1024.
110 BUSCLK/2048.
111 BUSCLK/4096.
FLTDIV1 Filter Division Set 1
Port Filter Division Set 1
00 BUSCLK/2.
01 BUSCLK/4.
10 BUSCLK/8.
11 BUSCLK/16.

8.5.12 Port Filter Register 0 (PORT_IOFLT0)

This register sets the filters for input from PTA to PTC.
Address: 0h base + 18EDh offset = 18EDh
Bit 7
Read 0
Write
Reset 0
Field
7–6 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
NXP Semiconductors
PORT_FCLKDIV field descriptions (continued)
6 5
FLTC
0 0
PORT_IOFLT0 field descriptions
Table continues on the next page...
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Description
4 3
FLTB
0 0
Description
Chapter 8 Port Control (PORT)
2 1
FLTA
0 0
0
0
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