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Generator loading
26.3.8.4 Initialization
Initialize all registers and set the load okay (LDOK) bit before setting the ENABLE
(PWMEN) bit. With LDOK set, setting the PWMEN bit is first set, a reload will
immediately occur, thereby setting the PWMF bit. The PWMF bit generates an interrupt
request if the PWMRIE bit is set. In complementary channel operation, the IPOLn bits
determine whether the even or odd numbered PWM value registers control the outputs
for the first PWM cycle.
Even if LDOK is not set, setting PWMEN also sets the PWMF
bit. To prevent a core interrupt request, clear the PWMRIE bit
before setting PWMEN bit.
Setting PWMEN bit for the first time after reset without first setting LDOK loads a
prescaler divisor of one, a PWM value of $0000, and an unknown modulus. If the LDOK
bit is not set after the PWMEN bit is cleared, then set (without a RESET) the value last
loaded will be used in the PWM generated. If the deadtime registers are changed after
PWMEN or OUTCTLn bits are set, an improper deadtime insertion will occur.
Initializing the deadtime registers after setting PWMEN or OUTCTLn can cause an
improper deadtime insertion. However, the deadtime can never be shorter than the
specified value.
500
LDFQ[3:0] = 0000 = Reload Every Cycle
Up only
Counter
LDOK = 1
Modulus = 3
PWM Value = 2
PWMF = 1
PWM
Figure 26-25. Edge-Aligned modulus loading
NOTE
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
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NXP Semiconductors
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