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12.1.3.3 FLL bypassed internal (FBI)
In FLL bypassed internal mode, the FLL is enabled and controlled by the internal
reference clock, but is bypassed. The ICS supplies a clock derived from the internal
reference clock.
12.1.3.4 FLL bypassed internal low power (FBILP)
In FLL bypassed internal low power mode, the FLL is disabled and bypassed, and the
ICS supplies a clock derived from the internal reference clock.
12.1.3.5 FLL bypassed external (FBE)
In FLL bypassed external mode, the FLL is enabled and controlled by an external
reference clock, but is bypassed. The ICS supplies a clock derived from the external
reference clock source.
12.1.3.6 FLL bypassed external low power (FBELP)
In FLL bypassed external low power mode, the FLL is disabled and bypassed, and the
ICS supplies a clock derived from the external reference clock.
12.1.3.7 Stop (STOP)
In Stop mode, the FLL is disabled. The ICS does not provide any MCU clock sources.
The DCO frequency changes from the pre-stop value to its reset
value and the FLL needs to reacquire the lock before the
frequency is stable. Timing sensitive operations must wait for
the FLL acquisition time, t
12.2 External signal description
There are no ICS signals that connect off chip.
NXP Semiconductors
NOTE
Acquire
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 12 Internal Clock Source (ICS)
, before executing.
191
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