Pwm Fault Control Register: Low (Pwm_Fctrll) - NXP Semiconductors MC9S08SU16 Reference Manual

Memory Map and Register Descriptions
Field
0010 Every 3 PWM opportunities
0011 Every 4 PWM opportunities
0100 Every 5 PWM opportunity
0101 Every 6 PWM opportunities
0110 Every 7 PWM opportunities
0111 Every 8 PWM opportunities
1000 Every 9 PWM opportunity
1001 Every 10 PWM opportunities
1010 Every 11 PWM opportunities
1011 Every 12 PWM opportunities
1100 Every 13 PWM opportunity
1101 Every 14 PWM opportunities
1110 Every 15 PWM opportunities
1111 Every 16 PWM opportunities
3 Half Cycle Reload
HALF
This read/write bit enables half-cycle reloads in center-aligned PWM mode. This bit has no effect on edge-
aligned PWMs.
0 Half-cycle reloads disabled.
1 Half-cycle reloads enabled.
Reserved This field is reserved.
This read-only field is reserved and always has the value 0.

26.4.3 PWM Fault Control Register: Low (PWM_FCTRLL)

Address: 40h base + 2h offset = 42h
Bit 7
Read
FIE3
Write
Reset
0
Field
7 FAULT3 Pin Interrupt Enable
FIE3
This read/write bit enables interrupt requests generated by the filtered FAULT3 pin. A reset clears FIE3.
NOTE: The fault protection circuit is independent of the FIE3 bits and is always active. If a fault is
0 FAULT3 interrupt requests disabled
1 FAULT3 interrupt requests enabled
6 FAULT3 Pin Clearing Mode
FMODE3
This read/write bit selects automatic or manual clearing of FAULT3 pin faults. A reset clears FMODE3.
508
PWM_CTRLH field descriptions (continued)
6 5
FMODE3 FIE2
0 0
PWM_FCTRLL field descriptions
detected, the PWM pins are disabled according to the PWM disable mapping register.
Table continues on the next page...
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Description
4 3
FMODE2 FIE1
0 0
Description
2 1
FMODE1 FIE0
0 0
NXP Semiconductors
0
FMODE0
0