Table of Contents
Advertisement
Memory map and register description
27.4.3 BDC Breakpoint Register: Low (BDC_BKPTL)
BDC_BKPTH and BDC_BKPTL registers hold the address for the hardware breakpoint
in the BDC. The BDC_SCR[FTS] and BDC_SCR[BKPTEN] bits are used to enable and
configure the breakpoint logic. Dedicated serial BDC commands (READ_BKPT and
WRITE_BKPT) are used to read and write the BDC_BKPTH and BDC_BKPTL register.
Breakpoints are normally set while the target MCU is in background debug mode before
running the user application program. However, since READ_BKPT and WRITE_BKPT
are foreground commands, they could be executed even while the user program is
running.
Address: 0h base + 2h offset = 2h
Bit
7
Read
Write
Reset
0
Field
A[7:0]
Low 8-bit of hardware breakpoint address.
27.4.4 System Background Debug Force Reset Register
(BDC_SBDFR)
This register contains a single write-only control bit. A serial background mode
command such as WRITE_BYTE must be used to write to SBDFR. Attempts to write
this register from a user program are ignored. Reads always return 0x00.
Address: 0h base + 3h offset = 3h
Bit
7
Read
Write
Reset
0
Field
7–1
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
0
Background Debug Force Reset
BDFR
546
6
5
0
0
BDC_BKPTL field descriptions
6
5
0
0
BDC_SBDFR field descriptions
Table continues on the next page...
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
4
3
A[7:0]
0
0
Description
4
3
0
0
0
Description
2
1
0
0
2
1
BDFR
0
0
NXP Semiconductors
0
0
0
0
0
Advertisement
Table of Contents
