NXP Semiconductors MC9S08SU16 Reference Manual

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MC9S08SU16 Reference Manual

Supports: MC9S08SU16VFK MC9S08SU8VFK

Document Number: MC9S08SU16RM

Rev. 5, 4/2017

Table of Contents

Summary of Contents for NXP Semiconductors MC9S08SU16

Page 1 MC9S08SU16 Reference Manual Supports: MC9S08SU16VFK MC9S08SU8VFK Document Number: MC9S08SU16RM Rev. 5, 4/2017...
Page 2 MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 3: Table Of Contents
Analog modules............................. 38 2.2.7 Timer modules............................... 38 2.2.8 Communication interfaces..........................39 2.2.9 Human-machine interfaces..........................39 MCU block diagram..............................40 Orderable part numbers..............................41 Chapter 3 Memory Memory map.................................43 Reset and interrupt vector assignments.........................44 MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 4 IRQ Memory Map and Register Descriptions......................63 4.4.1 Interrupt Pin Request Status and Control Register (IRQ_SC)............... 63 Chapter 5 Clock management Clock module................................65 System clock distribution..............................65 Internal clock source (ICS)............................67 20 kHz low-power oscillator (LPO)..........................68 MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 5 Internal pullup/pulldown enable........................... 84 Input glitch filter................................85 Memory map and register definition..........................86 8.5.1 Port A Data Register (PORT_PTAD)......................86 8.5.2 Port B Data Register (PORT_PTBD)......................87 8.5.3 Port C Data Register (PORT_PTCD)......................87 MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 6 Memory map and register definition..........................104 9.8.1 System Reset Status Register (SIM_SRS)..................... 105 9.8.2 System Background Debug Force Reset Register (SIM_SBDFR)..............107 9.8.3 System Device Identification Register: High (SIM_SDIDH)................107 9.8.4 System Device Identification Register: Low (SIM_SDIDL).................108 MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 7 Universally Unique Identifier Register 7 (SIM_UUID7)................126 Chapter 10 Central processor unit 10.1 Introduction...................................127 10.1.1 Features................................127 10.2 Programmer's Model and CPU Registers........................128 10.2.1 Accumulator (A)............................128 10.2.2 Index Register (H:X)............................129 MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 8 Direct to Indexed, Post-Increment..................... 137 10.4 Operation modes................................137 10.4.1 Stop mode..............................137 10.4.2 Wait mode..............................137 10.4.3 Background mode............................138 10.4.4 Security mode..............................139 10.5 HCS08 V6 Opcodes..............................141 10.6 Special Operations................................ 141 MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 9 Unsecuring the MCU using backdoor key access..............166 11.3.8.2 Unsecuring the MCU using BDM..................... 167 11.3.8.3 Mode and security effects on flash command availability............167 11.3.9 Flash commands.............................167 11.3.9.1 Flash commands.........................167 11.3.10 Flash command summary..........................168 MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 10 Flash Common Command Object Register: Low (FTMRH_FCCOBLO)............ 187 11.4.9 Flash Option Register (FTMRH_FOPT)....................... 187 Chapter 12 Internal Clock Source (ICS) 12.1 Introduction...................................189 12.1.1 Features................................189 12.1.2 Block diagram..............................190 12.1.3 Modes of operation............................190 MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 11 FLL bypassed external low power (FBELP)................199 12.4.1.7 Stop............................199 12.4.2 Mode switching..............................199 12.4.3 Bus frequency divider............................ 200 12.4.4 Low-power field usage...........................200 12.4.5 Internal reference clock..........................200 12.4.6 Fixed frequency clock............................ 201 12.4.7 FLL lock and clock monitor...........................201 MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 12 MTIM16 counter register high (MTIM_CNTH)................... 211 13.5.4 MTIM16 counter register low (MTIM_CNTL).....................212 13.5.5 MTIM16 modulo register high (MTIM_MODH)..................213 13.5.6 MTIM16 modulo register low (MTIM_MODL)................... 214 13.6 Functional Description ..............................214 13.6.1 MTIM16 Operation Example ........................216 Chapter 14 MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 13 Configuration Register (PMC_VREFHCFG)..................227 REFH 14.7.9 VREFH Low Voltage Warning (LVW) Configuration Register (PMC_VREFHLVW).......228 14.7.10 Status Register (PMC_STAT)........................228 14.8 Functional description..............................229 14.8.1 Voltage regulators............................229 14.8.1.1 VREGVDDX..........................229 14.8.1.2 VREGVDDF..........................229 MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 14 External signals description............................237 15.4 Register definition.................................237 15.5 Memory Map and Registers............................237 15.5.1 KBI Status and Control Register (KBI_SC)....................238 15.5.2 KBI Pin Enable Register (KBI_PE).......................239 15.5.3 KBI Edge Select Register (KBI_ES)......................239 MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 15 CRC Polynomial Register: Low 1 (CRC_PL1)..................... 249 16.3.8 CRC Polynomial Register: Low 0 (CRC_PL0)..................... 250 16.3.9 CRC Control register (CRC_CTRL)......................250 16.4 Functional description..............................251 16.4.1 CRC initialization/reinitialization........................251 16.4.2 CRC calculations............................252 16.4.2.1 16-bit CRC..........................252 16.4.2.2 32-bit CRC..........................252 MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 16 Status and Control Register 3 (ADCx_SC3)....................265 17.4.4 Status and Control Register 4 (ADCx_SC4)....................266 17.4.5 Conversion Result High Register (ADCx_RH)..................... 267 17.4.6 Conversion Result Low Register (ADCx_RL)....................268 17.4.7 Compare Value High Register (ADCx_CVH)....................269 MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 17 Pseudo-code example.........................282 17.7 Application information..............................283 17.7.1 External pins and routing..........................283 17.7.1.1 Analog supply pins........................283 17.7.1.2 Analog reference pins........................ 283 17.7.1.3 Analog input pins........................284 17.7.2 Sources of error.............................. 285 17.7.2.1 Sampling error..........................285 MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 18 18.10.5 DAC Control Register (CMP_DACCR)......................299 18.10.6 MUX Control Register (CMP_MUXCR)...................... 300 18.10.7 MUX Pin Enable Register (CMP_MUXPE)....................301 18.11 CMP Functional Description............................301 18.11.1 CMP Functional Modes..........................301 18.11.1.1 Disabled Mode (# 1)........................303 MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 19 18.17 DAC Interrupts................................316 Chapter 19 FlexTimer Module (FTM) 19.1 Chip specific FlexTimer module..........................317 19.2 Introduction...................................318 19.2.1 FlexTimer philosophy............................ 318 19.2.2 Features................................318 19.2.3 Modes of operation............................319 19.2.4 Block diagram..............................319 MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 20 19.5.4 Input capture mode............................332 19.5.5 Output compare mode............................ 333 19.5.6 Edge-aligned PWM (EPWM) mode......................335 19.5.7 Center-aligned PWM (CPWM) mode......................336 19.5.8 Update of the registers with write buffers......................338 19.5.8.1 MODH:L registers........................338 MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 21 Pulse Width Timer Counter Register: High (PWTx_CNTH)................ 351 20.4.8 Pulse Width Timer Counter Register: Low (PWTx_CNTL)................. 351 20.5 Functional description..............................352 20.5.1 PWT counter and PWT clock pre-scaler......................352 20.5.2 Edge detection and capture control........................ 352 MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 22 21.4.10 I2C Address Register 2 (I2C_A2)........................374 21.4.11 I2C SCL Low Timeout Register High (I2C_SLTH)..................375 21.4.12 I2C SCL Low Timeout Register Low (I2C_SLTL)..................375 21.4.13 I2C Status register 2 (I2C_S2)........................376 21.5 Functional description..............................376 MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 23 Stop Detect Interrupt........................388 21.5.6.4 Exit from low-power/stop modes....................388 21.5.6.5 Arbitration lost interrupt......................388 21.5.6.6 Timeout interrupt in SMBus...................... 389 21.5.7 Address matching wake-up..........................389 21.5.8 Double buffering mode..........................390 21.6 Initialization/application information........................... 391 MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 24 Receiver functional description........................412 22.5.3.1 Data sampling technique......................413 22.5.3.2 Receiver wake-up operation.......................414 22.5.4 Interrupts and status flags..........................415 22.5.5 Baud rate tolerance............................416 22.5.5.1 Slow data tolerance........................416 22.5.5.2 Fast data tolerance........................418 MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 25 PDB1 Comparison High Register (PDB_CMPH1)..................429 23.6.8 PDB1 Counter High/Low (PDB_CNT1)....................... 430 Chapter 24 Inter-peripheral Crossbar Switch (XBAR) 24.1 Introduction...................................431 24.2 Features..................................431 24.3 Block diagram................................431 24.4 Memory Map and Register Descriptions........................432 MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 26 25.6.15 Virtual Network Phase Detection Control (GDU_PHASECTRL)..............451 25.6.16 Current Sensor and Overcurrent Protection Control Register (GDU_CURCTRL)........452 25.6.17 LIMIT0 CMP Control Register 0 (GDU_LIMIT0CR0)................452 25.6.18 LIMIT0 CMP Control Register 1 (GDU_LIMIT0CR1)................453 25.6.19 LIMIT0 CMP Filter Period Register (GDU_LIMIT0FPR)................454 MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 27 GCMP diagram.......................... 465 25.7.4.2 GCMP block diagram........................ 466 25.7.4.3 GCMP functional modes......................468 25.7.4.4 Power modes..........................477 25.7.4.5 Startup and operation......................... 478 25.7.4.6 Low pass filter..........................478 25.8 GCMP interrupts................................480 Chapter 26 Pulse Width Modulator (PWM) MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 28 Fault pin filter..........................502 26.3.9.2 Automatic fault clearing......................503 26.3.9.3 Manual fault clearing......................... 503 26.4 Memory Map and Register Descriptions........................504 26.4.1 PWM Control Register: Low (PWM_CTRLL)..................... 506 26.4.2 PWM Control Register: High (PWM_CTRLH).................... 507 MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 29 26.4.23 PWM Channel Control Register: High (PWM_CCTRLH)................524 26.4.24 PWM Pulse Edge Control Register: Low (PWM_PECTRLL)..............524 26.4.25 PWM Compare Invert Register: High (PWM_CINVH)................525 26.5 Resets.................................... 526 26.6 Clocks................................... 526 26.7 Interrupts..................................527 Chapter 27 Development support 27.1 Introduction...................................529 MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 30 Modes of operation............................550 28.1.3 Block diagram..............................550 28.2 Signal description................................551 28.3 Memory map and registers............................551 28.3.1 Debug Comparator A High Register (DBG_CAH)..................552 28.3.2 Debug Comparator A Low Register (DBG_CAL)..................553 MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 31 Begin- and end-trigger....................... 569 28.4.4.2 Arming the DBG module......................569 28.4.4.3 Trigger modes..........................570 28.4.5 FIFO................................572 28.4.5.1 Storing data in FIFO........................573 28.4.5.2 Storing with begin-trigger......................573 28.4.5.3 Storing with end-trigger......................573 MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 32 Section number Title Page 28.4.5.4 Reading data from FIFO......................573 28.4.6 Interrupt priority.............................574 28.5 Resets.................................... 575 MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 33: About This Document
Hexadecimal number. For example, the hexadecimal equivalent of the number 60 is written 3Ch. In some cases, hexadecimal numbers are shown with the prefix 0x. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 34: Typographic Notation
In some cases, deasserted signals are described as negated. reserved Refers to a memory space, register, or field that is either reserved for future use or for which, when written to, the module or chip behavior is unpredictable. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 35: Introduction
• Interrupt priority controller (IPC) • Inter-module crossbar Memories • Up to 16 KB flash memory for SU16 and up to 8 KB flash memory for SU8 Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 36: S08L Core Modules
The on-chip ICE system is optimized for the HCS08 8-bit architecture and supports 64 KB of memory space. 2.2.2 System modules The following system modules are available on this device. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 37: Memories And Memory Interfaces
ICS module containing an internal reference clock (ICSIRCLK) and a frequency locked loop (FLL). Low-Power Oscillator (LPO) The PMC module contains a 20 kHz low-power oscillator which acts as a standalone low-frequency clock source in all modes. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 38: Security And Integrity Modules
• Operation of FTM channels as pairs with equal outputs or independent channels with independent outputs • Programmable interrupt on input capture, reference compare, overflowed counter Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 39: Communication Interfaces
Management Bus (SMBus) Specification, version 2. Serial communications interface (SCI) SCI is used to connect to the RS232 serial input/output port of a personal computer or workstation and communicate with other embedded controllers. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 40: Mcu Block Diagram
Predriver + 5 CMP + 2 OPAMP 12-bit Inter Module Crossbar Inputs Inter Module Crossbar Outputs GPIO Port A&B&C and Peripheral MUX Driver Analog Inpus Package Pins Package Pins Motor Drive Figure 2-1. Block diagram MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 41: Orderable Part Numbers
Part number Pin count Package Total flash Temperature range frequency memory MC9S08SU16VFK 40 MHz 16 KB 768 bytes -40 to 105 °C MC9S08SU8VFK 40 MHz 8 KB 768 bytes -40 to 105 °C MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 42 Orderable part numbers MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 43: Memory
• Unimplemented: 0x1900–0xBFFF (SU16) and 0x1900–0xDFFF (SU8) • Flash memory (SU16): 0xC000–0xFFFF • Flash array: 0xC000–0FFBF • Vector table: 0xFFC0–0xFFFF • Flash memory (SU8): 0xE000–0xFFFF • Flash array: 0xE000–0FFBF • Vector table: 0xFFC0–0xFFFF MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 44: Reset And Interrupt Vector Assignments
Table 3-1. Reset and interrupt vectors Address Vector number Vector Vector name Module Source (high/low) 0xFFC0:FFC1 Vnvm CCIF 0xFFC2:FFC3 Viic Or'ed all flags 0xFFC4:FFC5 Vkbi Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 45 0xFFEC:FFED PWT1 data ready Vpwt1rdy PWT1 PWTRDY 0xFFEE:FFEF PWT0 overflow Vpwt0ovf PWT0 PWTOV 0xFFF0:FFF1 PWT0 data ready Vpwt0rdy PWT0 PWTRDY 0xFFF2:FFF3 PWM reload Vmcpwm mcPWM PWMF Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 46: Register Addresses Assignments
• High-page registers are used much less often, so they are located above 0x1800 in the memory map. This leaves room in the direct page for more frequently used registers and variables. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 47 PWT0_PPL, PWT0_NPH, ― 0x0030—0x0037 PWT0 PWT0_NPL, PWT0_CNTH, PWT0_CNTL PWT1_CS, PWT1_CR, PWT1_PPH, PWT1_PPL, PWT1_NPH, ― 0x0038—0x003F PWT1 PWT1_NPL, PWT1_CNTH, PWT1_CNTL PWM_CTRLL, PWM_CTRLH, ― 0x0040—0x005F PWM_FCTRLL, PWM_FCTRLH, PWM_FLTACKL, PWM_FLTACKH, Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 48 SIM_PORREG2, SIM_PORREG3, ― 0x1810—0x1817 SIM register filer SIM_PORREG4, SIM_PORREG5, SIM_PORREG6, SIM_PORREG7 ― ― 0x1818—0x181F Reserved PWM_CNFGL, PWM_CNFGH, PWM_CCTRLL, PWM_CCTRLH, ― 0x1820—0x1829 PWM_PECTRLL, PWM_CINVH ― ― 0x182A—0x182F Reserved Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 49 ― ― 0x18BD—0x18BF Reserved DBG_CAH, DBG_CAL, DBG_CBH, DBG_CBL, DBG_CCH, DBG_CCL, ― 0x18C0—0x18CF DBG_FH, DBG_FL, DBG_CAX, DBG_CBX, DBG_CCX, DBG_FX, DBG_C, DBG_T, DBG_S, DBG_CNT ― 0x18D0—0x18DF XBAR XBAR_SEL0—XBAR_SEL15 Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 50 Reserved — — — — — — — — FPOPE 0xFF7C NV_FPROT — FPHDIS — — — 0xFF7D Reserved — — — — — — — — 0xFF7E NV_FOPT 0xFF7F NV_FSEC KEYEN MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 51: Random-Access Memory (Ram)
The flash module includes a memory controller that executes commands to modify flash memory contents. The user interface to the memory controller consists of the indexed flash common command object (FCCOB) MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 52: System Register File
3.6 System register file This device includes a 8-byte register file that is powered in all power modes. Also, it retains contents during low-voltage detect (LVD) events and is only reset during a power-on reset. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 53: Interrupts
[I] is automatically set to prevent another interrupt from interrupting the ISR itself, which is called nesting of interrupts. Normally, the [I] is restored to 0 when the CCR is restored from the value stacked MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 54: Interrupt Stack Frame
CCR was saved. The PC value that is stacked is the address of the instruction in the main program that would have executed next if the interrupt had not occurred. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 55: Hardware Nested Interrupt
• Higher or equal priority level interrupt requests can preempt lower priority interrupts being serviced. • Automatic update of interrupt priority mask with being serviced interrupt source priority level when the interrupt vector is being fetched. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 56 The IPC works with the existing HCS08 interrupt mechanism to allow nested interrupts with programmable priority levels. This module also allows implementation of preemptive interrupt according to the programmed interrupt priority with minimal software overhead. The IPC consists of three major functional blocks: MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 57: Interrupt Priority Level Register
ILR corresponding to that interrupt source. The original value of the IPM will be saved onto IPMPS for restoration after the interrupt service routine completes execution. When the interrupt service routine completes execution, the user restore the MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 58: Integration And Application Of The Ipc
• As an interrupt of the same priority level is allowed to pass through IPC to HCS08 CPU, the flag generating the interrupt must be cleared before doing CLI to enable preemptive interrupts. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 59: Ipc Memory Map And Register Descriptions
Address: Eh base + 0h offset = Eh Read IPCE Write PULIPM Reset IPC_SC field descriptions Field Description Interrupt Priority Controller Enable IPCE This bit enables/disables the interrupt priority controller module. Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 60: Interrupt Priority Mask Pseudo Stack Register (Ipc_Ipmps)
This register is used to store the previous interrupt priority mask level temporarily when the currently active interrupt is executed. Address: Eh base + 1h offset = Fh Read IPM3 IPM2 IPM1 IPM0 Write Reset MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 61: Interrupt Level Setting Registers N (Ipc_Ilrsn)
This field sets the interrupt level for interrupt source n*4+1. ILRn0 Interrupt Level Register for Source n*4+0 This field sets the interrupt level for interrupt source n*4+0. 4.3 IRQ The IRQ (interrupt request) module provides a maskable interrupt input. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 62: Features
Xbar_OUT15 for edge-only or edge-and-level events. When the MCU is in stop mode and system clocks are shut down, a separate asynchronous path is used so that the IRQ, if enabled, can wake the MCU. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 63: Configuration Options
This direct page register includes status and control bits, which are used to configure the IRQ function, report status, and acknowledge IRQ events. Address: 7Fh base + 0h offset = 7Fh Read IRQF IRQPDD IRQEDG IRQPE IRQIE IRQMOD Write IRQACK Reset MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 64 Interrupt requested whenever IRQF = 1. IRQ Detection Mode IRQMOD This read/write control bit selects either edge-only detection or edge-and-level detection. IRQ event on falling/rising edges only. IRQ event on falling/rising edges and low/high levels. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 65: Clock Management
• Low-power oscillator (LPO) module — The on-chip low-power oscillator in PMC module providing 20 kHz reference clock to windowed COP watchdog (WCOP) to meet IEC60730 safety standard. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 66 • Frequency-locked loop (FLL) output There are three clocks that are derived from this clock source: • MSTRCLK — Master clock is the clock source for CPU and RAM and DBG and system/ bus clock MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 67: Internal Clock Source (Ics)
Whichever clock source is chosen, ICSCLK is the output from a bus clock divider (BDIV), which allows a lower clock frequency to be derived. Key features of the ICS module are: • Frequency-locked loop (FLL) is trimmable for accuracy MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 68: 20 Khz Low-Power Oscillator (Lpo)
System Clock Gating Control registers (SIM_SCGCx, x=1, 2, 3). Any peripheral with a gated clock cannot be used unless its clock is enabled. Writing to the registers of a peripheral with a disabled clock has no effect. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 69 When clocks to a peripheral are re- enabled, the peripheral registers need to be re-initialized by user software. In stop modes, the bus clock is disabled for all gated peripherals, regardless of the setting in SIM_SCGCx (x=1,2,3) registers. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 70 Peripheral clock gating MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 71: Power Management
This is the normal operating mode. In this mode, the CPU executes code from internal memory with execution beginning at the address fetched from memory at 0xFFFE: 0xFFFF after reset. The power supply is fully regulating and all peripherals can be active in run mode. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 72: Wait Mode
Entry into the active background mode from run mode is enabled if the BDC_SCR[ENBDM] bit is set. This register is described in the development support. If BDC_SCR[ENBDM] is set when the CPU executes a STOP instruction, the system MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 73: Power Modes Behaviors
Standby Standby Flash Standby Standby Standby Optional on Optional on States held SCI / I2C Standby FTM / PWT / PWM / MTIM Standby WCOP Optional on Standby Standby Standby Standby Standby MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 74: Bandgap Reference
This reference voltage acts as an ideal reference voltage for accurate measurements. This device also includes a high accuracy voltage reference VREFH (~4.2 V). This reference provides high accuracy reference to ADC and 6-bit DAC inside CMP. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 75: Signal Multiplexing And Signal Descriptions
1. A given peripheral function must be assigned to a maximum of one package pin. Do not program the same function to more than one pin. 2. To ensure the best signal timing for a given peripheral's interface, choose the pins in closest proximity to each other. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 76: Pinout
KBI4 PTA3 AMP1_M/ CLKOUT XB_OUT1 PTA3/ ADC1AD1 KBI3 PTA2 AMP1_P/ XB_IN1 XB_OUT0 PTA2/ CMP2/ KBI2 ADC1AD0 PTA1 AMP0_M/ XB_OUT0 XB_IN1 PTA1/ CMP1/ KBI1 ADC0AD1 PTA0 AMP0_P/ CLK_IN XB_IN0 PTA0/ CMP0/ KBI0 ADC0AD0 MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 77: Signal Description Table
Default Supply Ground RESET_b RESET 0–5 Default Reset, A direct hardware reset on the internal processor. When RESET is Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 78 ALT2 Crossbar module output 1 PTA7/ KBI7 PORT/K PTA7/KBIP7 ALT3 This GPIO pin can be individually programmed as an input or output pin with KBI functionality Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 79 XBAR_OUT 0 ALT2 Crossbar module output 0 PTA2/KBI2 PORT/K PTA2/KBIP2 ALT3 This GPIO pin can be individually programmed as an input or output pin with KBI functionality Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 80 ADC0AD3: Input to channel 3 ADC1AD3 / ADC1/G CMP1 down of ADC0; GDU_CMP ADC1AD3: Input to channel 3 of ADC1; GDU_CMP1: GDU Phase comparator 1 positive input Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 81: Pinout
The following figures show the pinout diagrams for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see Signal multiplexing and pin assignments. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 82 Pinout PTA1 PTB5 PTA2 PWM_UH PTA3 PWM_VH PTA4 PWM_WH PTA5 VCLAMP PTA6 Figure 7-1. 24-pin QFN pinout diagram MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 83: Port Control (Port)
‘1’ when BKGD/RESET) ALT1 out data ALT2 out data PTAD0 0/1/PTAD0 Digital peripheral or CPU read Synchronizer & BUS clock PTA0 Glitch filter FLTDIV1 FLTDIV2 FLTDIV3 Analog peripheral Figure 8-1. Normal I/O structure MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 84: Port Data And Data Direction
If an SDA, SCL, RX, TX, KBI, or TCLK function is selected and enabled on a pin, the pullup configuration for that pin still works. The internal pullup device is enabled when pin select as BKGD/RESET function. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 85: Input Glitch Filter
It passes to internal circuitry. Pass to internal rate 100% Input high/low width 1(FLTxxx period) 2(FLTxxx period) Note: FLTxxx is contents in register PORT_IOFLTn (n=0-2). Figure 8-2. Input glitch filter MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 86: Memory Map And Register Definition
A write of valid data to this register must occur before setting the direction control bit of an associated port pin. This ensures that the pin will not be driven with an incorrect data value. Address: 0h base + 0h offset = 0h Read PTAD Write Reset MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 87: Port B Data Register (Port_Ptbd)
Writes are latched into all bits of this register. For port B pins that are configured as outputs, the logic level is driven out of the corresponding MCU pin. 8.5.3 Port C Data Register (PORT_PTCD) Reading and writing of parallel I/O is accomplished through this register. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 88: Port A Direction Register (Port_Ptadd)
These bits control the direction of port A pins and what is read for PTAD reads. Pin is configured as general-purpose input, for the GPIO function. Pin is configured as general-purpose output, for the GPIO function. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 89: Port B Direction Register (Port_Ptbdd)
These bits control the direction of port C pins and what is read for PTCD reads. Pin is configured as general-purpose input, for the GPIO function. Pin is configured as general-purpose output, for the GPIO function. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 90: Port A Pullup Enable Register (Port_Ptape)
Internal pullup device disabled for port A bit n. Internal pullup device enabled for port A bit n. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 91: Port B Pullup/Pulldown Enable Register (Port_Ptbpe)
Internal pullup device disabled for port C bit n. Internal pullup device enabled for port C bit n. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 92: Port B High Drive Strength Selection Register (Port_Ptbhd)
(they will pass to the internal circuitry). Address: 0h base + 18ECh offset = 18ECh Read FLTDIV3 FLTDIV2 FLTDIV1 Write Reset PORT_FCLKDIV field descriptions Field Description 7–5 Filter Division Set 3 FLTDIV3 Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 93: Port Filter Register 0 (Port_Ioflt0)
FLTB FLTA Write Reset PORT_IOFLT0 field descriptions Field Description 7–6 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 94: Port Filter Register 1 (Port_Ioflt1)
Select FLTDIV1, and will switch to FLTDIV3 in stop mode automatically. Select FLTDIV2, and will switch to FLTDIV3 in stop mode automatically. FLTDIV3 Reserved This field is reserved. This read-only field is reserved and always has the value 0. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 95: Port Filter Register 2 (Port_Ioflt2)
FLTDIV1 FLTDIV2 BUSCLK 3–2 Filter Selection For Input from SDA and SCL. FLTI2C No filter FLTDIV1 FLTDIV2 BUSCLK FLTXBI Filter Selection For Input from XB_IN0 and XB_IN1 No filter FLTDIV1 FLTDIV2 FLTDIV3 MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 96 Memory map and register definition MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 97: System Integration Module (Sim)
• Input clock option: BUSCLK (20 MHz); ICSIRCLK (up to the 32 kHz), LPOCLK (up to the 20 kHz), CLKIN (40 MHz) • WCOP is a part of SIM. Its register set is a subset of SIM registers. Module Instances: • One MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 98: System Device Identification (Sdid)
• Loss of clock reset (LOC) • Flash illegal access detect (FILA) Each of these sources, with the exception of the background debug forced reset, has an associated bit in the system reset status (SRS) register. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 99: Computer Operating Properly (Cop) Watchdog
COP operation. Even if the application will use the reset default settings of SOPT1[COPT], SOPT1[COPCLKS], and SOPT1[COPW] bits, the user must write to the write-once SOPT1 register during reset initialization to lock in the settings. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 100: System Options
(SOPT1[COPW] = 1). System options 9.6.1 BKGD pin After POR, PTB7/CLKOUT/BKGD/MS pin functions as BKGD output. Other functions are selected by SIM_MUXPTBH[MUXPTB7]. This pin is an output only when configured as PTB7. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 101: Reset_B Pin Enable
• The following table summarizes the signal connection of XBAR. Table 9-2. XBAR module input signals from Module XBAR_INx Function Package Pin XBAR_IN0 XB_IN0 Package Pin XBAR_IN1 XB_IN1 Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 102 ADC0 hardware trigger input ADC1 XBAR_OUT3 ADC1 Hardware trigger input FTM Channel0 XBAR_OUT4 FTM_Ch0 input capture or output FTM Channel1 XBAR_OUT5 FTM_Ch1 input capture or output Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 103: Module To Module Interconnects
GDU Predriver Phase B Top PWM3 GDU Predriver Phase B Bottom PWM4 GDU Predriver Phase C Top PWM5 GDU Predriver Phase C Bottom Limit CMP0 OUT PWM Fault2 Limit CMP1 OUT PWM Fault3 MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 104: Memory Map And Register Definition
9.8.16/121 1880 Illegal Address Register: High (SIM_ILLAH) Undefined 9.8.17/122 1881 Illegal Address Register: Low (SIM_ILLAL) Undefined 9.8.18/122 18F8 Universally Unique Identifier Register 0 (SIM_UUID0) Undefined 9.8.19/123 Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 105: System Reset Status Register (Sim_Srs)
(LVR) status bit is also set to indicate that the reset occurred while the internal supply was below the LVR threshold. NOTE: This bit POR to 1, LVR to uncertain value and reset to 0 at any other conditions. Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 106 Reset caused by LVD trip or POR. Flash Illegal Access FILA Reset was caused by an flash illegal access. Reset not caused by an flash illegal access. Reset caused by flash illegal access. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 107: System Background Debug Force Reset Register (Sim_Sbdfr)
HCS08 derivative and revision number. This allows the development software to recognize where specific memory blocks, registers, and control bits are located in a target MCU. Address: 1800h base + 2h offset = 1802h Read Reserved Write Reset MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 108: System Device Identification Register: Low (Sim_Sdidl)
These write-once bits selects the timeout period of the COP. COPT along with SOPT1[COPCLKS] defines the COP timeout period as described in Computer operating properly (COP) watchdog. Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 109 This write-once bit defaults to 0 after reset, which disables stop mode. If stop mode is disabled and a user program attempts to execute a STOP instruction, an illegal opcode reset occurs. Stop mode disabled. Stop mode enabled. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 110: System Options Register 2 (Sim_Sopt2)
This bit enables bus clock output on PTB7 via an optional prescalar. Bus. Bus divided by 2. Bus divided by 4. Bus divided by 8. Bus divided by 16. Bus divided by 32. Bus divided by 64. Bus divided by 128. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 111: System Port A Pin Multiplexing Control Register: Low (Sim_Muxptal)
Pin Mux Control MUXPTA2 The corresponding pin is configured in the following pin muxing slot: Alternative 0. Alternative 1. Alternative 2. Alternative 3. 3–2 Pin Mux Control MUXPTA1 Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 112: System Port A Pin Multiplexing Control Register: High (Sim_Muxptah)
“RX and CLK_IN” function at different location must not be selected at the same time to prevent signal override or modulation. Address: 1800h base + 7h offset = 1807h Read MUXPTA7 MUXPTA6 MUXPTA5 MUXPTA4 Write Reset MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 113: System Port B Pin Multiplexing Control Register: Low (Sim_Muxptbl)
The shared analog pin functions can work together if they’re enabled separately because they’re directly connected to internal analog modules separately. They still work even when pin Muxing mode is configured for digital pins. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 114: System Port B Pin Multiplexing Control Register: High (Sim_Muxptbh)
ALT0 to ALT3. Default is ALT0 function, When the Pin Muxing mode is configured for analog pins, all the digital functions on that pin are disabled, including the pullup/output/input. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 115 The corresponding pin is configured in the following pin muxing slot: Alternative 0. Alternative 1. Alternative 2. Alternative 3. MUXPTB4 Pin Mux Control The corresponding pin is configured in the following pin muxing slot: Alternative 0. Alternative 1. Alternative 2. Alternative 3. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 116: System Port C Pin Multiplexing Control Register: Low (Sim_Muxptcl)
MCU's run and wait currents. NOTE User software must disable the peripheral before disabling the clocks to the peripheral. When clocks are re-enabled to a peripheral, the peripheral registers need to be re-initialized by user software. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 117: System Clock Gating Control 2 Register (Sim_Scgc2)
This register contains control bits to enable or disable the bus clock to the CMP0, GDU, ADC, IRQ, PDB and KBI modules. Gating off the clocks to unused peripherals is used to reduce the MCU's run and wait currents. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 118 Reserved This read-only field is reserved and always has the value 0. PDB Clock Gate Control This bit controls the clock gate to the PDB module. Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 119: System Clock Gating Control 3 Register (Sim_Scgc3)
Bus clock to the PWM module is disabled. Bus clock to the PWM module is enabled. MTIM Clock Gate Control MTIM This bit controls the clock gate to the MTIM module. Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 120: System Clock Divider Register (Sim_Scdiv)
This read-only field is reserved and always has the value 0. Clock 1 output divider value DIV1 This field sets the divide value for the core/system clock. Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 121: System Por Register (Sim_Porregn)
Address: 1800h base + 10h offset + (1d × i), where i=0d to 7d Read PORREG Write Reset SIM_PORREGn field descriptions Field Description PORREG Power-on-reset only registers These 8 byte registers can only be reset by power-on. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 122: Illegal Address Register: High (Sim_Illah)
The ILLAL is a read-only register containing the low 8-bit of the illegal address of ILAD reset. Address: 1800h base + 81h offset = 1881h Read ADDR[7:0] Write Reset * Notes: • x = Undefined at reset. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 123: Universally Unique Identifier Register 0 (Sim_Uuid0)
The read-only UUIDx registers contain a series of 63-bit number to identify the unique device in the family. Address: 1800h base + F9h offset = 18F9h Read ID[55:48] Write Reset * Notes: • x = Undefined at reset. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 124: Universally Unique Identifier Register 2 (Sim_Uuid2)
Address: 1800h base + FBh offset = 18FBh Read ID[39:32] Write Reset * Notes: • x = Undefined at reset. SIM_UUID3 field descriptions Field Description ID[39:32] Universally Unique Identifier MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 125: Universally Unique Identifier Register 4 (Sim_Uuid4)
Address: 1800h base + FDh offset = 18FDh Read ID[23:16] Write Reset * Notes: • x = Undefined at reset. SIM_UUID5 field descriptions Field Description ID[23:16] Universally Unique Identifier MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 126: Universally Unique Identifier Register 6 (Sim_Uuid6)
Address: 1800h base + FFh offset = 18FFh Read ID[7:0] Write Reset * Notes: • x = Undefined at reset. SIM_UUID7 field descriptions Field Description ID[7:0] Universally Unique Identifier MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 127: Central Processor Unit
• Relative — 8-bit signed offset to branch destination • Immediate — Operand in next object code byte(s) • Direct — Operand in memory at 0x0000–0x00FF • Extended — Operand anywhere in 64-Kbyte address space MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 128: Programmer's Model And Cpu Registers
The A accumulator is a general-purpose 8-bit register. One input operand from the arithmetic logic unit (ALU) is connected to the accumulator, and the ALU results are often stored into the A accumulator after arithmetic and logical operations. The MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 129: Index Register (H:x)
The RSP (reset stack pointer) instruction was included for compatibility with the M68HC05 family and is seldom used in new HCS08 V6 programs because it affects only the low-order half of the stack pointer. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 130: Program Counter (Pc)
TAP). This ensures that the next instruction after a CLI or TAP will always be executed without the possibility of an intervening interrupt, provided I was set. 0 Interrupts enabled Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 131: Addressing Modes
Effective address computations do not require extra execution cycles. The HCS08 V6 CPU uses the 16 addressing modes described in the following sections. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 132: Inherent Addressing Mode (Inh)
LDA $55 means to load the value from address $0055 into the accumulator. Without the # symbol, the instruction is erroneously interpreted as a direct addressing instruction. Example: #$55 CPHX #$FFFF LDHX #$67 MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 133: Direct Addressing Mode (Dir)
In extended addressing, the full 16-bit address of the memory location to be operated on is provided in the instruction. Extended addressing can access any location in the 64 KB memory map. Example: MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 134: Indexed Addressing Mode
The table can begin anywhere and can extend as far as the address map allows. The k value would typically be in H:X, and the address of the beginning of the table would be MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 135: Indexed, 8-Bit Offset With Post Increment (Ix1+)
The sum is the effective address of the operand. If interrupts are disabled, this addressing mode allows the stack pointer to be used as a second "index" register. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 136: Sp-Relative, 16-Bit Offset (Sp2)
This addressing mode is used to move an 8-bit constant to any location in the direct page memory. The source data is the byte immediately following the opcode, and the destination is addressed by the second byte following the opcode. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 137: Indexed To Direct, Post Increment
CPU clocks will resume and the CPU will enter active background mode where other serial background commands can be processed. This ensures that a host development system can still gain access to a target MCU even if it is in stop mode. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 138: Wait Mode
MCU operation during software development. Active background mode is entered in any of the following ways: • When the BKGD pin is low at the time the MCU exits reset. • When a BACKGROUND command is received through the BKGD pin. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 139: Security Mode
Core. The core receives an external input signal that, when asserted, informs to the core that the MCU is in secure mode. While in secure mode, the core controls the following set of conditions: MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 140 Table 10-2. Security conditions for read access Inputs conditions Read control Ram, flash or Security Program or Current CPU instruction Current access Read access EEPROM enabled vector read from secure memory is via BDC allowed access MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 141: Hcs08 V6 Opcodes
(SWI) instruction, except the address used for the vector fetch is determined by the highest priority interrupt that is pending when the interrupt sequence started. The CPU sequence for an interrupt is: MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 142: Instruction Set Summary
– ↕ ↕ ↕ ↕ ↕ ADC oprx16,SP – 9ED9 ee ff ↕ ↕ ↕ ↕ ↕ ADC oprx8,SP – 9EE9 ↕ ↕ ↕ ↕ ↕ Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 143 BCC rel Branch if Carry Bit Branch if (C) = 0 – – – – – – Clear – – – – – – DIR (b0) Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 144 ↕ BIT ,X − − − ↕ ↕ BIT oprx16,SP − − − 9ED5 ee ff ↕ ↕ BIT oprx8,SP − − − 9EE5 ↕ ↕ Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 145 ↕ – – – – – – DIR (b0) – – – – – – DIR (b1) – – – – – – DIR (b2) Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 146 Memory Updated But Operands Not Changed) CMP ,X – – ↕ ↕ ↕ ↕ CMP oprx16,SP – – 9ED1 ee ff ↕ ↕ ↕ ↕ Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 147 ↕ ↕ A ← (A) – 0x01 DECA − − − ↕ ↕ ↕ X ← (X) – 0x01 DECX − − − ↕ ↕ ↕ Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 148 LDA #opr8i − − − ↕ ↕ LDA opr8a LDA opr16a hh ll LDA oprx16,X ee ff A ← (M) Load Accumulator LDA oprx8,X from Memory Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 149 − − 9E64 ↕ ↕ ↕ − − − DIR/DIR ↕ ↕ opr8a,opr8a ← (M) MOV opr8a,X+ Move − − − DIR/IX+ ↕ ↕ destination source Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 150 − − − − − − Low) from Stack Pull (X) ROL opr8a − − ↕ ↕ ↕ ↕ ROLA − − ↕ ↕ ↕ ↕ Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 151 ↕ ↕ ↕ C ← 1 Set Carry Bit − − − − − I ← 1 Set Interrupt Mask Bit − − − − − Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 152 PC ← (PC) + 0x0001 Push (PCL) SP ← (SP) – 0x0001 Push (PCH) SP ← (SP) – 0x0001, Push (X) SP ← (SP) – 0x0001 Push (A) Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 153 SP ← (H:X) – 0x0001 Transfer Index − − − − − − Register to SP I bit ← 0, Halt CPU WAIT Enable Interrupts Wait − − − − − for Interrupt MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 154 Instruction Set Summary MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 155: Flash Memory Module (Ftmrh)
The flash memory has the following features: • 16 KB of flash memory composed of one 16 KB flash block divided into 32 sectors of 512 bytes • Automated program and erase algorithm with verify MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 156: Other Flash Module Features
If a flash block is read during execution of a command (while FSTAT[CCIF] = 0), the read operation will return invalid data and it will trigger a illegal access exception in the MCU. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 157: Flash Memory Map
1. Configure the clock for flash program and erase command operations. 2. Use command write sequence to set flash command parameters and launch execution. 3. Execute valid flash commands according to MCU functional mode and MCU security state. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 158: Writing The Fclkdiv Register
More Parameters? Write: FSTAT register (to launch command) Clear CCIF 0x80 Read: FSTAT register Bit Polling for Command Completion CCIF Set? Check EXIT Figure 11-1. Generic flash command write sequence flowchart MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 159 20.6 21.6 0x14 21.6 22.6 0x15 22.6 23.6 0x16 23.6 24.6 0x17 24.6 25.6 0x18 1. BUSCLK is greater than this value. 2. BUSCLK is less than or equal to this value. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 160: Command Write Sequence
The return values are available for reading after the FSTAT[CCIF] flag has been returned to 1 by the memory controller. Writes to the unimplemented parameter fields, FCCOBIX[CCOBIX] =110b and FCCOBIX[CCOBIX] = 111b, are ignored with read from these fields returning 0x0000. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 161 0x02 Erase verify block 0x03 Erase verify flash section 0x04 Read once 0x06 Program flash 0x07 Program once 0x08 Erase all block 0x09 Erase flash block Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 162: Flash Interrupts
The logic used for generating the flash module interrupts is shown in the following figure. Flash command interrupt request CCIE CCIF Figure 11-2. Flash module interrupts implementation MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 163: Protection
1. For range sizes, see Table The flash protection scheme can be used by applications requiring reprogramming in single chip mode while providing as much protection as possible if reprogramming is not required. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 164 FPHDIS = 1 FPHDIS = 0 Scenario Flash start 0x0_FFFF Scenario Flash start 0x0_FFFF Unprotected region Protected region with size Protected region not defined by FPHS defined by FPHS Figure 11-3. Flash protection scenarios MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 165: Security
If the flash security byte is successfully programmed, its new value will take effect after the next MCU reset. The following subsections describe these security-related subjects: • Unsecuring the MCU using backdoor key access MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 166: Unsecuring The Mcu Using Backdoor Key Access
The verify backdoor access key command sequence has no effect on the program and erase protections defined in the flash protection register, FPROT. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 167: Unsecuring The Mcu Using Bdm
NOTE All commands in the following table, regardless of MCU mode or security state, cannot be launched while the flash array is MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 168: Flash Command Summary
• Starting any command write sequence that programs or erases flash memory before initializing the FLCKDIV register. • Writing an invalid command as part of the command write sequence. • For additional possible errors, refer to the error handling table provided for each command. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 169: Erase Verify All Blocks Command
11.3.10.2 Erase Verify Block command The Erase Verify Block command allows the user to verify that an entire flash block has been erased. The FCCOB global address [23:0] bits determine which block must be verified. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 170: Erase Verify Flash Section Command
The FSTAT[CCIF] flag will set after the erase verify flash section operation has completed. If the section is not erased, it means blank check failed and both FSTAT[MGSTAT] bits will be set. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 171: Read Once Command
Valid phrase index values for the read once command range from 0x0000 to 0x0007. During execution of the read once command, any attempt to read addresses within flash block will return invalid data. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 172: Program Flash Command
Set if CCOBIX[2:0] ≠ 011 or 101 at command launch FSTAT ACCERR Set if command not available in current mode (see Table 11-4) Set if an invalid global address [23:0] is supplied (see Table 11-1. Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 173: Program Once Command
Valid phrase index values for the program once command range from 0x0000 to 0x0007. During execution of the program once command, any attempt to read addresses within flash will return invalid data. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 174: Erase All Blocks Command
Set if any errors have been encountered during the verify operation MGSTAT0 Set if any errors have been encountered during the verify operation 1. As found in the memory map for NVM. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 175: Erase Flash Block Command
Upon clearing FSTAT[CCIF] to launch the erase flash sector command, the memory controller will erase the selected flash sector and then verify that it is erased. The FSTAT[CCIF] flag will be set after the erase flash sector operation has completed. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 176: Unsecure Flash Command
Set if any errors have been encountered during the verify operation MGSTAT0 Set if any errors have been encountered during the verify operation 1. As found in the memory map for NVM MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 177: Verify Backdoor Access Key Command
Set if an incorrect backdoor key is supplied ACCERR Set if backdoor key access has not been enabled (KEYEN[1:0] ≠ 10 FSTAT Set if the backdoor key has mismatched since the last reset FPVIOL None MGSTAT1 None MGSTAT0 None MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 178: Set User Margin Level Command
Set if command is not available in current mode (see Table 11-4) ACCERR Set if an invalid global address [23:0] is supplied FSTAT Set if an invalid margin level setting is supplied FPVIOL None MGSTAT1 None MGSTAT0 None MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 179: Set Factory Margin Level Command
Return to normal level 0x0001 User margin-1 level 0x0002 User margin-0 level 0x0003 Factory margin-1 level 0x0004 Factory margin-0 level 1. Read margin to the erased state 2. Read margin to the programmed state MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 180: Memory Map And Register Definition
Flash Configuration Register (FTMRH_FCNFG) 11.4.4/183 1836 Flash Status Register (FTMRH_FSTAT) 11.4.5/184 1838 Flash Protection Register (FTMRH_FPROT) See section 11.4.6/185 Flash Common Command Object Register:High 183A 11.4.7/186 (FTMRH_FCCOBHI) Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 181: Flash Clock Divider Register (Ftmrh_Fclkdiv)
FDIV[5:0] must be set to effectively divide BUSCLK down to 1MHz to control timed events during flash program and erase algorithms. Refer to the table in the Writing the FCLKDIV register for the recommended values of FDIV based on the BUSCLK frequency. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 182: Flash Security Register (Ftmrh_Fsec)
Defines the security state of the MCU. If the flash module is unsecured using backdoor key access, the SEC field is forced to 10. NOTE: 01 is the preferred SEC state to set MCU to secured state. Secured Secured Unsecured Secured MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 183: Flash Ccob Index Register (Ftmrh_Fccobix)
This field is reserved. Reserved This read-only field is reserved and always has the value 0. Reserved This field is reserved. This read-only field is reserved and always has the value 0. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 184: Flash Status Register (Ftmrh_Fstat)
Memory controller is busy executing a flash command (CCIF = 0). This field is reserved. Reserved This read-only field is reserved and always has the value 0. MGSTAT Memory Controller Command Completion Status Flag Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 185: Flash Protection Register (Ftmrh_Fprot)
When FPOPEN is clear, the FPHDIS fields defines unprotected address ranges as specified by the corresponding FPHS field. When FPOPEN is set, the FPHDIS fields enables protection for the address range specified by the corresponding FPHS field. Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 186: Flash Common Command Object Register:high (Ftmrh_Fccobhi)
FCCOBIX register. Byte-wide reads and writes are allowed to the FCCOB register. Address: 1830h base + Ah offset = 183Ah Read CCOB Write Reset FTMRH_FCCOBHI field descriptions Field Description CCOB Common Command Object Bit 15:8 High 8 bits of Common Command Object register MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 187: Flash Common Command Object Register: Low (Ftmrh_Fccoblo)
0x040F located in flash memory as indicated by reset condition. Address: 1830h base + Ch offset = 183Ch Read Write Reset * Notes: • x = Undefined at reset. FTMRH_FOPT field descriptions Field Description Nonvolatile Bits MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 188 The NV[7:0] bits are available as nonvolatile bits. During the reset sequence, the FOPT register is loaded from the flash nonvolatile byte in the flash configuration field at global address 0x40F located in flash memory. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 189: Introduction
• FLL lock detector and external clock monitor • FLL lock detector with interrupt capability • External reference clock monitor with reset capability • Digitally controlled oscillator optimized for 32-40 MHz frequency range MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 190: Fll Engaged Internal (Fei)
FLL which is controlled by the internal reference clock. 12.1.3.2 FLL engaged external (FEE) In FLL engaged external mode, the ICS supplies a clock derived from the FLL which is controlled by an external reference clock source. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 191: Fll Bypassed Internal (Fbi)
FLL needs to reacquire the lock before the frequency is stable. Timing sensitive operations must wait for the FLL acquisition time, t , before executing. Acquire 12.2 External signal description There are no ICS signals that connect off chip. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 192: Register Definition
Selects the amount to divide down the FLL reference clock selected by the IREFS bits. Resulting frequency must be in the range 31.25 kHz to 39.0625 kHz. RDIV SIM_SOPT1[RANGE]= 0 SIM_SOPT1[RANGE]= 1 Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 193: Ics Control Register 2 (Ics_C2)
Encoding 2—Divides the selected clock by 4. Encoding 3—Divides the selected clock by 8. Encoding 4—Divides the selected clock by 16. Encoding 5—Divides the selected clock by 32. Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 194: Ics Control Register 3 (Ics_C3)
The user can provide a custom trim value to attain other internal reference clock frequencies within the fint_t range. The custom trim value must be programmed into reserved flash location 0x0000_FF6F and copied to ICS_C3 during code initialization. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 195: Ics Control Register 4 (Ics_C4)
The user can provide a custom trim value to attain other internal reference clock frequencies within the fint_t range. The custom fine trim bit value must be programmed into reserved flash location 0x0000_FF6E and copied to ICS_C4 during code initialization. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 196: Ics Status Register (Ics_S)
Output of FLL is selected. FLL Bypassed, internal reference clock is selected. FLL Bypassed, external reference clock is selected. Reserved. Reserved This field is reserved. This read-only field is reserved and always has the value 0. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 197: Functional Description
12.4.1.1 FLL engaged internal (FEI) FLL engaged internal (FEI) is the default mode of operation and is entered when all the following conditions occur: • 00b is written to ICS_C1[CLKS]. • 1b is written to ICS_C1[IREFS]. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 198: Fll Engaged External (Fee)
• BDM mode is not active and ICS_C2[LP] bit is written to 1b. In FLL bypassed internal low-power mode, the ICSOUT clock is derived from the internal reference clock and the FLL is disabled. The internal reference clock is enabled. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 199: Fll Bypassed External (Fbe)
FLL need to re-acquire the lock before the frequency is stable. Timing sensitive operations must wait for the FLL acquisition time, t , before executing. Acquire Stop mode is entered whenever the MCU enters a STOP state. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 200: Mode Switching
• Writing a smaller value to the ICS_C3 register speeds up the ICSIRCLK frequency. The trim bits affect the ICSOUT frequency if the ICS is in FLL engaged internal (FEI), FLL bypassed internal (FBI), or FLL bypassed internal low power (FBILP) mode. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 201: Fixed Frequency Clock
ICS_C4[LOLIE] is set. ICS_S[LOLS] is cleared by reset or by writing a logic 1 to ICS_S[LOLS] when ICS_S[LOLS] is set. Writing a logic 0 to ICS_S[LOLS] has no effect. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 202: External Reference Clock Monitor
ICS_C2 = 0x00; // BDIV=divide by 1 – allows max core and bus clock frequencies 12.5.2 Initializing FBI mode The following code segment demonstrates setting ICS to FBI mode. Example: 12.5.2.1 FBI mode initialization routine MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 203: Initializing Fee Mode
((ICS_S & ICS_S_IREFST_MASK) == 1); // wait for external source selected while ((ICS_S & 0x0C) != 0x08); // wait until FBE mode is selected ICS_C2 = 0x00; // BDIV=divide by 1 – allows max core and bus clock frequencies MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 204 Initialization/application information MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 205: Modulo Timer (Mtim)
Table 13-1. MTIM module signals connection Module Signal Connect to MTIM Internal clock BUSCLK, ICSFFCLK/2 External clock PTB6/TCLK 13.2 Introduction NOTE For the chip-specific implementation details of this module's instances, see the chip configuration information. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 206: Features
• Clock source divide by 1, 2, 4, 8, 16, 32, 64, 128, or 256 • Modulo compare matched can be an output 13.3.1 Block Diagram The following figure is a block diagram of the modulo timer module. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 207: Modes Of Operation
Upon waking from very low-power stop modes, the MTIM enters its reset state. For low-power stop modes: • If the device exits any of these modes with a reset, the MTIM module enters its reset state. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 208: Mtim16 In Active Background Mode
As a result, the TCLK signal must be limited to one-fourth of the bus frequency. The TCLK pin can be muxed with a general-purpose port pin. Refer to the chip-level signal multiplexing and pin assignment details for more information. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 209: Memory Map And Register Descriptions
Address: 8h base + 0h offset = 8h Read TOIE TSTP Write TRST Reset MTIM_SC field descriptions Field Description MTIM16 overflow flag Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 210: Mtim16 Clock Configuration Register (Mtim_Clk)
Read CLKS Write Reset MTIM_CLK field descriptions Field Description 7–6 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 211: Mtim16 Counter Register High (Mtim_Cnth)
16-bit value is read after returning to normal execution. The value read from the CNTH and CNTL registers in BDM mode is the value of these registers and not the value of their read buffer. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 212: Mtim16 Counter Register Low (Mtim_Cntl)
CNTH and CNTL registers in BDM mode is the value of these registers and not the value of their read buffer. Address: 8h base + 3h offset = Bh Read CNTL Write Reset MTIM_CNTL field descriptions Field Description CNTL MTIM16 count (low byte) MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 213: Mtim16 Modulo Register High (Mtim_Modh)
MTIM_MODH field descriptions Field Description MODH MTIM16 modulo (high byte) These 8 read/write bits contain the modulo high byte value used to reset the counter and set TOF. Reset sets the register to 0x00. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 214: Mtim16 Modulo Register Low (Mtim_Modl)
The MTIM16 is composed of a main 16-bit up-counter with 16-bit modulo register, a clock source selector, and a prescaler block with nine selectable values. The module also contains software selectable interrupt logic. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 215 (TOIE) bit in the SC register. The TOIE bit should never be written to be 1 while TOF is 1. Instead, TOF should be cleared first, and then the TOIE bit can be set to 1. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 216: Mtim16 Operation Example
The timer overflow flag, TOF, sets when the counter value changes from 01AAh to 0000h. An MTIM16 overflow interrupt is generated when TOF is set, if the TOIE bit is 1. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 217: Power Management Controller (Pmc)
PMC also contains the power-on reset (POR), the low voltage detection system (low voltage reset and low voltage warning), a high-accuracy reference voltage output, a 20 kHz low-power oscillator and an internal temperature monitor. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 218: Features
• 20 kHz low-power oscillator (LPO) clock source • Integrated temperature sensor allowing both internal and external monitoring 14.4 Overview This section presents an overview of the PMC module. The following figure illustrates the simplified PMC block diagram. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 219: Modes Of Operation
• VREG is off. VREFH When in RPM, the low voltage detection system, the high-accuracy reference voltage and the temperature sensor are off. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 220: Full Performance Mode
I/O drivers. 14.6.3 VREFH VREFH is the accurate voltage reference (VREG ) output. It can be configured VREFH from 3.7 V to 4.9 V. An external decoupling capacitor is required on this pin. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 221: Vddf
Low Voltage Control and Status Register 2 (VREFH) 1856 See section 14.7.7/227 (PMC_LVCTLSTAT2) 1857 VREFH Configuration Register (PMC_VREFHCFG) See section 14.7.8/227 VREFH Low Voltage Warning (LVW) Configuration Register 1858 14.7.9/228 (PMC_VREFHLVW) 1859 Status Register (PMC_STAT) 14.7.10/228 MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 222: Control Register (Pmc_Ctrl)
Disables 20 kHz RC oscillator in the Stop mode. Enables 20 kHz RC oscillator in the Stop mode. This field is reserved. Reserved This read-only field is reserved and always has the value 0. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 223: Reset Flags Register (Pmc_Rst)
This read-only field is reserved and always has the value 0. 14.7.3 Temperature Control and Status Register (PMC_TPCTRLSTAT) Address: 1850h base + 2h offset = 1852h Read HTDS SWON TEMPEN HTIE HTIF Write Reset MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 224: Temperature Offset Step Trim Register (Pmc_Tptm)
Read TRMTPEN TOT[3:0] Write Reset PMC_TPTM field descriptions Field Description Temperature offset Trim Enable TRMTPEN If the bit is set, the temperature sensor offset is enabled. Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 225: Rc Oscillator Offset Step Trim Register (Pmc_Rc20Ktrm)
NOTE: After de-assert of system reset, a trim value is automatically loaded from the flash memory. Normal IPS writable only after PMC_CTRL[GWREN] is set. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 226: Low Voltage Control And Status Register 1 (System 5 V) (Pmc_Lvctlstat1)
Request a hardware interrupt when SLVWF = 1. Low Voltage Warning Selection SLVWSEL 4.2 V LVW threshold selected. 3.7 V LVW threshold selected. This field is reserved. Reserved This read-only field is reserved and always has the value 0. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 227: Low Voltage Control And Status Register 2 (Vrefh ) (Pmc_Lvctlstat2)
This field is reserved. This read-only field is reserved and always has the value 0. 14.7.8 V Configuration Register (PMC_VREFHCFG) REFH Address: 1850h base + 7h offset = 1857h Read Write Reset MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 228: Vrefh Low Voltage Warning (Lvw) Configuration Register (Pmc_Vrefhlvw)
3.6 V LVW threshold. 3.7 V LVW threshold. 4.1 V LVW threshold. 4.4 V LVW threshold. 14.7.10 Status Register (PMC_STAT) Address: 1850h base + 9h offset = 1859h Read HBGRDY VREFRDY Write Reset MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 229: Functional Description
5 V output regulator. It is the power supply for the digital I/Os domain VDDX (VDDX) and the analog modules domain (VDDA). 14.8.1.2 VREG VDDF VREG is a 2.8 V output regulator. It is the power supply for the on-chip NVM VDDF module (VDDF). MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 230: Vregvdd
VDDX, VDDF or VDD1.8. After an LVR reset occurs, the LVR system holds the MCU in reset status until the supply voltage rises above the low voltage level. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 231: Lvr In Low Power Mode
The VREFH low voltage level can be configured through the LVWCFG[1:0] bits in PMC_VREFHLVW register. 14.8.4.3 LVW in low power mode The LVW circuit is disabled when PMC enters the reduced performance mode (RPM). MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 232: High-Accuracy Reference Voltage
If PMC_TPCTRLSTAT[HTIE] is set to 1, PMC sets the HTIF flag in the same register and generates an interrupt when the HTDS status changes. Writing 1 to HTIF can clear this HTIF flag. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 233: Low-Power Rc Oscillator
The LPO clock is connected to SBAR (in the SIM module), and the calibration can be achieved by using FTM1 with on-chip clock. Refer to the SIM chapter for more detailed setting information. 3. Special write enable register handling MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 234 Application information PMC_TPTM, PMC_RC20KTRM and PMC_VREFHCFG are protected by a special write enable register handling. They cannot be written unless PMC_CTL[GWREN] is 1. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 235: Keyboard Interrupts (Kbi)
• both rising-edge and high-level sensitivity • One software-enabled keyboard interrupt • Exit from low-power modes 15.2.2 Modes of Operation This section defines the KBI operation in: • Wait mode • Stop mode • Background debug mode MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 236: Kbi In Wait Mode
The block diagram for the keyboard interrupt module is shown below.. BUSCLK KBACK V DD RESET KBIxP0 KBIPE0 SYNCHRONIZER KBEDG0 STOP BYPASS KEYBOARD STOP INTERRUPT FF KBIx INTERRUPT REQUEST KBIxPn KBMOD KBIPEn KBIE KBEDGn Figure 15-1. KBI block diagram MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 237: External Signals Description
Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) KBI Status and Control Register (KBI_SC) 15.5.1/238 KBI Pin Enable Register (KBI_PE) 15.5.2/239 KBI Edge Select Register (KBI_ES) 15.5.3/239 MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 238: Kbi Status And Control Register (Kbi_Sc)
KBI interrupt enabled. KBI Detection Mode KBMOD KBMOD (along with the KBEDG bits) controls the detection mode of the KBI interrupt pins. Keyboard detects edges only. Keyboard detects both edges and levels. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 239: Kbi Pin Enable Register (Kbi_Pe)
KBI_ES field descriptions Field Description KBEDG KBI Edge Selects Each of the KBEDGn bits selects the falling edge/low-level or rising edge/high-level function of the corresponding pin. Falling edge/low level. Rising edge/high level. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 240: Functional Description
1 to KBI_SC[KBACK], provided all enabled keyboard inputs are at their deasserted levels. KBI_SC[KBF] will remain set if any enabled KBI pin is asserted while attempting to clear KBI_SC[KBF] by writing a 1 to KBI_SC[KBACK]. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 241: Kbi Pullup Resistor
3. Before using internal pullup resistors, configure the associated bits in PORT_. 4. Enable the KBI pins by setting the appropriate KBI_PE[KBIPEn] bits. 5. Write to KBI_SC[KBACK] to clear any false interrupts. 6. Set KBI_SC[KBIE] to enable interrupts. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 242 Functional Description MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 243: Chip Specific Cyclic Redundancy Check (Crc)
• One 16.2 Introduction NOTE For the chip-specific implementation details of this module's instances, see the chip configuration information. The cyclic redundancy check (CRC) module generates 16/32-bit CRC code for error detection. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 244: Features
Logic Checksum CRC Engine Data Combine Polynomial Logic 16-/32-bit Select TCRC Figure 16-1. Programmable cyclic redundancy check (CRC) block diagram 16.2.3 Modes of operation Various MCU modes affect the CRC module's functionality. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 245: Run Mode
For 32-bit CRC, all registers are used. When programming data values for CRC calculation, data must be provided in DL0 register only. Writes to other bytes of data regsiters are ignored. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 246: Crc Data Register: High 0 (Crc_Dh0)
Reads to this register at any time returns the intermediate CRC value, provided CRC module is configured. Address: 1890h base + 1h offset = 1891h Read Write Reset CRC_DH0 field descriptions Field Description CRC Data Bits 23:16 MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 247: Crc Data Register: Low 1 (Crc_Dl1)
CRC module for general CRC computation. When programming the seed value in 16-bit CRC mode, the DH1:DH0 are not used and reads to these registers returns an indeterminate value. For 32-bit CRC, all registers are used. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 248: Crc Polynomial Register: High 1 (Crc_Ph1)
PL1:PL0 contain the lower 16-bits of CRC polynomial, which are used in both 16- and 32-bit CRC modes. Address: 1890h base + 4h offset = 1894h Read Write Reset CRC_PH1 field descriptions Field Description CRC Polynomial Bits 31:24 MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 249: Crc Polynomial Register: High 0 (Crc_Ph0)
PL1:PL0 contain the lower 16-bits of CRC polynomial, which are used in both 16- and 32-bit CRC modes. Address: 1890h base + 6h offset = 1896h Read Write Reset CRC_PL1 field descriptions Field Description CRC Polynomial Bits 15:8 MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 250: Crc Polynomial Register: Low 0 (Crc_Pl0)
Both bits in bytes and bytes are transposed. Only bytes are transposed; no bits in a byte are transposed. 5–4 Type Of Transpose For Read TOTR Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 251: Functional Description
After a completed CRC calculation, the module can be reinitialized for a new CRC computation by reasserting CRC_CTRL[WAS] and programming a new, or previously used, seed value. All other parameters must be set before programming the seed value and subsequent data values. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 252: Crc Calculations
6. Clear CRC_CTRL[WAS] to start writing data values. 7. Write data values into CRC_DL0. A CRC is computed on every data value write, and the intermediate CRC result is stored back into CRC_DH1, CRC_DH0, CRC_DL1 and CRC_DL0. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 253: Transpose Feature
CRC data register: 1. CTRL[TOT] or CTRL[TOTR] is 00. No transposition occurs. 2. CTRL[TOT] or CTRL[TOTR] is 01. Bits in a byte are transposed, while bytes are not transposed. reg[7:0] becomes reg[0:7] MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 254: Crc Result Complement
CRC data register every time the CRC data register is read. When CTRL[FXOR] is cleared, reading the CRC data register accesses the raw checksum value. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 255: Chip-Specific Adc Information
• The following table summarizes the signal connection of ADC module. Table 17-1. ADC module signals connection Module Signal Connect to ADC0 ADO~AD30 Analog signal ( details shouwn in below section) ADC1 HW_TRIG XBAR_OUT2, XBAR_OUT3 Internal Clock BUSCLK, ADACK External Clock CLKIN MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 256: Adc Channel Assignments
AD23 Bandgap 11101 AD29 REFH 11110 AD30 REFL 11111 Module disabled None 1. AD7 can select PMC temperature or bandgap by configuring PMC_TPCTRLSTAT. 2. This is 1.15 V, high-precision bandgap from PMC. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 257: Adc Analog Supply And Reference Connections
This allows ALTCLK to be used as the conversion clock source for the ADC while the MCU is in wait mode. ALTCLK cannot be used as the ADC conversion clock source while the MCU is in stop mode. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 258: Hardware Trigger
V , the cold slope value is applied TEMP25 TEMP TEMP25 in the above equation. If V is less than V the hot slope value is applied. TEMP TEMP25 MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 259: Introduction
• Operation in Wait or Stop modes for lower noise operation • Asynchronous clock source for lower noise operation • Selectable asynchronous hardware conversion trigger • Automatic compare with interrupt for less-than, or greater-than or equal-to, programmable value MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 260: Block Diagram
ADACK ASYNC CLOCK GENERATOR ADICLK ADIV Figure 17-1. ADC Block Diagram 17.3 External Signal Description The ADC module supports up to 24 separate analog inputs. It also requires four supply/ reference/ground connections. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 261 In some packages, V REFL REFL connected internally to V . If externally available, connect the V pin to the same REFL voltage potential as V MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 262: Analog Channel Inputs (Adx)
FIFO is fulfilled at the depth indicated by the ADC_SC4[AFDEP]. Any write 0x1F to these bits will reset the FIFO and stop the conversion if it is active. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 263 The ADCH bits form a 5-bit field that selects one of the input channels. 00000-00111 AD0-AD7 01000-10011 10100-10101 Reserved 10110 Temperature Sensor 10111 Bandgap 11000-11100 Reserved 11101 REFH 11110 REFL 11111 Module disabled NOTE: Reset FIFO in FIFO mode. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 264: Status And Control Register 2 (Adcx_Sc2)
Indicates that ADC result FIFO have at least one valid new data. Indicates that ADC result FIFO have no valid new data. Result FIFO full FFULL Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 265: Status And Control Register 3 (Adcx_Sc3)
Longer sample times can also be used to lower overall power consumption when continuous conversions are enabled if high conversion rates are not required. Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 266: Status And Control Register 4 (Adcx_Sc4)
The FIFO always use the first dummied FIFO channels when it is enabled. When this bit is set and FIFO function is enabled, ADC will repeat using the first FIFO channel as the conversion channel until the result Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 267: Conversion Result High Register (Adcx_Rh)
6-level FIFO is enabled. 7-level FIFO is enabled. 8-level FIFO is enabled. 17.4.5 Conversion Result High Register (ADCx_RH) In 12-bit operation, ADC_RH contains the upper four bits of the result of a 12-bit conversion. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 268: Conversion Result Low Register (Adcx_Rl)
FIFO is fulfilled at the depth indicated by the AFDEP. The AD result FIFO can be read via ADC_RH:ADC_RL continuously by the order set in analog input channel FIFO. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 269: Compare Value High Register (Adcx_Cvh)
This register holds the lower 8 bits of the 12-bit compare value. Bits CV7:CV0 are compared to the lower 8 bits of the result following a conversion in 12-bit mode. Address: Base address + 7h offset Read Write Reset MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 270: Functional Description
• The bus clock, which is equal to the frequency at which software is executed. This is the default selection following reset. • The bus clock divided by 2: For higher bus clock rates, this allows a maximum divide by 16 of the bus clock. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 271: Hardware Trigger
In addition, the ADC module can be configured for low power operation, long sample time, continuous conversion, and an automatic compare of the conversion result to a software determined compare value. 17.5.3.1 Initiating conversions A conversion initiates under the following conditions: MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 272: Completing Conversions
(when ADC_SC4[AFDEP] are not all 0s) are therefore invalid. • The MCU is reset. • The MCU enters Stop mode with ADACK not enabled. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 273: Power Control
5 µs + 20 ADCK + 5 bus clock cycles Single or first continuous 10-bit or 12-bit 5 µs + 23 ADCK + 5 bus clock cycles Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 274: Automatic Compare Function
(ADC_SC2[ACFGT] = 0), if the result is less than the compare value, ADC_SC1[COCO] is set. The value generated by the addition of the conversion result and the complement of the compare value is transferred to ADC_R. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 275: Fifo Operation
FIFO to get the proper results. Don't read ADC_R until all of the conversions are completed in FIFO mode. The ADC_SC1[COCO] bit will be set only when all conversions indicated by the analog input channel FIFO complete whatever software or MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 276 ADC_SC4[HTRGME]=1), the next analog is fetched from analog input channel FIFO only when this conversion completes, its result is stored in the result FIFO, and next conversion will start without waiting for next MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 277 In continuous conversion in which the ADC_SC1[ADCO] bit is set, the ADC starts next conversion immediately when all conversions are completed. ADC module will fetch the analog input channel from the beginning of analog input channel FIFO. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 278 Channel FIFO fulfilled Start FIFOed Conversion when hardware trigger occurs Hardware Triggered Continuous Conversion (Only need one hardware trigger) The n COCO = 1 Conversions Completed result store Figure 17-3. ADC FIFO conversion sequence MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 279: Mcu Wait Mode Operation
If a conversion is in progress when the MCU enters Stop mode, it continues until completion. Conversions can be initiated while the MCU is in Stop mode by means of the hardware trigger or if continuous conversions are enabled. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 280: Initialization Information
ADCK. This register is also used for selecting sample time and low-power configuration. 2. Update status and control register 2 (ADC_SC2) to select the hardware or software conversion trigger and compare function options, if enabled. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 281: Pseudo-Code Example
4. Update status and control register 1 (ADC_SC1) to select whether conversions will be continuous or completed only once, and to enable or disable conversion complete interrupts. The input channel on which conversions will be performed is also selected here. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 282: Pseudo-Code Example
// read conversion result of channel 5 buffer[2] = ADC_R; // read conversion result of channel 7 buffer[3] = ADC_R; NOTE ADC_R is 16-bit ADC result register, combined from ADC_RH and ADC_RL MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 283: Application Information
, which may be shared on the same pin as REFH on some devices. The low reference is V , which may be shared on the same REFL pin as V on some devices. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 284: Analog Input Pins
There is a brief current associated with V when the sampling capacitor is charging. REFL The input is sampled for 3.5 cycles of the ADCK source when ADC_SC3[ADLSMP] is low, or 23.5 cycles when ADC_SC3[ADLSMP] is high. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 285: Sources Of Error
The ADC accuracy numbers are guaranteed as specified only if the following conditions are met: • There is a 0.1 µF low-ESR capacitor from V to V REFH REFL • There is a 0.1 µF low-ESR capacitor from V to V MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 286: Code Width And Quantization Error
The ideal code width for an N bit converter (in this case N can be 8, 10 or 12), defined as 1LSB, is: MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 287: Linearity Errors
• Total unadjusted error (TUE) — This error is defined as the difference between the actual transfer function and the ideal straight-line transfer function and includes all forms of error. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 288: Code Jitter, Non-Monotonicity, And Missing Codes
Missing codes are those values that are never converted for any input value. In 8-bit or 10-bit mode, the ADC is guaranteed to be monotonic and have no missing codes. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 289: Cmp Configuration Information
• The following table summarizes the signal connection of CMP module. Table 18-1. CMP module signals Connection Module Signal Connect to PTA0/CMP0 PTA1/CMP1 PTA2/CMP2 6-bit DAC 6-bit DAC To GDU Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 290: Acmp In Stop Mode
Vin to Vin/64. Vin can be selected from two voltage sources, V and V . The 6-bit DAC from a comparator is available as an on-chip internal signal only and is not available externally to a pin. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 291: Cmp Features
18.6 6-bit DAC Key Features • 6-bit resolution • Selectable supply reference source • Power down mode to conserve power when it is not being used • Output can be routed to internal comparator input MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 292: Anmux Key Features
• Operates the entire supply range 18.8 CMP, DAC, and ANMUX Diagram The following figure shows the block diagram for the High Speed Comparator, Digital to Analog Converter, and Analog MUX modules. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 293: Cmp Block Diagram
Sample Input Window ANMUX and Filter control CMPO MSEL[1:0] Figure 18-1. CMP, DAC and ANMUX Blocks Diagram 18.9 CMP Block Diagram The following figure shows the block diagram for the Comparator module. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 294 CR0[FILTER_CNT] is set greater than 0x01. • If CR1[SE] = 1, the external SAMPLE input is used as sampling clock • IF CR1[SE] = 0, the divided bus clock is used as sampling clock MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 295: Memory Map/Register Definitions
These bits represent the number of consecutive samples that must agree prior to the comparator ouput filter accepting a new output state. For information regarding filter programming and latency reference the Functional Description. Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 296: Cmp Control Register 1 (Cmp_Cr1)
WE is cleared. However, avoid writing ones to both bit locations because this "11" case is reserved and may change in future implementations. Windowing mode not selected. Windowing mode selected. Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 297: Cmp Filter Period Register (Cmp_Fpr)
When you select the same input from analog mux to the positive and negative port, the comparator is disabled automatically. Analog Comparator disabled. Analog Comparator enabled. 18.10.3 CMP Filter Period Register (CMP_FPR) Address: 68h base + 2h offset = 6Ah Read FILT_PER Write Reset MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 298: Cmp Status And Control Register (Cmp_Scr)
CFR is level sensitive and as long as COUT is high CFR will be set. The CFR bit is cleared by writing a logic one to the bit. Rising edge on COUT has not been detected. Rising edge on COUT has occurred. Analog Comparator Flag Falling Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 299: Dac Control Register (Cmp_Daccr)
DAC Output Voltage Select This bit selects an output voltage from one of 64 distinct levels. DACO = (Vin/64) * (VOSEL[5:0] + 1), so the DACO range is from Vin/64 to Vin. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 300: Mux Control Register (Cmp_Muxcr)
DAC and ANMUX Blocks Diagram. NOTE: When an inappropriate operation selects the same input for both MUXes, the comparator automatically shuts down to prevent itself from becoming a noise generator. 6-bit DAC output is selected MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 301: Mux Pin Enable Register (Cmp_Muxpe)
SCR[CFF] is set on a falling edge and SCR[CFR] is set on rising edge of the comparator output. The (optionally filtered) comparator output can be read directly through the SCR[COUT] bit. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 302: Cmp Functional Modes
Windowed Mode (#s 5A & 5B). 0x01 0x01 - 0xFF Windowed/Resampled mode Comparator output is sampled on every rising bus clock edge when SAMPLE=1 to generate COUTA, Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 303: Disabled Mode (# 1)
In disabled mode, the analog comparator is non-functional and consumes no power. The output of the analog comparator block (CMPO) is zero in this mode. 18.11.1.2 Continuous Mode (#s 2A & 2B) MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 304: Sampled, Non-Filtered Mode (#S 3A & 3B)
(unclocked) mode. COUT and COUTA are identical. For control configurations which result in disabling the Filter Block, refer to Filter Block Bypass Logic diagram. 18.11.1.3 Sampled, Non-Filtered Mode (#s 3A & 3B) MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 305 #3B, the clock to filter block is internally derived. The comparator filter has no other function than sample/hold of the comparator output in this mode (# 3B). MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 306: Sampled, Filtered Mode (#S 4A & 4B)
COUTA is sampled whenever a rising edge is detected on the Filter Block clock input. The only difference in operation between Sampled, Non-Filtered (# 3A) and Sampled, Filtered (# 4A) is that CR0[FILTER_CNT] is now greater than 1, which activates filter operation. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 307 Select Control Block CMPO COUT (TO OTHER SOC FUNCTIONS) WINDOW/SAMPLE bus clock COUTA Clock CMPO to divided Prescaler FILT_PER CGMUX clock SE=1 Figure 18-6. Sampled, Filtered (# 4A): Sampling point externally driven MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 308: Windowed Mode (#S 5A & 5B)
COUTA only when the WINDOW signal is high. In actual operation, COUTA may lag the analog inputs by up to one bus clock cycle plus the combinational path delay through the comparator and polarity select logic. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 309 COUTA Clock CMPO to divided Prescaler FILT_PER CGMUX clock SE=0 Figure 18-9. Windowed Mode For control configurations which result in disabling the Filter Block, refer to Filter Block Bypass Logic diagram. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 310: Windowed/Resampled Mode (# 6)
FPR[FILT_PER] and the bus clock rate. Configuration for this mode is virtually identical to that for the Windowed/Filtered Mode shown in the next section. The only difference is that the value of CR0[FILTER_CNT] must be exactly one. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 311: Windowed/Filtered Mode (#7)
Figure 18-11. Windowed/Filtered Mode 18.11.2 Power Modes 18.11.2.1 Wait Mode Operation During Wait mode and if enabled, the CMP continues to operate normally. Also, if enabled, a CMP interrupt can wake the MCU. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 312: Stop Mode Operation
When programmed for filtering modes, COUT will initially be equal to zero until sufficient clock cycles have elapsed to fill all stages of the filter. This occurs even if COUTA is at a logic one. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 313: Low Pass Filter
Always switch to this setting prior to making any changes in filter parameters. This resets the filter to a known state. Switching CR0[FILTER_CNT] on the fly without this intermediate step can result in unexpected behavior. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 314: Latency Issues
Windowed mode 0x00 0x01 0x01 - 0xFF Windowed / Resampled + (FPR[FILT_PER] x mode ) + 2T > 0x01 0x01 - 0xFF Windowed / Filtered mode + (CR0[FILTER_CNT] x FPR[FILT_PER] x T MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 315: Cmp Interrupts
. The module can be powered down (disabled) when it is not used. When in disable mode, DACO is connected to the analog ground. VOSEL[5:0] DACEN VRSEL DACO Figure 18-12. 6-bit DAC Block Diagram MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 316: Dac Functional Description
This module has a single reset input, corresponding to the chip-wide peripheral reset. 18.16 DAC Clocks This module has a single clock input, the bus clock. 18.17 DAC Interrupts This module has no interrupts. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 317: Chip Specific Flextimer Module
Table 19-1. FTM module signals Connection Module Signal Connect to channel 0 output XBAR_IN10 channel 0 input XBAR_OUT4 channel 1 output XBAR_IN11 channel 1 input XBAR_OUT5 Internal Clock BUSCLK, ICSFFCLK/2 External Clock PTB6/TCLK MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 318: Introduction
• Selecting external clock connects FTM clock to a chip level input pin therefore allowing to synchronize the FTM counter with an off chip clock source • Prescaler divide-by 1, 2, 4, 8, 16, 32, 64, or 128 • FTM has a 16-bit counter MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 319: Modes Of Operation
(0–7). The following figure shows the FTM structure. The central component of the FTM is the 16-bit counter with programmable final value and its counting can be up or up-down. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 320: Signal Description
Input capture interrupt input CH7F mode logic Output modes C7VH:L channel 7 logic output Figure 19-1. FTM block diagram 19.3 Signal description The following table shows the user-accessible signals for the FTM. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 321: Extclk — Ftm External Clock
This section provides a detailed description of all FTM registers. 19.4.1 Module memory map This section presents a high-level summary of the FTM registers and how they are mapped. 19.4.2 Register descriptions This section consists of register descriptions in address order. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 322: Status And Control (Ftmx_Sc)
TOF. FTM counter has not overflowed. FTM counter has overflowed. Timer Overflow Interrupt Enable TOIE Enables FTM overflow interrupts. Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 323: Counter High (Ftmx_Cnth)
BDM became active, even if one or both counter bytes are read while MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 324: Counter Low (Ftmx_Cntl)
Update of the registers with write buffers. This write coherency mechanism may be manually reset by writing to the SC register whether BDM is active or not. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 325: Modulo Low (Ftmx_Modl)
See the description for the Modulo High register. Address: 70h base + 4h offset = 74h Read MOD_L Write Reset FTMx_MODL field descriptions Field Description MOD_L Low byte of the modulo value MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 326: Channel Status And Control (Ftmx_Cnsc)
CHF remains set indicating an event has occurred. In this case a CHF interrupt request is not lost due to the clearing sequence for a previous CHF. Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 327: Channel Value High (Ftmx_Cnvh)
16-bit value after returning to normal execution. Any read of the CnV registers in BDM mode bypasses the buffer latches and returns the value of these registers and not the value of their read buffer. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 328: Channel Value Low (Ftmx_Cnvl)
Address: 70h base + 7h offset + (3d × i), where i=0d to 1d Read VAL_L Write Reset FTMx_CnVL field descriptions Field Description VAL_L Channel Value Low Byte Captured FTM counter value of the input capture function or the match value for the output modes MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 329: Functional Description
The CLKS[1:0] bits in the SC register select one of three possible clock sources for the FTM counter or disable the FTM counter. After any MCU reset, CLKS[1:0] = 0:0 so no clock source is selected. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 330: Prescaler
The FTM counter clock is the selected clock divided by the prescaler (see Prescaler). The FTM counter has these modes of operation: • up counting (see counting) • up-down counting (see Up-down counting) MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 331: Up Counting
The FTM period when using up-down counting is 2 × (MODH:L) × period of the FTM counter clock. The TOF bit is set when the FTM counter changes from MODH:L to (MODH:L – 1). MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 332: Free Running Counter
19.5.4 Input capture mode The input capture mode is selected when (CPWMS = 0), (MSnB:MSnA = 0:0), and (ELSnB:ELSnA ≠ 0:0). MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 333: Output Compare Mode
CHnF bit is set on the third rising edge of the system clock after a valid edge occurs on the channel input. 19.5.5 Output compare mode The output compare mode is selected when (CPWMS = 0) and (MSnB:MSnA = 0:1). MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 334 CNTH:L channel (n) output previous value previous value CHnF bit TOF bit Figure 19-10. Example of the output compare mode when the match sets the channel output MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 335: Edge-Aligned Pwm (Epwm) Mode
0x0000 is loaded into the FTM counter. Additionally, it is forced low at the channel (n) match, when the FTM counter = CnVH:L. See the following figure. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 336: Center-Aligned Pwm (Cpwm) Mode
0x0001 to 0x7FFF because values outside this range can produce ambiguous results. In the CPWM mode, the FTM counter counts up until it reaches MODH:L and then counts down until it reaches the value of 0x0000. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 337 If (ELSnB:ELSnA = X:1), then the channel (n) output is forced low at the channel (n) match (FTM counter = CnVH:L) when counting down, and it is forced high at the channel (n) match when counting up; see the following figure. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 338: Update Of The Registers With Write Buffers
FTM counter changes from 0xFFFF to 0x0000. • If the selected mode is CPWM mode, then MODH:L registers are updated after both bytes have been written and the FTM counter changes from MODH:L to (MODH:L – 0x0001). MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 339: Cnvh:l Registers
• The FTM counter and the prescaler counter are zero and are stopped (CLKS[1:0] = 0b00) • The timer overflow interrupt is zero (Timer overflow interrupt) • The channels interrupts are zero (Channel (n) interrupt) MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 340 (n) output is toggled when there is a match. In the output compare mode, the channel output is not updated to its initial value when there is a write to CNTH or CNTL registers (item 3). MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 341: Ftm Interrupts
The timer overflow interrupt is generated when (TOIE = 1) and (TOF = 1). 19.7.2 Channel (n) interrupt The channel (n) interrupt is generated when (CHnIE = 1) and (CHnF = 1). MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 342 FTM Interrupts MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 343: Chip Specific Pules Width Timer
PWT0 PWT0_IN0 PTA6/PWT0 PWT0_IN1 XBAR_OUT6 PWT0_IN2, PWT0_IN3, tie to ground Internal Clock BUSCLK External Clock PTB6/TCLK PWT1 PWT1_IN0 PTA7/PWT1 PWT1_IN1 XBAR_OUT7 PWT1_IN2, PWT1_IN3 tie to ground Internal Clock BUSCLK External Clock PTB6/TCLK MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 344: Introduction
PWTSR bit (PWT software reset) is not written to 1 and the PWT module is still enabled. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 345: Block Diagram
PWTRDY POVIE PINSEL[1:0] PWTTOG PWTLVL PWTIE Data PINEN0 Interrupt PINEN1 PRDYIE PINEN2 PINEN3 Figure 20-1. Pulse width timer (PWT) block diagram 20.3 External signal description 20.3.1 Overview PWT has the following signal. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 346: Pwtin[3:0] — Pulse Width Timer Capture Inputs
Pulse Width Timer Control Register (PWT0_CR) 20.4.2/348 Pulse Width Timer Positive Pulse Width Register: High 20.4.3/349 (PWT0_PPH) Pulse Width Timer Positive Pulse Width Register: Loq 20.4.4/350 (PWT0_PPL) Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 347: Pulse Width Timer Control And Status Register (Pwtx_Cs)
The PWT is enabled. PWT Module Interrupt Enable PWTIE Enables the PWT module to generate an interrupt. Disables the PWT to generate interrupt. Enables the PWT to generate interrupt. Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 348: Pulse Width Timer Control Register (Pwtx_Cr)
PWT counter no overflow. PWT counter runs from 0xFFFF to 0x0000. 20.4.2 Pulse Width Timer Control Register (PWTx_CR) Address: Base address + 1h offset Read PCLKS PINSEL Write Reset MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 349: Pulse Width Timer Positive Pulse Width Register: High (Pwtx_Pph)
Clock divided by 32. Clock divided by 64. Clock divided by 128. 20.4.3 Pulse Width Timer Positive Pulse Width Register: High (PWTx_PPH) Address: Base address + 2h offset Read PPWH Write Reset MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 350: Pulse Width Timer Positive Pulse Width Register: Loq (Pwtx_Ppl)
20.4.5 Pulse Width Timer Negative Pulse Width Register: High (PWTx_NPH) Address: Base address + 4h offset Read NPWH Write Reset PWTx_NPH field descriptions Field Description NPWH Negative Pulse Width[15:8] High byte of captured negative pulse width value. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 351: Pulse Width Timer Negative Pulse Width Register: Low (Pwtx_Npl)
PWTx_CNTH field descriptions Field Description PWTH PWT counter[15:8] High byte of PWT counter register. 20.4.8 Pulse Width Timer Counter Register: Low (PWTx_CNTL) Address: Base address + 7h offset Read PWTL Write Reset MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 352: Functional Description
As soon as the PWT is enabled, the 16-bit free counter will begin to count up until a edge transistion on the selected PWTIN. Determined by PWT_CS[FCTLE] and PWTIN state, the counter contents can be uploaded to the corresponding registers. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 353 The following figure illustrates the trigger edge detection and pulse width registers update of PWT. PWTEN FCTLE(=0) PWTIN NPH:L 0xD1 PPH:L 0xD2 READY CNTH:L 0x00 0x00 0x00 0xD1 0x00 0xD2 Figure 20-2. PWT normal measurement with FCTLE = 0 MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 354 READY CNTH:L 0xFFFF 0xD9 0xDA 0x00 Figure 20-4. PWT measurement overflows at high level with FCTLE = 1 PWTEN PWTIN PWTOV CNTH:L 0x00 0xFFFF Figure 20-5. PWT measurement overflows with PWTIN toggles MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 355 MCU reset , writing 1 to PWTSR bit or writing a 0 to PWTEN bit followed by writing a 1 to it. The following figure illustrates the buffering mechanism of pulse width register: MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 356: Reset Overview
0). Unlike reset by the CPU, the PWT reset does not restore everything in the PWT to its reset state. The following occurs 1. The PWT counter is set to 0x0000 MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 357: Interrupts
The PWTIE bit of PWTxCS controls the interrupt generation of the PWT module. The functionality of the PWT is not affected while the interrupt is being generated. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 358: Application Examples
11 pwtclk + err actual pulse width: 11 pwtclk + err (err < 1 pwtclk + 1 bus clock) Figure 20-9. Example at PWTCLK is Bus Clock divided by 2 MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 359: Initialization/Application Information
2. Set PWTIE, PRDYIE and POVIE bits in PWTxCS if corresponding interrupt is desired to be generated. 3. Set PWTEN bit in PWTxCS to enable the pulse width measurement. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 360 Initialization/Application information The step 1 and 2 can be sequential or not, but they must be completed before step 3 to ensure all settings are ready before pulse width measurement is enabled. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 361: Chip Specific Inter-Integrated Circuit
PTA5/SDA PTA4/SCL Internal clock BUSCLK NOTE This module supports wakeup in Wait and Stop modes. 21.2 Introduction NOTE For the chip-specific implementation details of this module's instances, see the chip configuration information. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 362: Features
21.2.2 Modes of operation The I2C module's operation in various low power modes is as follows: • Run mode: This is the basic mode of operation. To conserve power in this mode, disable the module. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 363: Block Diagram
Module Enable Address Write/Read Interrupt DATA_MUX ADDR_DECODE DATA_REG CTRL_REG FREQ_REG ADDR_REG STATUS_REG Input Sync In/Out START Data STOP Shift Arbitration Register Control Clock Address Control Compare Figure 21-1. I2C Functional block diagram MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 364: I2C Signal Descriptions
18B9 I2C Address Register 2 (I2C_A2) 21.4.10/374 18BA I2C SCL Low Timeout Register High (I2C_SLTH) 21.4.11/375 18BB I2C SCL Low Timeout Register Low (I2C_SLTL) 21.4.12/375 18BC I2C Status register 2 (I2C_S2) 21.4.13/376 MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 365: I2C Address Register 1 (I2C_A1)
The SCL divider multiplied by multiplier factor (mul) determines the I2C baud rate. I2C baud rate = I2C module clock speed (Hz)/(mul × SCL divider) Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 366: I2C Control Register 1 (I2C_C1)
WUEN Write RSTA Reset I2C_C1 field descriptions Field Description I2C Enable IICEN Enables I2C module operation. Disabled Enabled I2C Interrupt Enable IICIE Enables I2C interrupt requests. Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 367 Normal operation. No interrupt generated when address matching in low power mode. Enables the wakeup function in low power mode. This field is reserved. Reserved This read-only field is reserved and always has the value 0. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 368: I2C Status Register (I2C_S)
ARBL This bit is set by hardware when the arbitration procedure is lost. The ARBL bit must be cleared by software, by writing 1 to it. Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 369: I2C Data I/O Register (I2C_D)
Acknowledge signal was received after the completion of one byte of data transmission on the bus No acknowledge signal detected 21.4.5 I2C Data I/O register (I2C_D) Address: 18B0h base + 4h offset = 18B4h Read DATA Write Reset MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 370: I2C Control Register 2 (I2C_C2)
This read-only field is reserved and always has the value 0. This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 371: I2C Stop Control And Status Register (I2C_Scs)
If the I2C Control Register 1's IICIE bit was set to 1 before the MCU entered stop mode, system software will receive the interrupt triggered by the I2C Status Register's TCF bit after the MCU wakes from the stop mode. Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 372: I2C Range Address Register (I2C_Ra)
If I2C_C2[RMEN] is set to 1, any nonzero value write enables this register. This register value can be considered as a maximum boundary in the range matching mode. This field is reserved. Reserved This read-only field is reserved and always has the value 0. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 373: I2C Smbus Control And Status Register (I2C_Smb)
Second I2C Address Enable SIICAEN Enables or disables SMBus device default address. I2C address register 2 matching is disabled I2C address register 2 matching is enabled Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 374: I2C Address Register 2 (I2C_A2)
SHTF2 interrupt is enabled 21.4.10 I2C Address Register 2 (I2C_A2) Address: 18B0h base + 9h offset = 18B9h Read Write Reset I2C_A2 field descriptions Field Description 7–1 SMBus Address Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 375: I2C Scl Low Timeout Register High (I2C_Slth)
Address: 18B0h base + Bh offset = 18BBh Read SSLT[7:0] Write Reset I2C_SLTL field descriptions Field Description SSLT[7:0] SSLT[7:0] Least significant byte of SCL low timeout value that determines the timeout period of SCL low. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 376: I2C Status Register 2 (I2C_S2)
Tx or Rx buffer is empty and can be written to, that is new data can be loaded into the buffer. 21.5 Functional description This section provides a comprehensive functional description of the I2C module. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 377: I2C Protocol
Stop Signal Signal Write AD3 AD2 AD1 AD3 AD2 AD1 Calling Address Repeated New Calling Address Read/ Stop Start Read/ Start Signal Signal Write Write Signal Figure 21-2. I2C bus transmission signals MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 378: Slave Address Transmission
MSB is transferred first. Each data byte is followed by a ninth (acknowledge) bit, which is signaled from the receiving device by pulling SDA low at the ninth clock. In summary, one complete data transfer needs nine clock pulses. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 379: Stop Signal
The relative priority of the contending masters is determined by a data arbitration procedure. A bus master loses arbitration if it transmits logic level 1 while another master transmits logic level 0. The losing masters immediately switch to slave receive mode and MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 380: Clock Synchronization
SCL low after completing a single byte transfer (9 bits). In this case, it halts the bus clock and forces the master clock into wait states until the slave releases SCL. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 381: Clock Stretching
SCL hold SCL hold SDA hold SCL hold SCL hold divider value (start) (stop) divider (clocks) (start) (stop) (hex) (hex) value value (clocks) value value 1024 Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 382: Bit Address
START condition (Sr) followed by a different slave address. Table 21-4. Master-transmitter addresses slave-receiver with a 10-bit address Slave Slave Data Data address address first 7 bits second 11110 + byte AD10 + AD[8:1] MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 383: Master-Receiver Addresses A Slave-Transmitter
I2C interrupt. User software must ensure that for this interrupt, the contents of the Data register are ignored and not treated as valid data. 21.5.3 Address matching All received addresses can be requested in 7-bit or 10-bit address format. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 384: System Management Bus Specification
SDA float high) when it detects any single clock held low longer than T TIMEOUT,MIN Devices that have detected this condition must reset their communication and be able to receive a new START condition within the timeframe of T TIMEOUT,MAX MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 385 T within a byte, where each byte is LOW:MEXT defined as START-to-ACK, ACK-to-ACK, or ACK-to-STOP. When CSMBCLK TIMEOUT MEXT occurs, SMBus MEXT rises and also triggers the SLTF. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 386: Fast Ack And Nack
In addition to indicating a slave device busy condition, SMBus uses the NACK mechanism to indicate the reception of an invalid command or invalid data. Because such a condition may occur on the last byte of the transfer, SMBus devices are required to MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 387: Resets
IICIE & SSIE SMBus SCL low timeout SLTF IICIF IICIE SMBus SCL high SDA low timeout SHTF2 IICIF IICIE & SHTF2IE Wakeup from stop3 or wait mode IAAS IICIF IICIE & WUEN MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 388: Byte Transfer Interrupt
ARBL bit in the Status Register is set. Arbitration is lost in the following circumstances: 1. SDA is sampled as low when the master drives high during an address or data transmit cycle. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 389: Timeout Interrupt In Smbus
MCU execution of a STOP instruction when the I2C module is in the middle of a transfer unless the Stop mode holdoff feature is used during this period (set FLT[SHEN] to 1). MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 390: Double Buffering Mode
In the next-to-last ISR, do not send data again (the buffer data will be under running). • To keep new ISRs software-compatible with previous ISRs, the write/read I2C_D operation will not block the internal-hardware-released SCL/SDA signals. At the MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 391: Initialization/Application Information
The routine shown in the following figure encompasses both master and slave I2C operations. For slave operation, an incoming I2C message that contains the proper address begins I2C communication. For master operation, communication must be MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 392 Data register. An example of an I2C driver which implements many of the steps described here is available in AN4342: Using the Inter-Integrated Circuit on ColdFire+ and Kinetis MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 393 2. When 10-bit addressing addresses a slave, the slave sees an interrupt following the first byte of the extended address. Ensure that for this interrupt, the contents of the Data register are ignored and not treated as a valid data transfer. Figure 21-5. Typical I2C interrupt routine MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 394 2. In receive mode, one bit time delay may be needed before the stop signal generation, to wait for the possible longest time period (in worst case) of the 9th SCL cycle. Figure 21-6. Typical I2C SMBus interrupt routine MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 395: Chip Specific Serial Communications Interface
CPU • SC1_C1[SCISWAI] = 1: SCI clocks freeze when CPU is in Wait mode. Customization: • Primary clock: BUSCLK (20 MHz) • Alternate clock: None MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 396: Introduction
• Programmable 8-bit or 9-bit character length • Programmable 1-bit or 2-bit stop bits • Receiver wakeup by idle-line or address-mark • Optional 13-bit break character generation / 11-bit break character detection • Selectable transmitter output polarity MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 397: Modes Of Operation
1x Baud Rate Clock  SHIFT DIRECTION TXINV Parity Generation SCI Controls TxD TO TxD Transmit Control Pin Logic TxD Direction TXDIR BRK13 TDRE Tx Interrupt Request TCIE Figure 22-1. SCI transmitter block diagram MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 398 Logic RDRF IDLE ILIE Rx Interrupt Request LBKDIF LBKDIE From RxD Pin Active Edge RXEDGIF Detect RXEDGIE ORIE FEIE Error Interrupt Request NEIE Parity Checking PEIE Figure 22-2. SCI receiver block diagram MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 399: Sci Signal Descriptions
SCI registers. This section refers to registers and control bits only by their names. An NXP-provided equate or header file is used to translate these names into the appropriate absolute addresses. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 400: Sci Baud Rate Register: High (Scix_Bdh)
Stop Bit Number Select SBNS SBNS determines whether data characters are one or two stop bits. One stop bit. Two stop bit. Baud Rate Modulo Divisor. Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 401: Sci Baud Rate Register: Low (Scix_Bdl)
22.4.3 SCI Control Register 1 (SCIx_C1) This read/write register controls various optional features of the SCI system. Address: 1868h base + 2h offset = 186Ah Read LOOPS SCISWAI RSRC WAKE Write Reset MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 402 1s in the data character, including the parity bit, is odd. Even parity means the total number of 1s in the data character, including the parity bit, is even. Even parity. Odd parity. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 403: Sci Control Register 2 (Scix_C2)
When the SCI receiver is off, the RxD pin reverts to being a general-purpose port I/O pin. If LOOPS is set the RxD pin reverts to being a general-purpose I/O pin even if RE is set. Receiver off. Receiver on. Receiver Wakeup Control Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 404: Sci Status Register 1 (Scix_S1)
• Write to the SCI data register (SCI_D) to transmit new data • Queue a preamble by changing TE from 0 to 1 • Queue a break character by writing 1 to SCI_C2[SBK] Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 405 FE set and then read the SCI data register (SCI_D). No framing error detected. This does not guarantee the framing is correct. Framing error. Parity Error Flag Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 406: Sci Status Register 2 (Scix_S2)
No active edge on the receive pin has occurred. An active edge on the receive pin has occurred. This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 407: Sci Control Register 3 (Scix_C3)
SCI receiver idle waiting for a start bit. SCI receiver active (RxD input not idle). 22.4.7 SCI Control Register 3 (SCIx_C3) Address: 1868h base + 6h offset = 186Eh Read TXDIR TXINV ORIE NEIE FEIE PEIE Write Reset MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 408 Hardware interrupt requested when FE is set. Parity Error Interrupt Enable PEIE This bit enables the parity error flag (PF) to generate hardware interrupt requests. PF interrupts disabled; use polling). Hardware interrupt requested when PF is set. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 409: Sci Data Register (Scix_D)
Read receive data buffer 0 or write transmit data buffer 0. R0T0 22.5 Functional description The SCI allows full-duplex, asynchronous, NRZ serial communication among the MCU and remote devices, including other MCUs. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 410: Baud Rate Generation
22.5.2 Transmitter functional description This section describes the overall block diagram for the SCI transmitter, as well as specialized functions for sending break and idle characters. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 411: Send Break And Queued Idle
If the receiving device is another NXP SCI, the break characters are received as 0s in all eight data bits and a framing error (SCI_S1[FE] = 1) occurs. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 412: Receiver Functional Description
(lsb first), and one (or two) stop bits of logic 1. For information about 9-bit data mode, refer to 8- and 9-bit data modes. For the remainder of this discussion, assume the SCI is configured for normal 8-bit data mode. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 413: Data Sampling Technique
It does not improve worst case analysis because some characters do not have any extra falling edges anywhere in the character frame. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 414: Receiver Wake-Up Operation
When SCI_C1[ILT] is set, the idle bit counter does not start until after a stop bit time, so the idle detection is not affected by the data in the last character of the previous message. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 415: Interrupts And Status Flags
When a program detects that the receive data register is full (SCI_S1[RDRF] = 1), it gets the data from the receive data register by reading SCI_D. The SCI_S1[RDRF] flag is cleared by reading SCI_S1 while SCI_S1[RDRF] is set and then reading SCI_D. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 416: Baud Rate Tolerance
As the receiver samples an incoming frame, it re-synchronizes the RT clock on any valid falling edge within the frame. Resynchronization within frames will correct a misalignment between transmitter bit times and receiver bit times. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 417: Slow Data Tolerance
The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit and 2 stop bits character with no errors is: ((186 - 179) / 186) X 100 = 3.76% MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 418: Fast Data Tolerance
The maximum percent difference between the receiver count and the transmitter count of a fast 9-bit and 2 stop bits character with no errors is: ((186 - 192) / 186) x 100 = 3.23% MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 419: Additional Sci Functions
(including preamble, break and normal data) being transmitted out of or received into the SCI module, that means SCI_S1[TC] =1, SCI_S1[TDRE] = 1, and SCI_S2[RAF] = 0 must all meet before entering stop mode. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 420: Loop Mode
In single-wire mode, the transmitter output is internally connected to the receiver input and the RxD pin is not used by the SCI, so it reverts to a general-purpose port I/O pin. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 421: Chip Specific Programmable Delay Block
Table 23-1. PDB module signals Connection Module Signal Connect to PDB0 PDB0 HW Trigger XBAR_OUT8 PDB0 Output XBAR_IN8 Internal Clock HSCLK PDB1 PDB1 HW trigger XBAR_OUT9 PDB1 OUTPUT XBAR_IN9 Internal Clock HSCLK MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 422: Introduction
• Support continuous count mode or single shot delay mode • Supply on-fly delay value update • Selective output mode: logic level or one-shot pulse 23.4 Block diagram The following figure show the block diagram of the PDB. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 423: Mode Of Operation
4. If Pulse output mode is set, pulse will be generated when counter value is equal and greater than compare value 5. A stop bit is needed to stop counter and reset counter to zero and clear output. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 424: Continuous Count Mode
5. A stop bit is needed to stop counter and reset counter to zero and clear output. Logic Output mode Pulse output Mode Compare Value Counter Counter reset Hardware Trigger S oftware S tart Resume Count S top S tart Count Count Figure 23-3. Continuous count mode MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 425: Memory Map And Register Descriptions
Timer compare interrupt requests disabled. Timer compare interrupt requests enabled. PDB1 Trigger Output TRGOUT1 Configure PDB1 trigger output as an pulse or level when a successful compare occurs. Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 426: Pdb Control Register 1 (Pdb_Ctrl1)
Do NOT use BSET and BCLR instruction to this register, which may cause unexpected software clear to SWCLR0 and SWCLR1. Address: 60h base + 1h offset = 61h Read CNTSEL1 CNTSEL0 PRESCALER SWCLR1 SWTRG1 SWCLR0 SWTRG0 Write Reset MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 427: Pdb0 Comparison Low Register (Pdb_Cmpl0)
After the counter reaches the comparison value, the timer comparison flag (TCF0) becomes set at the next clock. NOTE Writing to the CMPx0 registers would take effect immediately. Address: 60h base + 2h offset = 62h Read CMPL0 Write Reset MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 428: Pdb0 Comparison High Register (Pdb_Cmph0)
This register is also used to enable PDB0 by writing 1 to bit 0, the writing operation doesn’t take effect the counter’s value. Address: 60h base + 4h offset = 64h Read CNT0_7_1 CNT0_0_ PDBEN0 Write Reset MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 429: Pdb1 Comparison Low Register (Pdb_Cmpl1)
After the counter reaches the comparison value, the timer comparison flag (TCF0) becomes set at the next clock. NOTE Writing to the CMPx1 registers would take effect immediately. Address: 60h base + 6h offset = 66h Read CMPH1 Write Reset MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 430: Pdb1 Counter High/Low (Pdb_Cnt1)
PDBEN1 doesn’t take effect the counter’s value. Writing 0 to bit0 of this register: Counter is off and Trigger output is low. Writing 1 to bit0 of this register: Counter is enabled. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 431: Introduction
24.2 Features The XBAR has the following features: • M(16) identical N(16)-input muxes with individual select fields. 24.3 Block diagram The following figure show the block diagram of the XBAR. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 432: Memory Map And Register Descriptions
XBAR Selection Register (XBAR_SEL1) 24.4.2/434 18D2 XBAR Selection Register (XBAR_SEL2) 24.4.2/434 18D3 XBAR Selection Register (XBAR_SEL3) 24.4.2/434 18D4 XBAR Selection Register (XBAR_SEL4) 24.4.2/434 18D5 XBAR Selection Register (XBAR_SEL5) 24.4.2/434 Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 433: External Mux Selection Register (Xbar_Extmux)
External mux selection 1 for PWM channels SEL1 PWM output channel 2. PWM output channel 3. External mux selection 0 for PWM channels SEL0 PWM output channel 0. PWM output channel 1. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 434: Xbar Selection Register (Xbar_Seln)
XBAR_SELn field descriptions Field Description 7–4 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Mux Selection Select inputs of XBAR_IN to be muxed to XBAR_OUT. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 435: Chip Specific Gdu Information
Phase detection ACMP0 output XB_IN12 Phase detection ACMP1 output XB_IN13 Phase detection ACMP2 output XB_IN14 Phase detection ACMP0 window input XB_OUT10 Phase detection ACMP1 window input XB_OUT11 Phase detection ACMP2 window input XB_OUT12 25.2 Introduction MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 436: Features
• Programmable Phase selection allows the maximize the gain of BEMF zero crossing detection • Selectable offset from internal 6bit DAC or external pin • Over-voltage detection on supply VDD pin 25.4 Block diagram The following figure shows the block diagram of GDU. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 437: Modes Of Operation
5.5 V. In the open-loop mode, the clamped voltage follows with V 2. Stop mode The module is disabled in Stop mode. All internal analog circuits are switched off. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 438: Memory Map And Register Definition
25.6.24/458 LIMIT1 CMP Status and Control Register 187C 25.6.25/459 (GDU_LIMIT1SCR) 187D LIMIT1 DAC Control Register (GDU_LIMIT1DACCR) 25.6.26/460 187E PDCS and Clamp Status Register (GDU_STATREG) 25.6.27/460 187F LIMIT CMP BIAS Register (GDU_SIGBIAS) 25.6.28/461 MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 439: Phcmp0 Control Register 0 (Gdu_Phcmp0Cr0)
See the device's data sheet for the exact values. Level 0 Level 1 25.6.2 PHCMP0 Control Register 1 (GDU_PHCMP0CR1) Address: 20h base + 1h offset = 21h Read PMODE Write Reset MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 440 The EN bit enables the Analog Comparator Module. When the module is not enabled, it remains in the off state, and consumes no power. When you select the same input from analog mux to the positive and negative port, the comparator is disabled automatically. Analog Comparator disabled. Analog Comparator enabled. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 441: Phcmp0 Filter Period Register (Gdu_Phcmp0Fpr)
The IEF bit enables the CFF interrupt from the CMP. When this bit is set, an interrupt will be asserted when the CFF bit is set. Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 442: Phcmp1 Control Register 0 (Gdu_Phcmp1Cr0)
1 consecutive sample must agree (comparator output is simply sampled). 2 consecutive samples must agree. 3 consecutive samples must agree. 4 consecutive samples must agree. 5 consecutive samples must agree. Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 443: Phcmp1 Control Register 1 (Gdu_Phcmp1Cr1)
This read-only field is reserved and always has the value 0. Power Mode Select PMODE Low Speed (LS) comparison mode selected. High Speed (HS) comparison mode selected. GDU Comparator INVERT Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 444: Phcmp1 Filter Period Register (Gdu_Phcmp1Fpr)
Setting FILT_PER to 0x0 disables the filter. Filter programming and latency details appear in the Functional Description. This field has no effect when CR1[SE] is equal to one. In that case, the external SAMPLE signal is used to determine the sampling period. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 445: Phcmp1 Status And Control Register (Gdu_Phcmp1Scr)
Reading the COUT bit will return the current value of the analog comparator output. The register bit is reset to zero and will read as CR1[INV] when the Analog Comparator module is disabled (CR1[EN] = 0). Writes to this bit are ignored. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 446: Phcmp2 Control Register 0 (Gdu_Phcmp2Cr0)
See the device's data sheet for the exact values. Level 0 Level 1 25.6.10 PHCMP2 Control Register 1 (GDU_PHCMP2CR1) Address: 20h base + 9h offset = 29h Read PMODE Write Reset MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 447 The EN bit enables the Analog Comparator Module. When the module is not enabled, it remains in the off state, and consumes no power. When you select the same input from analog mux to the positive and negative port, the comparator is disabled automatically. Analog Comparator disabled. Analog Comparator enabled. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 448: Phcmp2 Filter Period Register (Gdu_Phcmp2Fpr)
The IEF bit enables the CFF interrupt from the CMP. When this bit is set, an interrupt will be asserted when the CFF bit is set. Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 449: Clamp Control Register (Gdu_Clmpctrl)
Tunes the clamped output voltage when the clamp works at regulation mode. The tuning range is 5 V TUNE ±20% with step of 5%. Clamp Enable CLAMPEN Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 450: I/O Control Register (Gdu_Ioctrl)
The value setting of LSDS1 (higher bit) and LSDS0 (lower bit) is as follows: Disable the output buffer Lowest drive strength, I =25 mA peak Middle drive strength, I =75 mA peak Highest drive strength, I =100 mA peak Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 451: Virtual Network Phase Detection Control (Gdu_Phasectrl)
This read-only field is reserved and always has the value 0. Virtual Network Phase 2 Selection PHSEL2 Phase 2 is off. Phase 2 is on. Virtual Network Phase 1 Selection PHSEL1 Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 452: Current Sensor And Overcurrent Protection Control Register (Gdu_Curctrl)
This read-only field is reserved and always has the value 0. OPAMP1 Enable AMP1EN Disables GDU AMP1. Enables GDU AMP1. 25.6.17 LIMIT0 CMP Control Register 0 (GDU_LIMIT0CR0) Address: 20h base + 1854h offset = 1874h Read FLTCNT HYST Write Reset MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 453: Limit0 Cmp Control Register 1 (Gdu_Limit0Cr1)
NOTE: Set this bit to zero, because the sample input is connected to the logic 1. Sampling mode is not selected. Sampling mode is selected. Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 454: Limit0 Cmp Filter Period Register (Gdu_Limit0Fpr)
The comparator output (CMPO) is driven out on the associated CMPO output pin. Comparator Enable Analog Comparator is disabled. Analog Comparator is enabled. 25.6.19 LIMIT0 CMP Filter Period Register (GDU_LIMIT0FPR) Address: 20h base + 1856h offset = 1876h Read FLTPER Write Reset MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 455: Limit0 Cmp Status And Control Register (Gdu_Limit0Scr)
During normal operation, the CFF bit is set when a falling edge on COUT is detected. This bit is cleared by writing a logic 1 to it. Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 456: Limit0 Dac Control Register (Gdu_Limit0Daccr)
GDU_LIMIT1CR0 field descriptions Field Description This field is reserved. Reserved This read-only field is reserved and always has the value 0. 6–4 Filter Sample Count FLTCNT Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 457: Limit1 Cmp Control Register 1 (Gdu_Limit1Cr1)
NOTE: Set this bit to zero, because the sample input is connected to the logic 1. Sampling mode is not selected. Sampling mode is selected. Windowing Enable Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 458: Limit1 Cmp Filter Period Register (Gdu_Limit1Fpr)
The comparator output (CMPO) is driven out on the associated CMPO output pin. Comparator Enable Analog Comparator is disabled. Analog Comparator is enabled. 25.6.24 LIMIT1 CMP Filter Period Register (GDU_LIMIT1FPR) Address: 20h base + 185Bh offset = 187Bh Read FLTPER Write Reset MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 459: Limit1 Cmp Status And Control Register (Gdu_Limit1Scr)
During normal operation, the CFF bit is set when a falling edge on COUT is detected. This bit is cleared by writing a logic 1 to it. Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 460: Limit1 Dac Control Register (Gdu_Limit1Daccr)
Overvoltage Protection 22 V OVP22V This bit is set when a voltage over 22 V is detected. The bit is cleared by writing a logic 1 to it. Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 461: Limit Cmp Bias Register (Gdu_Sigbias)
REFH Bias voltage selected from V REFH Bias voltage selected from V Reserved This field is reserved. This read-only field is reserved and always has the value 0. 25.7 Functional description MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 462: Phase Detection Function Descriptions
The comparators are provided with a virtual neutral reference signal that is generated at the virtual resistor network circuit and tracks the signal at the motor MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 463: Opamp Function Descriptions
VBIAS/2 6Bit BUF1 DAC1 Logic 1 WINDOW /SAMPLE LIMT1CMP (128KΩ) (6.4KΩ) AMP1P LIMIT1[COUT] Window and AMP1 To PWM FAULT3 Filter Control (6.4KΩ) AMP1M To ADCA6 & ADCB6 (128KΩ) Figure 25-3. OpAMP diagram MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 464: Opamp Descriptions
6-bit DAC. The output of the comparator is connected to a digital filter circuit. 25.7.3 Predrive function descriptions This section describes the MOSFET predriver. 25.7.3.1 Predrive diagram The following figure shows the predrive diagram MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 465: Predrive Descriptions
SCR[CFF] is set on a falling edge and SCR[CFR] is set on rising edge of the comparator output. The (optionally filtered) comparator output can be read directly through the SCR[COUT] bit. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 466: Gcmp Diagram
The following figure shows the block diagram for the GDU comparator module. Sample Input GCMP Window and Filter control CMPO Figure 25-5. GCMP block diagram 25.7.4.2 GCMP block diagram The following figure shows the block diagram for the GDU comparator module. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 467 CR0[FILTER_CNT] is set greater than 0x01. • If CR1[SE] = 1, the external SAMPLE input is used as sampling clock • IF CR1[SE] = 0, the divided bus clock is used as sampling clock MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 468: Gcmp Functional Modes
(#s 3A & 3B). Sampled, Filtered mode > 0x01 > 0x01 > 0x00 Refer to the Sampled, filtered mode (#s 4A & 4B). 0x00 Windowed mode Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 469 In disabled mode, the GDU analog comparator is non-functional and consumes no power. The output of the analog comparator block (CMPO) is zero in this mode. 25.7.4.3.2 Continuous mode (#s 2A & 2B) MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 470 (unclocked) mode. COUT and COUTA are identical. For control configurations which result in disabling the Filter Block, refer to Filter Block Bypass Logic diagram. 25.7.4.3.3 Sampled, non-filtered mode (#s 3A & 3B) MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 471 #3B, the clock to filter block is internally derived. The GDU comparator filter has no other function than sample/hold of the comparator output in this mode (# 3B). MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 472 COUTA is sampled whenever a rising edge is detected on the Filter Block clock input. The only difference in operation between Sampled, Non-Filtered (# 3A) and Sampled, Filtered (# 4A) is that CR0[FILTER_CNT] is now greater than 1, which activates filter operation. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 473 Polarity Filter Control Select Control Block CMPO COUT (TO OTHER SOC FUNCTIONS) WINDOW/SAMPLE bus clock Clock divided Prescaler FILT_PER CGMUX clock SE=1 Figure 25-10. Sampled, filtered (# 4A): sampling point externally driven MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 474 COUTA only when the WINDOW signal is high. In actual operation, COUTA may lag the analog inputs by up to one bus clock cycle plus the combinational path delay through the comparator and polarity select logic. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 475 (TO OTHER SOC FUNCTIONS)) WINDOW/SAMPLE bus clock Clock divided Prescaler FILT_PER CGMUX clock SE=0 Figure 25-13. Windowed mode For control configurations which result in disabling the Filter Block, refer to Filter Block Bypass Logic diagram. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 476 FPR[FILT_PER] and the bus clock rate. Configuration for this mode is virtually identical to that for the Windowed/Filtered Mode shown in the next section. The only difference is that the value of CR0[FILTER_CNT] must be exactly one. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 477: Power Modes
Figure 25-15. Windowed/filtered mode 25.7.4.4 Power modes 25.7.4.4.1 Wait mode operation During Wait mode and if enabled, the GDU CMP continues to operate normally. Also, if enabled, a GDU CMP interrupt can wake the MCU. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 478: Startup And Operation
They also apply to COUT for all sampling and windowed modes. Filtering can be performed using an internal timebase defined by FPR[FILT_PER], or using an external SAMPLE input to determine sample time. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 479 The following table summarizes maximum latency values for the various modes of operation in the absence of noise. Filtering latency is restarted each time an actual output transition is masked by noise. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 480: Gcmp Interrupts
SCR[IER] bit and SCR[CFR] are set. It is also asserted when both SCR[IEF] bit and SCR[CFF] are set. The interrupt is de-asserted by clearing either SCR[IER] or SCR[CFR] for a rising edge interrupt, or SCR[IEF] and SCR[CFF] for a falling edge interrupt. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 481: Chip Specific Pulse Width Modulator
GDU OPAMP0 ACMP OUT Fault3 GDU OPAMP1 ACMP OUT PWM_Synch XBAR_IN4 PWM0, PWM1 GDU inputs, XB_IN5 2-to-1 Mux PWM2, PWM3 GDU inputs, XB_IN6 2-to-1 Mux PWM4, PWM5 GDU inputs, XB_IN7 2-to-1 Mux Internal Clock HSCLK MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 482: Mc9S08Su16 Reference Manual, Rev. 5, 4/2017 Nxp Semiconductors
• separate top and bottom polarity control • Edge- or center-aligned PWM signals • 15 bits of resolution • Half-cycle reload capability • Integral reload rates from 1 to 16 • Individual software controlled PWM output MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 483: Modes Of Operation
PWM outputs disabled as a function of CNFG WAIT_EN bit. EOnCE PWM outputs are disabled as a function of the CNFG DBG_EN bit. 26.2.4 Block diagram The following figure show the block diagram of the PWM. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 484 PWM5 Unit 5 Register 5 Software Filters Compare Control and Output Output Mode Polarity Setting Control Fault Inputs Figure 26-1. PWM block diagram The following figure shows PWM SWAP and MASK functionality. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 485: Functional Description
PWM reload cycle begins. 26.3.2 Generator The PWM generator contains a 15-bit up/down PWM counter producing output signals with software selectable alignment, period, duty cycle, and the inversion of PWM signal generation. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 486: Alignment And Compare Output Polarity
CINVx = 1 Figure 26-4. Edge-Aligned PWM output NOTE Because of the equals-comparator architecture of this PWM, the modulus=0 case is considered illegal. However, the deadtime constraints and fault conditions will still be guaranteed. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 487: Period
26.3.2.3 Pulse width duty cycle The signed 16-bit number written to the PWM value registers is the pulse width in PWM clock periods of the PWM prescaler output (or period minus the pulse width if CINVx=1). MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 488 An edge-aligned operation is illustrated in the following figure. The pulse width is the value written to the PWM value register with edge-aligned output in PWM clock cycles. PWM pulse width = (PWM value) × (PWM clock period) MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 489: Independent Or Complementary Channel Operation
Writing 0 to the INDEPnn bit configures the PWM output as a pair of complementary channels. The PWM pins are paired in complementary channel operation, illustrated in the following figure. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 490 In complementary channel operation, there are three additional features: • Deadtime insertion • Separate top and bottom pulse width correction for distortions caused by deadtime inserted and reactive load characteristics • Separate top and bottom output polarity control MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 491: Deadtime Generators
PWM2 & PWM3 OUTCTL2 Top (PWM4) Top/Bottom OUT5 Generator Bottom (PWM5) OUT4 Deadtime Generator PWM4 & PWM5 OUTCTL4 Figure 26-11. Deadtime generators The following figures illustrate deadtime insertion in different operation conditions. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 492 PWM Value = 3 PWM Value = 2 Value = 1 PWM0, No Deadtime PWM1, No Deadtime PWM0, Deadtime = 3 PWM1, Deadtime = 3 Figure 26-14. Deadtime and small pulse widths MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 493: Asymmetric Pwm Output
CINV. The results of the XOR are fed into the complement and dead-time logic. In contrast to asymmetric PWM output mode, the PWM phase shift can pass the PWM cycle boundary, as shown in the following figure. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 494: Pwm Output Polarity
Setting and clearing the OUTn bit activates and deactivates the corresponding PWM channel. The OUTCTRLn and OUTn bits are in the PWM output control (OUT) register. During software output control, TOPNEGnn and BOTNEGnn still control output polarity. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 495 Software can drive the PWM outputs, even when the PWM Enable (PWMEN) bit is set to zero. NOTE Avoid an unexpected deadtime insertion by clearing the OUTn bits before setting and after clearing the OUTCTLn bits. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 496 Functional description Figure 26-17. Software output control in complementary mode MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 497: Generator Loading
Up/Down Counter Reload Change To Every Reload To Every To Every Opportunity Frequency Two Opportunities Four Opportunities Figure 26-18. Full cycle reload frequency change MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 498: Reload Flag
Figure 26-20. Full-Cycle center-aligned PWM value loading Half = 0, LDFQ[3:0] = 0000 = Reload Every Cycle Up/Down Counter LDOK = 1 Modulus = 2 PWM Value = 1 PWMF = 1 Figure 26-21. Full-Cycle center-aligned modulus loading MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 499 PWM Value = 1 PWMF = 1 Figure 26-23. Half-Cycle center-aligned modulus loading Up only Counter LDOK = 1 Modulus = 3 PWM Value = 1 PWMF = 1 Figure 26-24. Edge-Aligned PWM value loading MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 500: Initialization
PWMEN or OUTCTLn bits are set, an improper deadtime insertion will occur. Initializing the deadtime registers after setting PWMEN or OUTCTLn can cause an improper deadtime insertion. However, the deadtime can never be shorter than the specified value. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 501: Fault Protection
PWM pin. Please refer to the following table. The fault protection is enabled even when the PWM is not enabled; therefore, if a fault is latched in, it must be cleared prior to enabling the PWM to prevent an unexpected interrupt. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 502: Fault Pin Filter
• Software clears the FFLAGn flag by writing a 1 to the FTACKn bit • Software clears the FIEn bit by writing a 0 to it • A reset occurs MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 503: Automatic Fault Clearing
PWM half cycle boundary. Please see Figure 1-31. Fault 0 or Fault 2 PWMS Enabled PWMS Disabled PWMS Enabled PWMS Disabled FFLAGn Cleared Figure 26-30. Manual fault clearing (example 1) MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 504: Memory Map And Register Descriptions
PWM Fault Status Acknowledge Register: High 26.4.6/511 (PWM_FLTACKH) PWM Output Control Register: Low (PWM_OUTL) 26.4.7/513 PWM Output Control Register: High (PWM_OUTH) 26.4.8/514 PWM Counter Register: Low (PWM_CNTRL) 26.4.9/514 Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 505 PWM Deadtime Register: High (PWM_DTIM1H) 26.4.17/ PWM Disable Mapping Registers 1: Low (PWM_DMAP1L) 26.4.18/ PWM Disable Mapping Registers 1: High (PWM_DMAP1H) 26.4.19/ PWM Disable Mapping Registers 2: Low (PWM_DMAP2L) Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 506: Pwm Control Register: Low (Pwm_Ctrll)
This read/write bit enables the PWMF flag to generate interrupt requests. Reset clears PWMRIE. PWMF interrupt requests disabled. PWMF interrupt requests enabled. PWM Reload Flag PWMF Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 507: Pwm Control Register: High (Pwm_Ctrlh)
LDOK. Reading the LDFQn bits reads the buffered values and not necessarily the values currently in effect. 0000 Every PWM opportunity 0001 Every 2 PWM opportunities Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 508: Pwm Fault Control Register: Low (Pwm_Fctrll)
FAULT3 interrupt requests disabled FAULT3 interrupt requests enabled FAULT3 Pin Clearing Mode FMODE3 This read/write bit selects automatic or manual clearing of FAULT3 pin faults. A reset clears FMODE3. Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 509 FAULT0 Pin Clearing Mode FMODE0 This read/write bit selects automatic or manual clearing of FAULT0 pin faults. A reset clears FMODE0. Manual fault clearing of FAULT0 pin faults. Automatic fault clearing of FAULT0 pin faults. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 510: Pwm Fault Control Register: High (Pwm_Fctrlh)
Reset PWM_FLTACKL field descriptions Field Description This field is reserved. Reserved This read-only field is reserved and always has the value 0. FAULT3 Pin Acknowledge FTACK3 Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 511: Pwm Fault Status Acknowledge Register: High (Pwm_Fltackh)
PWM_FLTACKH field descriptions Field Description FAULT3 Pin FPIN3 This read-only bit reflects the current state of the filtered FAULT3 pin. A reset has no effect on FPIN3. Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 512 This read-only flag is set within two CPU cycles after a rising edge on the filtered FAULT0 pin. Clear FFLAG0 by writing a one to the FTACK0 bit in this register (FLTACK). A reset clears FFLAG0. No fault on the FAULT0 pin Fault on the FAULT0 pin MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 513: Pwm Output Control Register: Low (Pwm_Outl)
PWM1 is complement of PWM0 (complementary channel operation); PWM1 is active (independent channel operation) Output 0 OUT0 When the corresponding OUTCTL bit is set, these read/write bits control the PWM pins. PWM0 is inactive PWM0 is active MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 514: Pwm Output Control Register: High (Pwm_Outh)
CNTRH value. Reading the CNTRH reads this internal hold register. Always read the lower byte before reading the upper byte in order to guarantee a coherent 15-bit value is read. Address: 40h base + 8h offset = 48h Read CNTR7_0 Write Reset MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 515: Pwm Counter Register: High (Pwm_Cntrh)
PWM load cycle begins. Reading CMOD reads the value in a buffer. It is not necessarily the value the PWM generator is currently using. Address: 40h base + Ah offset = 4Ah Read CMOD7_0 Write Reset MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 516: Pwm Counter Register: High (Pwm_Cmodh)
A PWM value less than or equal to zero deactivates the PWM output for the entire PWM period. A PWM value greater than, or equal to the modulus, activates the PWM output for the entire PWM period. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 517: Pwm Value Register: High (Pwm_Valnh)
PWM outputs. Address: 40h base + Dh offset + (2d × i), where i=0d to 5d Read PMVAL15_8 Write Reset PWM_VALnH field descriptions Field Description PMVAL15_8 PWM Pulse Width Value 15:8 MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 518: Pwm Deadtime Register: Low (Pwm_Dtimnl)
PWM clock cycles minus one PWM clock cycle. This register is write protected after the WP bit in the PWM configuration register is set. Reserved bits 15–12 cannot be modified. They are read as zero. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 519: Pwm Disable Mapping Registers 1: Low (Pwm_Dmap1L)
Reserved bits 15-8 in the DMAP2 register cannot be modified. The bits are read as zero. Address: 40h base + 1Ch offset = 5Ch Read DISMAP7_0 Write Reset PWM_DMAP1L field descriptions Field Description DISMAP7_0 PWM Disable Mapping7:0 MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 520: Pwm Disable Mapping Registers 1: High (Pwm_Dmap1H)
DISMAP23_16 Write Reset PWM_DMAP2L field descriptions Field Description DISMAP23_16 PWM Disable Mapping 23:16 26.4.20 PWM Configure Register: Low (PWM_CNFGL) Address: 40h base + 17E0h offset = 1820h Read BOTNEG INDEP Write Reset MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 521: Pwm Configure Register: High (Pwm_Cnfgh)
DBGEN WAITEN TOPNEG Write Reset PWM_CNFGH field descriptions Field Description This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 522: Pwm Channel Control Register: Low (Pwm_Cctrll)
The ENHA bit cannot be modified after the WP bit in the CNFG register is set. ENHA in turn provides protection for the VLMODE[1:0], SWP45, SWP23 and SWP01 bits. The Mask bits are not write protectable. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 523 No swap Channel two and channel three are swapped Swap 0 and 1 SWP01 This bit is write protected when ENHA is zero. No swap Channel zero and channel one are swapped MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 524: Pwm Channel Control Register: High (Pwm_Cctrlh)
LDOK bit is set and the next PWM load cycle begins. Reading PECn reads the value in a buffer and not necessarily the value the PWM generator is currently using. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 525: Pwm Compare Invert Register: High (Pwm_Cinvh)
CINV1 CINV0 Write Reset PWM_CINVH field descriptions Field Description 7–6 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 526: Resets
All PWM registers are reset to their default values upon any system reset. 26.6 Clocks The PWM operation clock runs at either system clock or 2 × system clock, which is selected in the SIM module. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 527: Interrupts
FAULTn pin. The fault pin interrupt enable bits, FIE0–FIE3, enable the FFLAGn flags to generate CPU interrupt requests. FFLAG0–FFLAG3 are in the fault status register. FIE0–FIE3 are in the fault control register MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 528 Interrupts MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 529 • Active background mode commands for CPU register access • GO and TRACE1 commands • BACKGROUND command can wake CPU from stop or wait modes • One hardware address breakpoint built into BDC MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 530: Background Debug Controller (Bdc)
• Non-intrusive commands can be executed at any time even while the user's program is running. Non-intrusive commands allow a user to read or write MCU memory locations or access status and control registers within the background debug controller. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 531: Bkgd Pin Description
If a host is attempting to communicate with a target MCU that has an unknown BDC clock rate, a SYNC command may be sent to the target MCU to request a timed sync response signal from which the host can determine the correct communication speed. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 532: Communication Details
Ten target BDC clock cycles later, the target senses the bit level on the BKGD pin. Typically, the host actively drives the pseudo-open-drain BKGD pin during MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 533 1 0 C Y C L E S H O S T S A M P L E S B K G D P IN Figure 27-3. BDC target-to-host serial bit timing (logic 1) MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 534: Bdc Commands
The following table shows all HCS08 BDC commands, a shorthand description of their coding structure, and the meaning of each command. Coding Structure Nomenclature This nomenclature is used in the following table to describe the coding structure of the BDC commands. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 535 TRACE1 Active BDM 10/d Trace 1 user instruction at the address in the PC, then return to active background mode Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 536 • Removes all drive to the BKGD pin so it reverts to high impedance • Monitors the BKGD pin for the sync response pulse MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 537: Bdc Hardware Breakpoint
Because HCS08 devices do not have external address and data buses, the most important functions of an in-circuit emulator have been built onto the chip with the MCU. The debug system consists of an 8-stage FIFO that can store address or data bus information, MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 538: Comparators A And B
• Storage of data bus values into the FIFO • Starting to store change-of-flow addresses into the FIFO (begin type trace) • Stopping the storage of change-of-flow addresses into the FIFO (end type trace) MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 539: Bus Capture Information And Fifo Operation
DBGFL reads needed to initially fill the FIFO. Additional periodic reads of DBGFH and DBGFL return delayed information about executed instructions so the host debugger can develop a profile of executed instruction addresses. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 540: Change-Of-Flow Information
There is separate opcode tracking logic for each comparator so more than one compare event can be tracked through the instruction queue at a time. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 541: Trigger Modes
A Then B ̶ Trigger when the address matches the value in comparator B but only after the address for another cycle matched the value in comparator A. There can be any number of cycles after the A match and before the B match. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 542: Hardware Breakpoints
CPU. TAG in DBGC controls whether the breakpoint request will be treated as a tag-type breakpoint or a force-type breakpoint. A tag breakpoint causes the current opcode to be marked as it enters the instruction queue. If a tagged opcode reaches MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 543: Memory Map And Register Description
The reset values shown in the register figure are those in the normal reset conditions. If the MCU is reset in BDM, ENBDM, BDMACT, CLKSW will be reset to 1 and others all be to 0. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 544 BDC commands work. Whenever the host forces the target MCU into active background mode, the host should issue a READ_STATUS command to check that BDMACT = 1 before attempting other BDC commands. Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 545: Bdc Breakpoint Match Register: High (Bdc_Bkpth)
Breakpoints are normally set while the target MCU is in active background mode before running the user application program. Address: 0h base + 1h offset = 1h Read A[15:8] Write Reset BDC_BKPTH field descriptions Field Description A[15:8] High 8-bit of hardware breakpoint address. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 546: Bdc Breakpoint Register: Low (Bdc_Bkptl)
BDC_SBDFR field descriptions Field Description 7–1 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Background Debug Force Reset BDFR Table continues on the next page... MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 547 A serial active background mode command such as WRITE_BYTE allows an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot be written from a user program. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 548 Memory map and register description MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 549: Introduction
• Event only B, store data • A then event only B, store data • Inside range, A ≤ address ≤ B • Outside range, address < A or address > B MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 550: Modes Of Operation
MCU is secure. The DBG module comparators are disabled when executing a Background Debug Mode (BDM) command. 28.1.3 Block diagram The following figure shows the structure of the DBG module. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 551: Signal Description
Figure 28-1. DBG block diagram 28.2 Signal description The DBG module contains no external signals. 28.3 Memory map and registers This section provides a detailed description of all DBG registers accessible to the end user. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 552: Debug Comparator A High Register (Dbg_Cah)
DBGEN = 1 and BEGIN = 0, the bits in this register do not change after reset. Address: 18C0h base + 0h offset = 18C0h Read CA[15:8] Write Reset MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 553: Debug Comparator A Low Register (Dbg_Cal)
The Comparator A Low compare bits control whether Comparator A will compare the address bus bits [7:0] to a logic 1 or logic 0. Compare corresponding address bit to a logic 0. Compare corresponding address bit to a logic 1. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 554: Debug Comparator B High Register (Dbg_Cbh)
DBGEN = 1 and BEGIN = 0, the bits in this register do not change after reset. Address: 18C0h base + 3h offset = 18C3h Read CB[7:0] Write Reset MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 555: Debug Comparator C High Register (Dbg_Cch)
The Comparator C High compare bits control whether Comparator C will compare the address bus bits [15:8] to a logic 1 or logic 0. Compare corresponding address bit to a logic 0. Compare corresponding address bit to a logic 1. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 556: Debug Comparator C Low Register (Dbg_Ccl)
DBGEN = 1 and BEGIN = 0, the bits in this register do not change after reset. Address: 18C0h base + 6h offset = 18C6h Read F[15:8] Write Reset MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 557: Debug Fifo Low Register (Dbg_Fl)
DBGFX and DBGFH before reading DBGFL because reading DBGFL causes the FIFO pointers to advance to the next FIFO location. In event-only modes, there is no useful information in DBGFX and DBGFH so it is not necessary to read them before reading DBGFL. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 558: Debug Comparator A Extension Register (Dbg_Cax)
The RWA bit controls whether read or write is used in compare for Comparator A. The RWA bit is not used if RWAEN = 0. Write cycle will be matched. Read cycle will be matched. Reserved This field is reserved. This read-only field is reserved and always has the value 0. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 559: Debug Comparator B Extension Register (Dbg_Cbx)
RWBEN = 0.In full modes, RWAEN and RWA are used to control comparison of R/W and RWB is ignored. Write cycle will be matched. Read cycle will be matched. Reserved This field is reserved. This read-only field is reserved and always has the value 0. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 560: Debug Comparator C Extension Register (Dbg_Ccx)
The RWC bit controls whether read or write is used in compare for Comparator C. The RWC bit is not used if RWCEN = 0. Write cycle will be matched. Read cycle will be matched. Reserved This field is reserved. This read-only field is reserved and always has the value 0. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 561: Debug Fifo Extended Information Register (Dbg_Fx)
Bit16 This bit is the most significant bit of the 17-bit core address. 28.3.13 Debug Control Register (DBG_C) Address: 18C0h base + Ch offset = 18CCh Read DBGEN BRKEN LOOP1 Write Reset MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 562: Debug Trigger Register (Dbg_T)
In the case of an end- trace to reset where DBGEN=1 and BEGIN=0, the ARM and BRKEN bits are cleared but the remaining control bits in this register do not change after reset. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 563 0011 Event only B. 0100 A then event only B. 0101 A and B (full mode). 0110 A and not B (full mode). 0111 Inside range. 1000 Outside range. 1001-1111 No trigger. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 564: Debug Status Register (Dbg_S)
The ARMF bit indicates whether the debugger is waiting for trigger or waiting for the FIFO to fill. While DBGEN = 1, this status bit is a read-only image of the ARM bit in DBGC. Debugger not armed. Debugger armed. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 565: Debug Count Status Register (Dbg_Cnt)
0001 1 word valid. 0010 2 words valid. 0011 3 words valid. 0100 4 words valid. 0101 5 words valid. 0110 6 words valid. 0111 7 words valid. 1000 8 words valid. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 566: Functional Description
FIFO buffer. In loop1 capture mode, comparator C is not available for use as a normal hardware breakpoint. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 567: Breakpoints
DBG_C[TAG] affect all three comparators. When DBG_C[BRKEN] = 0, no CPU breakpoints are enabled. When DBG_C[BRKEN] = 1, CPU breakpoints are enabled and the DBG_C[TAG] bit determines whether the breakpoints will be tag-type or force-type MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 568: Trigger Selection
CPU break will be a tag-type or force-type breakpoint. When DBG_T[TRGSEL] is set, the R/W qualified comparator match signal also passes through the opcode tracking logic. If/when it propagates through this logic, it will cause a MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 569: Begin- And End-Trigger
DBG_C[ARM] is written to zero or when the DBG_C[DBGEN] bit is low. The TBC logic determines whether a trigger condition has been met based on the trigger mode and the trigger selection. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 570: Trigger Modes
B is compared. When the match condition for A or B is met, the corresponding flag in the DBG_S register is set. The A then event only B trigger mode is considered a begin-trigger type and the DBG_T[BEGIN] bit is ignored. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 571 28.4.4.3.9 Outside range, address < A or address > B In the outside range trigger mode, if the match condition for A or B is met, the corresponding flag in the DBGS register is set. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 572: Fifo
Start FIFO at trigger address, force CPU breakpoint when FIFO full Start FIFO at trigger opcode (No CPU breakpoint - keep running) Start FIFO at trigger opcode, force CPU breakpoint when FIFO full MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 573: Storing Data In Fifo
DBG_C[ARM] and DBG_S[ARMF] will be cleared and no more data will be stored. In non-event only end-trigger modes, if the trigger is at a change of flow address the trigger event will be stored in the FIFO. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 574 When DBG_T[TRGSEL] is clear and the DBG module is armed to trigger on begin- trigger types, the trigger event is detected on a program fetch of the target address, even when an interrupt becomes pending on the same cycle. In this scenario, the FIFO captures MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 575: Resets
16-bit CPU address 0xFFFE appears during the reset vector fetch • DBG_C = 0xC0 to enable and arm the DBG module • DBG_T = 0x40 to select a force-type trigger, a BEGIN trigger, and A-only trigger mode MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 576 Resets MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 577 Description Memory • Updated the register names in the Register addresses assignments Cyclic redundancy check • Corrected CRC_PL1[PH1] to CRC_PL1[PL1] (CRC) • Updated the registers descriptions in CRC_PH0, CRC_PH1, CRC_PL0 and CRC_PL1 MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 578 MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 579 Appendix B Changes between revision 4 and 3 Table B-1. Changes between revision 4 and 3 Chapter Description Throughout the book • Added new part of MC9S08SU8VFK. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 580 MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 581 • Updated V descriptions in the ADC analog supply and reference connections. REFH converter (ADC) Chapter 25 Gate Drive Unit • Updated Functional description (GDU) • Added a note to the GDU_SIGBIAS[BIASSEL]. MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 582 MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors...
Page 583 How to Reach Us: Information in this document is provided solely to enable system and software implementers to use NXP products. There are no express or implied copyright Home Page: licenses granted hereunder to design or fabricate any integrated circuits based nxp.com on the information in this document.

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NXP Semiconductors MC9S08SU16 Reference Manual

Chapter 1 About this Document

Chapter 2 Introduction

Chapter 3 Memory

Chapter 4

Chapter 5 Clock Management

Chapter 6 Power Management

Chapter 7 Signal Multiplexing and Signal Descriptions

Chapter 8 Port Control (PORT)

Chapter 9 System Integration Module (SIM)

Chapter 10 Central Processor Unit

Chapter 11 Flash Memory Module (FTMRH)

Chapter 13 Modulo Timer (MTIM)

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