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Field
Writing a one to FTACK3 clears FFLAG3. Writing a zero has no effect. Reset clears FTACK3. The fault
protection is enabled even when the PWM is not enabled; therefore, a fault is latched in, requiring it to be
cleared in order to prevent an interrupt when the PWM is enabled.
5
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
4
FAULT2 Pin Acknowledge
FTACK2
Writing a one to FTACK2 clears FFLAG2. Writing a zero has no effect. Reset clears FTACK2. The fault
protection is enabled even when the PWM is not enabled; therefore, a fault is latched in, requiring it to be
cleared in order to prevent an interrupt when the PWM is enabled.
3
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
2
FAULT1 Pin Acknowledge
FTACK1
Writing a one to FTACK1 clears FFLAG1. Writing a zero has no effect. Reset clears FTACK1. The fault
protection is enabled even when the PWM is not enabled; therefore, a fault is latched in, requiring it to be
cleared in order to prevent an interrupt when the PWM is enabled.
1
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
0
FAULT0 Pin Acknowledge
FTACK0
Writing a one to FTACK0 clears FFLAG0 Writing a zero has no effect. Reset clears FTACK0. The fault
protection is enabled even when the PWM is not enabled; therefore, a fault is latched in, requiring it to be
cleared in order to prevent an interrupt when the PWM is enabled.
26.4.6 PWM Fault Status Acknowledge Register: High
(PWM_FLTACKH)
After enabling clock to PWM, but before enabling any PWM
interrupt, clear all flags in FLTACK.
Address: 40h base + 5h offset = 45h
Bit
7
Read
FPIN3
Write
Reset
0
Field
7
FAULT3 Pin
FPIN3
This read-only bit reflects the current state of the filtered FAULT3 pin. A reset has no effect on FPIN3.
NXP Semiconductors
PWM_FLTACKL field descriptions (continued)
6
5
FFLAG3
FPIN2
0
0
PWM_FLTACKH field descriptions
Table continues on the next page...
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 26 Pulse Width Modulator (PWM)
Description
NOTE
4
3
FFLAG2
FPIN1
0
0
Description
2
1
FFLAG1
FPIN0
0
0
0
FFLAG0
0
511
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