Pinout; Signal Multiplexing And Pin Assignments - NXP Semiconductors MC9S08SU16 Reference Manual

Pinout

7.4 Pinout

7.4.1 Signal multiplexing and pin assignments

The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
24 QFN Pin Name
1 PTB5
2 PWM_UH
3 PWM_VH
4 PWM_WH
5 VCLAMP
6 VDD
7 VDDX
8 VSS
9 PTB6/
RESET_b
10 PTC0
11 PTB7/
BKGD/
MS
12 PTA7
13 PTA6
14 PTA5
15 PTA4
16 PTA3
17 PTA2
18 PTA1
19 PTA0
76
Default/ALT0
PWM_WL
PWM_UH
PWM_VH
PWM_WH
VCLAMP
VDD
VDDX
VSS
RESET_b
CMP_REF/ PWM_FAULT0
VREFH
BKGD/
MS
PWT1 TX
PWT0 RX
TX SDA
RX SCL
AMP1_M/ CLKOUT
ADC1AD1
AMP1_P/ XB_IN1
CMP2/
ADC1AD0
AMP0_M/ XB_OUT0
CMP1/
ADC0AD1
AMP0_P/ CLK_IN
CMP0/
ADC0AD0
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
ALT1 ALT2
TCLK
CLK_IN
CLKOUT
XB_OUT1
XB_IN1
XB_OUT0
XB_IN0
XB_OUT1
XB_OUT0
XB_IN1
XB_IN0
ALT3
PTB5
PTB6
PTC0
PTB7
PTA7/
KBI7
PTA6/
KBI6
PTA5/
KBI5
PTA4/
KBI4
PTA3/
KBI3
PTA2/
KBI2
PTA1/
KBI1
PTA0/
KBI0
NXP Semiconductors