NXP Semiconductors MC9S08SU16 Reference Manual page 143

Source Form Operation
ADD #opr8i
ADD opr8a
ADD opr16a
ADD oprx16,X
ADD oprx8,X Add without Carry
ADD ,X
ADD oprx16,SP
ADD oprx8,SP
AIS #opr8i Add Immediate Value
(Signed) to Stack
Pointer
AIX #opr8i Add Immediate Value
(Signed) to Index
Register (H:X)
AND #opr8i
AND opr8a
AND opr16a
AND oprx16,X
Logical AND
AND oprx8,X
AND ,X
AND oprx16,SP
AND oprx8,SP
ASL opr8a
ASLA
ASLX
ASL oprx8,X Arithmetic Shift Left
(same as LSL)
ASL ,X
ASL oprx8,SP
ASR opr8a
ASRA
ASRX
Arithmetic Shift Right
ASR oprx8,X
ASR ,X
ASR oprx8,SP
BCC rel Branch if Carry Bit
NXP Semiconductors
Table 10-3. Instruction Set Summary (continued)
Description
A ← (A) + (M)
SP ← (SP) + (M) where
M is sign extended to a
16-bit value
H:X ← (H:X) + (M)
where M is sign
extended to a 16-bit
value
A ← (A) & (M)
C ← MSB, LSB ← 0
MSB → MSB, LSB → C
Branch if (C) = 0
Clear
Table continues on the next page...
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 10 Central processor unit
Effect on CCR
Address
V H I N Z C
Mode
– IMM
↕ ↕ ↕ ↕ ↕
– DIR
↕ ↕ ↕ ↕ ↕
– EXT
↕ ↕ ↕ ↕ ↕
– IX2
↕ ↕ ↕ ↕ ↕
– IX1
↕ ↕ ↕ ↕ ↕
– IX
↕ ↕ ↕ ↕ ↕
– SP2
↕ ↕ ↕ ↕ ↕
– SP1
↕ ↕ ↕ ↕ ↕
– – – – – – IMM
– – – – – – IMM
0 – – – IMM
↕ ↕
0 – – – DIR
↕ ↕
0 – – – EXT
↕ ↕
0 – – – IX2
↕ ↕
0 – – – IX1
↕ ↕
0 – – – IX
↕ ↕
0 – – – SP2
↕ ↕
0 – – – SP1
↕ ↕
– – DIR
↕ ↕ ↕ ↕
– – INH
↕ ↕ ↕ ↕
– – INH
↕ ↕ ↕ ↕
– – IX1
↕ ↕ ↕ ↕
– – IX
↕ ↕ ↕ ↕
– – SP1
↕ ↕ ↕ ↕
– – DIR
↕ ↕ ↕ ↕
– – INH
↕ ↕ ↕ ↕
– – INH
↕ ↕ ↕ ↕
– – IX1
↕ ↕ ↕ ↕
– – IX
↕ ↕ ↕ ↕
– – SP1
↕ ↕ ↕ ↕
– – – – – – REL
– – – – – – DIR (b0)
AB ii 2
BB dd 3
CB hh ll 4
DB ee ff 4
EB ff 3
FB 3
9EDB ee ff 5
9EEB ff 4
A7 ii 2
AF ii 2
A4 ii 2
B4 dd 3
C4 hh ll 4
D4 ee ff 4
E4 ff 3
F4 3
9ED4 ee ff 5
9EE4 ff 4
38 dd 5
48 1
58 1
68 ff 5
78 4
9E68 ff 6
37 dd 5
47 1
57 1
67 ff 5
77 4
9E67 ff 6
24 rr 3
11 dd 5
143