Integration And Application Of The Ipc - NXP Semiconductors MC9S08SU16 Reference Manual

Interrupts
original value of IPM by writing 1 to the IPCSC[PULIPM] bit. In both cases, the IPMPS
is a shift register functioning as a pseudo stack register for storing the IPM. When the
IPM is updated, the original value is shifted into IPMPS. The IPMPS can store four levels
of IPM. If the last position of IPMPS is written, the PSF flag indicates that the IPMPS is
full. If all the values in the IPMPS were read, the PSE flag indicates that the IPMPS is
empty.

4.1.2.4 Integration and application of the IPC

All interrupt inputs that comes from peripheral modules are asynchronous signals. None
of the asynchronous signals of the interrupts are routed to IPC. The asynchronous signals
of the interrupts are routed directly to SIM module to wake system clocks in stop mode.
Additional care must be exercised when IRQ is reprioritized by IPC. CPU instructions
BIL and BIH need input from IRQ pin. If IRQ interrupt is masked, BIL and BIH still
work but the IRQ interrupt will not occur.
• The interrupt priority controller must be enabled to function. While inside an
interrupt service routine, some work has to be done to enable other higher priority
interrupts. The following is a pseudo code example written in assembly language:
INT_SER :
BCLR
.
.
.
.
.
CLI
enabled
.
.
.
.
BSET
RTI
• A minimum overhead of six bus clock cycles is added inside an interrupt services
routine to enable preemptive interrupts.
• As an interrupt of the same priority level is allowed to pass through IPC to HCS08
CPU, the flag generating the interrupt must be cleared before doing CLI to enable
preemptive interrupts.
58
INTFLAG,INTFLAG_R ; clear flag that generate interrupt
; do the most critical part
; which it cannot be interrupted
; global interrupt enable and nested interrupt
; continue the less critical
PULIPM, PULIPM_R ; restore the old IPM value before leaving
; then you can return
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
NXP Semiconductors