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NXP Semiconductors freescale semiconductor ColdFire MCF51CN128 Series Reference Manual

Integrated microcontroller

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MCF51CN128 ColdFire

Integrated

Microcontroller Reference Manual

Devices Supported:

MCF51CN128

Document Number: MCF51CN128RM

Rev. 6

12/2009

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Summary of Contents for NXP Semiconductors freescale semiconductor ColdFire MCF51CN128 Series

Page 1 ® MCF51CN128 ColdFire Integrated Microcontroller Reference Manual Devices Supported: MCF51CN128 Document Number: MCF51CN128RM Rev. 6 12/2009...
Page 2 How to Reach Us: Home Page: http://www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com Europe, Middle East, and Africa: Information in this document is provided solely to enable system and software Freescale Halbleiter Deutschland GmbH implementers to use Freescale Semiconductor products.
Page 3 Chapter 1 Device Overview The MCF51CN128 Series Microcontrollers ........1-1 1.1.1 Definition .
Page 4 Secure Mode ..............3-6 Run Modes .
Page 5 5.4.2.1 Pin Configuration Options ......... 5-4 5.4.2.2 Edge and Level Sensitivity .
Page 6 6.4.7 External Reference Clock ..........6-15 6.4.8 Fixed Frequency Clock .
Page 7 7.3.3.13 Fault-on-Fault Halt ..........7-18 7.3.3.14 Reset Exception .
Page 8 Pin Controls ..............9-4 9.2.1 Pin Controls Overview .
Page 9 10.6.2 Application 2: 16-bit Message Transmission using SPI Protocol ....10-9 Chapter 11 Mini-FlexBus 11.1 Introduction ..............11-1 11.1.1 Overview .
Page 10 12.2 External Signal Description ........... . 12-3 12.3 Register Definition .
Page 11 14.1.2.2 SPI Module Block Diagram ........14-3 14.1.3 SPI Baud Rate Generation .
Page 12 15.4 Functional Description ............15-11 15.4.1 Clock Select and Divide Control .
Page 13 16.2.4 Internal Loopback ........... . 16-4 16.3 External Signal Description .
Page 14 16.5.15Ethernet Error-Managing Procedure ........16-38 16.5.15.1 Transmission Errors .
Page 15 17.6 Interrupts ..............17-23 17.6.1 Byte Transfer Interrupt .
Page 16 19.4.1.1 Counter Clock Source ......... 19-14 19.4.1.2 Counter Overflow and Modulo Reset .
Page 17 20.4.1.6 Serial Interface Hardware Handshake Protocol ..... . 20-51 20.4.1.7 Hardware Handshake Abort Procedure ......20-53 20.4.2 Real-Time Debug Support .
Page 18 About This Book The primary objective of this reference manual is to define the MCF51CN128 processor for software and hardware developers. This book is written from the perspective of the MCF51CN128. The information in this book is subject to change without notice, as described in the disclaimers on the title page. As with any technical documentation, the reader needs to make sure to use the most recent version of the documentation.
Page 19 • Product briefs — Each device has a product brief that provides an overview of its features. This document is roughly equivalent to the overview (Chapter 1) of an device’s reference manual. • Application notes — These short documents address specific design issues useful to programmers and engineers working with Freescale Semiconductor processors.
Page 20 [signal_name] Reset value is determined by the polarity of the indicated signal. The following register fields are used: Indicates a reserved bit field in a memory-mapped register. These bits are always read as zeros. Indicates a reserved bit field in a memory-mapped register. These bits are always read as ones. R FIELDNAME Indicates a read/write bit.
Page 21 Chapter 1 Device Overview The MCF51CN128 Series Microcontrollers 1.1.1 Definition The MCF51CN128 series microcontrollers are systems-on-chips (SoCs) that are based on the V1 ColdFire core and: • Operate at processor core speeds up to 50.33 MHz (all peripherals except the SCIs operate at half of this speed.
Page 22 Device Overview 1.1.3 MCF51CN128 Series Device Comparison compares the MCF51CN128 series microcontrollers. Table 1-2 Table 1-2. MCF51CN128 Series Device Comparison MCF51CN128 Feature 80-pin 64-pin 48-pin Flash memory size (KB) RAM size (KB) V1 ColdFire core equiped with BDM (background debug module) and 2X3 Crossbar switch ADC (analog-to-digital converter) channels (12-bit) FEC (Fast Ethernet Controller with MII Interface)
Page 23 Device Overview Block Diagram MCF51CN128 Series 1.2.1 Block Diagram Figure 1-1 shows the connections between the MCF51CN128 series pins and functional units. MCF51CN128 Reference Manual, Rev. 6 Freescale Semiconductor...
Page 24 Device Overview PTA7/MII_RX_DV/MOSI2 VDDA/ VDDA Port C: Port C/G: PTA6/MII_RXD0/MISO2 VREFH VREFH ADP3- SDA1 IIC1 PTA5/MII_RXD1/SPSCK2 VSSA/ VSSA ADP0 SCL1 PTA4/MII_RXD2/RXD3 VREFL VREFL Port D: PTA3/MII_RXD3/TXD3 ADP8- Port C/G: PTA2/MII_MDC/SCL2 ADP4 SDA2 IIC2 PTA1/MII_MDIO/SDA2 Port E: SCL2 PTA0/PHYCLK ADP11- PTB7/MII_TXD2/TPM2CH1 ADP9 Port E: PTB6/MII_TXD1/TPM2CH0...
Page 25 Device Overview 1.2.2 Functional Units Table 1-3 describes the functional units of the MCF51CN128 series microcontrollers. Table 1-3. MCF51CN128 Series Functional Units Unit Function ADC (analog-to-digital converter) Measures analog voltages at up to 12 bits of resolution BDM (background debug module) Provides single pin debugging interface (part of the V1 ColdFire core) CF1CORE (V1 ColdFire core) Executes programs and interrupt handlers.
Page 26 Device Overview 1.2.3 Module Versions Table 1-4 provides the functional version of the on-chip modules Table 1-4. Module Versions Module Version Analog-to-Digital Converter (ADC12) Fast Ethernet Controller (FEC) General Purpose I/O (GPIO) Inter-Integrated Circuit (IIC) Interrupt Controller (CF1_INTC) Keyboard Interrupt (KBI) Low Power Oscillator (OSCVLP_25MHz...
Page 27 Device Overview V1 ColdFire Core The MCF51CN128 series devices contain a version of the V1 ColdFire platform that is optimized for area and low power. The CPU implements ColdFire instruction set architecture revision C (ISA_C) with a reduced programming model: •...
Page 28 Device Overview System Clock Generation and Distribution 1.4.1 Clock Distribution Diagram Figure 1-3 shows how clocks from the MCG and XOSC are distributed to the microcontroller’s other functional units. Some modules in the microcontroller have selectable clock inputs. All memory-mapped registers associated with the modules (except RGPIO) are clocked with BUSCLK.
Page 29 Device Overview 1.4.2 System Clocks Table 1-5 describes each of the system clocks. Table 1-5. System Clocks Clock Description OSCOUT This is the direct output of the external oscillator module and can be selected as the real-time counter clock source. This signal is used by the Real Time Counter, and the MCG. See Chapter 6, “Multipurpose Clock Generator (MCG)”...
Page 30 Device Overview 1.4.4 MCG Modes of Operation The MCG operates in one of the modes described in Table 1-6. This information has been abbreviated for clarity’s sake. See the MCG block specification for additional details. Table 1-6. MCG Modes Mode Description FLL Engaged Internal (FEI) Default.
Page 31 Device Overview Table 1-6. MCG Modes (continued) Mode Description Bypassed Low Power External (BLPE) MCGOUT is derived from the external reference clock. The external reference clock that is enabled can be produced by an external crystal, ceramic resonator, or another external clock source connected to the required crystal oscillator (XOSC).
Page 32 Device Overview 1.4.5 MCG Mode State Diagram Figure 1-4 shows the valid state transitions for the MCG. The arrows indicate the permitted mode transitions. See Chapter 6, “Multipurpose Clock Generator (MCG),” for additional details. Software must ensure that the system bus frequency is less than 125 kHz and the FLLs are disengaged prior to switching to BLPE and BLPI modes of operation.
Page 33 Chapter 2 Pins and Connections This section describes signals that connect to package pins. It includes pinout diagrams, recommended system connections, and detailed discussions of signals. Package Pin Assignments 2.1.1 Pinout: 80-Pin LQFP Figure 2-1 shows the pinout of the 80-pin LQFP. MCF51CN128 Reference Manual, Rev.
Page 34 Pins and Connections VDD1 PTG7/KBI1P7/FB_D1 VSS1 PTG6/KBI1P6/FB_D2 PTA0/PHYCLK PTG5/KBI1P5/FB_D3 PTA1/MII_MDIO/SDA2 PTG4/KBI1P4/FB_RW PTA2/MII_MDC/SCL2 PTG3/KBI1P3/FB_A5/FB_AD5/SDA1 PTA3/MII_RXD3/TXD3 PTG2/KBI1P2/FB_A6/FB_AD6/SCL1 PTA4/MII_RXD2/RXD3 PTG1/KBI1P1/FB_A7/FB_AD7/SDA2 PTA5/MII_RXD1/SPSCK2 PTG0/KBI1P0/FB_A8/FB_AD8/SCL2 PTA6/MII_RXD0/MISO2 PTD3/RGPIO3/RXD2/ADP4 PTA7/MII_RX_DV/MOSI2 80-Pin LQFP PTD2/RGPIO2/TXD2/ADP5 PTB0/MII_RX_CLK/SS2 PTD1/RGPIO1/RXD1/ADP6 PTB1/MII_RX_ER/TMRCLK1 PTD0/RGPIO0/TXD1/ADP7 PTF0/RGPIO8/FB_A19/FB_AD19 PTC7/SDA2/SPSCK1/ADP8 PTF1/RGPIO9/FB_A18/FB_AD18 PTC6/SCL2/MISO1/ADP9 PTF2/RGPIO10/FB_A17/FB_AD17 PTC5/MOSI1/ADP10 PTF3/RGPIO11/FB_A16/FB_AD16 PTC4/IRQ/SS1/ADP11 PTH0/FB_A15/FB_AD15 VSSA PTH1/FB_OE VDDA PTH2/FB_D7/TMRCLK1 VSS3...
Page 35 Pins and Connections 2.1.2 Pinout: 64-Pin LQFP Figure 2-2 shows the pinout of the 64-pin LQFP. VDD1 PTG3/KBI1P3/FB_A5/FB_AD5/SDA1 VSS1 PTG2/KBI1P2/FB_A6/FB_AD6/SCL1 PTA0/PHYCLK PTG1/KBI1P1/FB_A7/FB_AD7/SDA2 PTA1/MII_MDIO/SDA2 PTG0/KBI1P0/FB_A8/FB_AD8/SCL2 PTA2/MII_MDC/SCL2 PTD3/RGPIO3/RXD2/ADP4 PTA3/MII_RXD3/TXD3 PTD2/RGPIO2/TXD2/ADP5 PTA4/MII_RXD2/RXD3 PTD1/RGPIO1/RXD1/ADP6 PTA5/MII_RXD1/SPSCK2 PTD0/RGPIO0/TXD1/ADP7 64-Pin LQFP PTA6/MII_RXD0/MISO2 PTC7/SDA2/SPSCK1/ADP8 PTA7/MII_RX_DV/MOSI2 PTC6/SCL2/MISO1/ADP9 PTB0/MII_RX_CLK/SS2 PTC5/MOSI1/ADP10 PTB1/MII_RX_ER/TMRCLK1 PTC4/IRQ/SS1/ADP11 PTF0/RGPIO8/FB_A19/FB_AD19...
Page 36 Pins and Connections 2.1.3 Pinout: 48-Pin QFN Figure 2-3 shows the pinout of the 48-pin QFN. PTD3/RGPIO3/RXD2/ADP4 VDD1 PTD2/RGPIO2/TXD2/ADP5 VSS1 PTD1/RGPIO1/RXD1/ADP6 PTA0/PHYCLK PTD0/RGPIO0/TXD1/ADP7 PTA1/MII_MDIO/SDA2 PTC7/SDA2/SPSCK1/ADP8 PTA2/MII_MDC/SCL2 PTA3/MII_RXD3/TXD3 PTC6/SCL2/MISO1/ADP9 48-Pin QFN PTA4/MII_RXD2/RXD3 PTC5/MOSI1/ADP10 PTA5/MII_RXD1/SPSCK2 PTC4/IRQ/SS1/ADP11 PTA6/MII_RXD0/MISO2 VSSA PTA7/MII_RX_DV/MOSI2 VDDA PTB0/MII_RX_CLK/SS2 VSS3 PTB1/MII_RX_ER/TMRCLK1 VDD3 Figure 2-3.
Page 37 Pins and Connections Pin Assignment Tables MCF51CN128 family is available in 80-pin LQFP, 64-pin LQFP, and 48-pin QFN package options. Table 2-1 summarizes the functions available on each pin of the various package configurations. The default function column specifies the function of the given pin upon exiting the reset state. Alternate functions 1, 2 and 3 can be assigned to each pin under software control via the MC registers.
Page 38 Pins and Connections Table 2-1. MC51CN128 Package Pin Assignments (continued) 80-Pin 64-Pin 48-Pin Default Function Alt 1 Alt 2 Alt 3 Comment PTB2 MII_TX_ER — — PTB3 MII_TX_CLK MOSI1 — — PTB4 MII_TX_EN MISO1 — — PTB5 MII_TXD0 SPSCK1 — —...
Page 39 Pins and Connections Table 2-1. MC51CN128 Package Pin Assignments (continued) 80-Pin 64-Pin 48-Pin Default Function Alt 1 Alt 2 Alt 3 Comment PTD0/RGPIO0 — TXD1 ADP7 RGPIO_ENB selects between standard GPIO PTD1/RGPIO1 — RXD1 ADP6 and RGPIO PTD2/RGPIO2 — TXD2 ADP5 PTD3/RGPIO3 —...
Page 40 Pins and Connections Table 2-1. MC51CN128 Package Pin Assignments (continued) 80-Pin 64-Pin 48-Pin Default Function Alt 1 Alt 2 Alt 3 Comment PTD7RGPIO7 — SPSCK2 ADP3 RGPIO_ENB selects between standard GPIO and RGPIO PTE0 KBI2P0 MISO2 ADP2 — PTE1 KBI2P1 MOSI2 ADP1 —...
Page 41 Pins and Connections Table 2-2. Power/Ground Pinout Summary (continued) VDD4 VDDA VSS1 VSS2 VSS3 VSS4 VSSA Table 2-3. MII Pinout Summary 80-Pin 64-Pin 48-Pin Default Function Signals PTC1 PTC1/MII_COL/SCL1 MII_COL PTC2 PTC2/MII_CRS/SDA1 MII_CRS PTA2 PTA2/MII_MDC/SCL2 MII_MDC PTA1 PTA1/MII_MDIO/SDA2 MII_MDIO PTB0 PTB0/MII_RX_CLK/SS2 MII_RX_CLK PTA7...
Page 42 Pins and Connections Table 2-4. Mini-FlexBus Pinout Summary (continued) 80-Pin 64-Pin 48-Pin Default Function Signals Mini-FlexBus — — PTH5 PTH5/FB_A11/FB_AD11 FB_A11/FB_AD11 — — PTH4 PTH4/FB_A12/FB_AD12 FB_A12/FB_AD12 — PTF7/RGPIO15 PTF7/RGPIO15/FB_A13/FB_AD13/TPM2CH2 FB_A13/FB_AD13 — PTF6/RGPIO14 PTF6/RGPIO14/FB_A14/FB_AD14/TPM2CH1 FB_A14/FB_AD14 — — PTH0 PTH0/FB_A15/FB_AD15 FB_A15/FB_AD15 — PTF3/RGPIO11 PTF3/RGPIO11/FB_A16/FB_AD16 FB_A16/FB_AD16...
Page 43 Pins and Connections Table 2-5. IIC1 Pinout Summary Default 80-Pin 64-Pin 48-Pin Signals IIC1 Function — PTG2/KBI1P2 PTG2/KBI1P2/FB_A6/FB_AD6/SCL1 SCL1 PTC1 PTC1/MII_COL/SCL1 SCL1 — PTG3/KBI1P3 PTG3/KBI1P3/FB_A5/FB_AD5/SDA1 SDA1 PTC2 PTC2/MII_CRS/SDA1 SDA1 Table 2-6. IIC2 Pinout Summary 80-Pi 64-Pi Default 48-Pin Signals4 IIC2 Function —...
Page 44 Pins and Connections Table 2-8. SPI2 Pinout Summary (continued) PTA7 PTA7/MII_RX_DV/MOSI2 MOSI2 PTE1/KBI2P1 PTE1/KBI2P1/MOSI2/ADP1 MOSI2 PTA5 PTA5/MII_RXD1/SPSCK2 SPSCK2 PTD7RGPIO7 PTD7RGPIO7/SPSCK2/AD SPSCK2 PTB0 PTB0/MII_RX_CLK/SS2 PTE2/KBI2P2 PTE2/KBI2P2/SS2/ADP0 Table 2-9. SCI1 Pinout Summary 80-Pi 64-Pi Default 48-Pin Signals SCI1 Function PTD1/RGPIO1 PTD1/RGPIO1/RXD1/ADP6 RXD1 PTD0/RGPIO0 PTD0/RGPIO0/TXD1/ADP7 TXD1 Table 2-10.
Page 45 Pins and Connections Table 2-12. TPM1 Pinout Summary (continued) PTE4/KBI2P4 PTE4/KBI2P4/CLKOUT/TPM1CH TPM1CH1 PTE5/KBI2P5 PTE5/KBI2P5/IRQ/TPM1CH2 TPM1CH2 Table 2-13. TPM2 Pinout Summary Default 80-Pin 64-Pin 48-Pin Signals TMR2 Function — — PTH2 PTH2/FB_D7/TMRCLK1 TMRCLK1 PTB1 PTB1/MII_RX_ER/TMRCLK1 TMRCLK1 — PTF4/RGPIO1 PTF4/RGPIO12/FB_D5/TMRCLK2 TMRCLK2 — PTF5/RGPIO1 PTF5/RGPIO13/FB_D4/TPM2CH0 TPM2CH0...
Page 46 Pins and Connections Table 2-15. ADC Pinout Summary (continued) PTD7/RGPIO7 PTD7/RGPIO7/SPSCK2/ADP ADP3 PTD3/RGPIO3 PTD3/RGPIO3/RXD2/ADP4 ADP4 PTD2/RGPIO2 PTD2/RGPIO2/TXD2/ADP5 ADP5 PTD1/RGPIO1 PTD1/RGPIO1/RXD1/ADP6 ADP6 PTD0/RGPIO0 PTD0/RGPIO0/TXD1/ADP7 ADP7 PTC7 PTC7/SDA2/SPSCK1/ADP8 ADP8 PTC6 PTC6/SCL2/MISO1/ADP9 ADP9 PTC5 PTC5/MOSI1/ADP10 ADP10 PTC4 PTC4/IRQ/SS1/ADP11 ADP11 Table 2-16. GPIO Pinout Summary Default 80-Pin 64-Pin...
Page 47 Pins and Connections Table 2-16. GPIO Pinout Summary (continued) Default 80-Pin 64-Pin 48-Pin Signals GPIO Function PTC5 PTC5/MOSI1/ADP10 PTC5 PTC6 PTC6/SCL2/MISO1/ADP9 PTC6 PTC7 PTC7/SDA2/SPSCK1/ADP8 PTC7 PTD0/RGPIO0 PTD0/RGPIO0/TXD1/ADP7 PTD0 PTD1/RGPIO1 PTD1/RGPIO1/RXD1/ADP6 PTD1 PTD2/RGPIO2 PTD2/RGPIO2/TXD2/ADP5 PTD2 PTD3/RGPIO3 PTD3/RGPIO3/RXD2/ADP4 PTD3 PTD4/RGPIO4 PTD4/RGPIO4/EXTAL PTD4 PTD5/RGPIO5 PTD5/RGPIO5/XTAL PTD5...
Page 48 Pins and Connections Table 2-16. GPIO Pinout Summary (continued) Default 80-Pin 64-Pin 48-Pin Signals GPIO Function — PTG1/KBI1P1 PTG1/KBI1P1/FB_A7/FB_AD7/SDA2 PTG1 — PTG2/KBI1P2 PTG2/KBI1P2/FB_A6/FB_AD6/SCL1 PTG2 — PTG3/KBI1P3 PTG3/KBI1P3/FB_A5/FB_AD5/SDA1 PTG3 — — PTG4/KBI1P4 PTG4/KBI1P4/FB_RW PTG4 — — PTG5/KBI1P5 PTG5/KBI1P5/FB_D3 PTG5 — — PTG6/KBI1P6 PTG6/KBI1P6/FB_D2 PTG6...
Page 49 Pins and Connections Table 2-17. KBI1 Pinout Summary (continued) Default 80-Pin 64-Pin 48-Pin Signals KBI1 Function — — PTG5/KBI1P5 PTG5/KBI1P5/FB_D3 KBI1P5 — — PTG6/KBI1P6 PTG6/KBI1P6/FB_D2 KBI1P6 — — PTG7/KBI1P7 PTG7/KBI1P7/FB_D1 KBI1P7 Table 2-18. KBI2 Pinout Summary Default 80-Pin 64-Pin 48-Pin Signals KBI2 Function...
Page 50 Pins and Connections Table 2-19. RGPIO Pinout Summary (continued) Default 80-Pin 64-Pin 48-Pin Signals RGPIO Function PTD4/RGPIO4 PTD4/RGPIO4/EXTAL RGPIO4 PTD5/RGPIO5 PTD5/RGPIO5/XTAL RGPIO5 BKGD/MS BKGD/MS/PTD6/RGPIO6 RGPIO6 PTD7/RGPIO7 PTD7/RGPIO7/SPSCK2/ADP3 RGPIO7 — PTF0/RGPIO8 PTF0/RGPIO8/FB_A19/FB_AD19 RGPIO8 Pin Mux Controls Package pins on the MCF51CN128 can be programmed for up to four different functions using the Pin Mux Control Registers.
Page 51 Pins and Connections Table 2-20. Pin Mux Control Registers 0x(FF)FF_80C PTFPF1 0x(FF)FF_80C PTFPF2 0x(FF)FF_80C PTGPF1 0x(FF)FF_80C PTGPF2 0x(FF)FF_80C PTHPF1 0x(FF)FF_80C PTHPF2 0x(FF)FF_80D PTJPF1 0x(FF)FF_80D PTJPF2 MCF51CN128 Reference Manual, Rev. 6 Freescale Semiconductor 2-19...
Page 52 Pins and Connections Table 2-21. Pin Mux Control Register Bits Register Bit Mux Control Port PTA0 Pin Mux Controls PTA0 PHYCLK Reserved Reserved Port PTA1 Pin Mux Controls PTA1 MII_MDIO Reserved SDA2 Port PTA2 Pin Mux Controls PTA2 MII_MDC Reserved SCL2 Port PTA3 Pin Mux Controls PTA3...
Page 53 Pins and Connections Table 2-21. Pin Mux Control Register Bits (continued) Register Bit Mux Control MISO2 Reserved Port PTA7 Pin Mux Controls PTA7 MII_RX_DV MOSI2 Reserved Port PTB0 Pin Mux Controls PTB0 MII_RX_CLK Reserved Port PTB1 Pin Mux Controls PTB1 MII_RX_ER Reserved TMRCLK1...
Page 54 Pins and Connections Table 2-21. Pin Mux Control Register Bits (continued) Register Bit Mux Control PTB5 MII_TXD0 SPSCK1 Reserved Port PTB6 Pin Mux Controls PTB6 MII_TXD1 Reserved TPM2CH0 Port PTB7 Pin Mux Controls PTB7 MII_TXD2 Reserved TPM2CH1 Port PTC0 Pin Mux Controls PTC0 MII_TXD3 Reserved...
Page 55 Pins and Connections Table 2-21. Pin Mux Control Register Bits (continued) Register Bit Mux Control Reserved Port PTC4 Pin Mux Controls PTC4 ADP11 Port PTC5 Pin Mux Controls PTC5 Reserved MOSI1 ADP10 Port PTC6 Pin Mux Controls PTC6 SCL2 MISO1 ADP9 Port PTC7 Pin Mux Controls PTC7...
Page 56 Pins and Connections Table 2-21. Pin Mux Control Register Bits (continued) Register Bit Mux Control Reserved TXD2 ADP5 Port PTD3 Pin Mux Controls PTD3/RGPIO3 Reserved RXD2 ADP4 Port PTD4 Pin Mux Controls PTD4/RGPIO4 Reserved Reserved EXTAL Port PTD5 Pin Mux Controls PTD5/RGPIO5 Reserved Reserved...
Page 57 Pins and Connections Table 2-21. Pin Mux Control Register Bits (continued) Register Bit Mux Control Port PTE1 Pin Mux Controls PTE1 KBI2P1 MOSI2 ADP1 Port PTE2 Pin Mux Controls PTE2 KBI2P2 ADP0 Port PTE3 Pin Mux Controls PTE3 KBI2P3 Reserved TPM1CH0 Port PTE4 Pin Mux Controls PTE4...
Page 58 Pins and Connections Table 2-21. Pin Mux Control Register Bits (continued) Register Bit Mux Control FB_CS0 RXD3 Port PTF0 Pin Mux Controls PTF0/RGPIO8 Reserved FB_A19/FB_AD19 Reserved Port PTF1 Pin Mux Controls PTF1/RGPIO9 Reserved FB_A18/FB_AD18 Reserved Port PTF2 Pin Mux Controls PTF2/RGPIO10 Reserved FB_A17/FB_AD17...
Page 59 Pins and Connections Table 2-21. Pin Mux Control Register Bits (continued) Register Bit Mux Control PTF6/RGPIO14 Reserved FB_A14/FB_AD14 TPM2CH1 Port PTF7 Pin Mux Controls PTF7/RGPIO15 Reserved FB_A13/FB_AD13 TPM2CH2 Port PTG0 Pin Mux Controls PTG0 KBI1P0 FB_A8/FB_AD8 SCL2 Port PTG1 Pin Mux Controls PTG1 KBI1P1 FB_A7/FB_AD7...
Page 60 Pins and Connections Table 2-21. Pin Mux Control Register Bits (continued) Register Bit Mux Control Reserved Port PTG5 Pin Mux Controls PTG5 KBI1P5 FB_D3 Reserved Port PTG6 Pin Mux Controls PTG6 KBI1P6 FB_D2 Reserved Port PTG7 Pin Mux Controls PTG7 KBI1P7 FB_D1 Reserved...
Page 61 Pins and Connections Table 2-21. Pin Mux Control Register Bits (continued) Register Bit Mux Control Reserved FB_D6 TPM2CH0 Port PTH4 Pin Mux Controls PTH4 Reserved FB_A12/FB_AD12 Reserved Port PTH5 Pin Mux Controls PTH5 Reserved FB_A11/FB_AD11 Reserved Port PTH6 Pin Mux Controls PTH6 Reserved FB_A10/FB_AD10...
Page 62 Pins and Connections Table 2-21. Pin Mux Control Register Bits (continued) Register Bit Mux Control Port PTJ2 Pin Mux Controls PTJ2 Reserved FB_A3/FB_AD3 Reserved Port PTJ3 Pin Mux Controls PTJ3 Reserved FB_A2/FB_AD2 Reserved Port PTJ4 Pin Mux Controls PTJ4 Reserved FB_A1/FB_AD1 Reserved Port PTJ5 Pin Mux Controls...
Page 63 Pins and Connections PTA0/PHYCLK REFH BYAD PTA1/MII_MDIO/SDA2 0.1 μF PTA2/MII_MDC/SCL2 PORT REFL PTA3/MII_RXD3/TXD3 PTA4/MII_RXD2/RXD3 PTA5/MII_RXD1/SPSCK2 0.1 μF PTA6/MII_RXD0/MISO2 MCF51CN128 PTA7/MII_RX_DV/MOSI2 PTB0/MII_RX_CLK/SS2 0.1 μF PTB1/MII_RX_ER/TMRCLK1 PTB2/MII_TX_ER/SS1 PORT PTB3/MII_TX_CLK/MOSI1 PTB4/MII_TX_EN/MISO1 PTB5/MII_TXD0/SPSCK1 0.1 μF PTB6/MII_TXD1/TPM2CH0 PTB7/MII_TXD2/TPM2CH1 SYSTEM PTC0/MII_TXD3/TPM2CH2 POWER PTC1/MII_COL/SCL1 PTC2/MII_CRS/SDA1 3.3 V 0.1 μF 10 μF RESET/PTC3...
Page 64 Pins and Connections 2.4.1 Power and V are the primary power supply pins for the microcontroller. This voltage source DD1.2.3.4 SS1,2,3,4 supplies power to all I/O buffer circuitry and to an internal voltage regulator. The internal voltage regulator provides a regulated lower-voltage source to the CPU and other internal circuitry of the microcontroller. Typically, application systems have two separate capacitor values across the power pins.
Page 65 Pins and Connections 2.4.3 RESET/PTC3 The RESET/PTC3 pin defaults to hardware reset upon a power-on-reset event. Unless otherwise programmed, it continues in that role indefinitely. It can also be programmed as an open drain GPIO output. It should not be programmed as a GPIO input, as an external driver on that pin could drive a zero on that pin during power up, which would prevent the part from exiting the power-on-reset sequence.
Page 66 Pins and Connections microcontroller’s BDC clock could be as fast as the bus clock rate, so there should never be any significant capacitance connected to the BKGD/MS pin that could interfere with background serial communications. Although the BKGD/MS pin is a pseudo open-drain pin, the background debug communication protocol provides brief, actively driven, high speed-up pulses to ensure fast rise times.
Page 67 Chapter 3 Modes of Operation Introduction The operating modes of the MCF51CN128 are described in this chapter. Entry into each mode, exit from each mode, and functionality while in each of the modes are described. The overall system mode is generally a function of a number of separate, but inter-related variables: debug mode, security mode, power mode, and clock mode.
Page 68 Modes of Operation Overview The ColdFire CPU has two primary user modes of operation: run and stop. (The CPU also supports a halt mode that is used strictly for debug operations.) The STOP instruction is used to invoke stop and wait modes for this family of devices.
Page 69 Modes of Operation Table 3-2. CPU / Power Mode Selections SOPT1 XCSR SPMSC1 SPMSC2 Effects on Sub-System CPU and Mode of Operation Peripheral Switche Clocks BDC Clock Power Run mode - processor and peripherals clocked normally. On. MCG in any mode Note: When not needed, the BDC...
Page 70 Modes of Operation Stop4 Stop3 Mode Regulator State Full On Wait Full On Stop4 Full On Stop2 LPrun LPrun Standby LPwait Standby Stop3 Standby Stop2 Partial Power Off Wait LPwait Figure 3-2. Allowable Power Mode Transitions for the MCF51CN128 Series Figure 3-2 illustrates mission mode state transitions allowed between the legal states shown in Table...
Page 71 Modes of Operation Stop4 Stop3 Halt Stop2 LPrun Wait LPwait Figure 3-3. All Allowable Power Mode Transitions for MCF51CN128 Table 3-3 defines triggers for the various state transitions shown in Figure 3-2. Table 3-3. Triggers for Transitions Shown in Figure 3-2 Transition # From Trigger...
Page 72 Modes of Operation Table 3-3. Triggers for Transitions Shown in Figure 3-2 (continued) Transition # From Trigger Stop3 Interrupt when SPMSC2[LPWUI] is set Pre-configure settings shown in Table 3-2, execute Stop3 STOP instruction When a BACKGROUND command is received Stop4 Halt through the BKGD/MS pin (XCSR[ENBDM] must be set).
Page 73 Modes of Operation Run Modes 3.6.1 Run Mode Run mode is the normal operating mode for this device. This mode is selected when the BKGD/MS pin is high at the rising edge of the internal reset signal. Upon exiting reset, the CPU fetches the supervisor SR and initial PC from locations 0x(00)00_0000 and 0x(00)00_0004 and executes code starting at the newly set value of the PC.
Page 74 Modes of Operation Wait Modes 3.7.1 Wait Mode Wait mode is entered by executing a STOP instruction after configuring the device as shown in Table 3-2. After execution of the STOP instruction, the CPU enters a low-power state in which it is not clocked. The V1 ColdFire core does not differentiate between stop and wait modes.
Page 75 Modes of Operation Stop Modes One of three stop modes is entered upon execution of a STOP instruction when SOPT1[STOPE] is set and SOPT1[WAITE] is cleared. In stop3 mode, the bus and CPU clocks are halted. If XCSR[ENBDM] is set prior to entering stop4, only the peripheral clocks are halted.
Page 76 Modes of Operation • The LVD reset function is enabled and the MCU remains in the reset state if V is below the LVD trip point (low trip point selected due to POR). • The CPU initiates reset exception processing by fetching the vectors at 0x(00)00_0000 and 0x(00)00_0004.
Page 77 Modes of Operation 3.8.3 Stop4 Mode Stop4 is differentiated from stop2 and stop3 in that the on-chip regulator is fully engaged. Entry into halt mode from run mode is enabled if the XCSR[ENBDM] bit is set. This register is described Chapter 20, “Version 1 ColdFire Debug (CF1_DEBUG).”...
Page 78 Modes of Operation Analog modules must be in their low-power mode when the device is operated in this state. ADC-specific mode where the device is in soft regulation and the normal peripheral clock is stopped. The ADC can only be run using its low-power mode and internally generated asynchronous ADACK clock.
Page 79 Modes of Operation Table 3-5. Low-Power Mode Behavior (continued) Mode Peripheral Stop2 Stop3 Stop4 LPwait Wait LPrun SPIx SoftNoClk FullNoClk SoftOn FullOn SoftOn TPMx SoftNoClk FullNoClk SoftOn FullOn SoftOn Voltage Regulator / PMC Partial Soft Regulation. Full SoftOn FullOn SoftOn Shutdown.
Page 80 Chapter 4 Memory MCF51CN128 Series Memory Map 80-pin versions of the device allow flash and memory to be supplemented with off-chip storage via the Mini-FlexBus, providing a continuous memory range from 0x(00)00 0000 to 0x(00)C0 0000. Address Range V1 ColdFire Memory Usage 0x(00)00_0000 Allocated to on-chip flash memory...
Page 81 Memory Figure 4-1 is the generic, high level, memory map applicable to the MCF51CN128 family. Devices (including the MCF51CN128) which include off-chip expansion capability alias smaller memories across the range shown as shown in Figure 4-2. 0x(00)00_0000 128K bytes of physical flash memory 0x(00)01_FFFF 0x(00)02_0000...
Page 82 Memory Table 4-1. CPU Access Type Allowed by Region Read Write Base Address Region Byte Word Long Byte Word Long Flash 0x(00)00_0000 — — 0x(00)80_0000 Rapid GPIO 0x(00)C0_0000 8-bit Peripherals 0x(FF)FF_8000 Fast Ethernet Controller 0x(FF)FF_E000 — — — — Mini-FlexBus 0x(FF)FF_E800 Allowed access types are peripheral specific.
Page 83 Memory Table 4-2. High Level Peripheral Memory Map (continued) Peripheral Description Instance Name BaseAddress Port Control Port I/O Control Module 0x(FF)FF_8068 Module Keyboard Interrupt Module KBI1 0x(FF)FF_806C Port I/O Module General Purpose I/O 0x(FF)FF_8070 Port Control Port I/O Control Module 0x(FF)FF_8078 Module Port I/O Module...
Page 84 Memory The MCF51CN128 series microcontrollers use an 8-bit peripheral bus. The bus bridge from the ColdFire system bus to the peripheral bus is capable of serializing 16-bit accesses into two 8-bit accesses and 32-bit access into four 8-bit accesses. This can be used to speed access to properly aligned peripheral registers. However, not all peripheral registers are aligned to take advantage of this feature.
Page 85 Memory Table 4-3. Detailed Peripheral Memory Map (continued) CLR[7:0] (Write only) 0x(00)C0_0006 RGPIO RESERVED DATA[15:8] (Read only) DATA[7:0] (Read only) 0x(00)C0_0008 RGPIO RESERVED DIR[15:8] (Read only) DIR[7:0] (Read only) 0x(00)C0_000A RGPIO RGPIO_SET SET[15:8] (Write only) SET[7:0] (Write only) 0x(00)C0_000A RGPIO RESERVED DATA[15:8] (Read only) DATA[7:0] (Read only)
Page 86 Memory Table 4-3. Detailed Peripheral Memory Map (continued) 0x(FF)FF_802A PTCDS PTCDS7 PTCDS6 PTCDS5 PTCDS4 PTCDS3 PTCDS2 PTCDS1 PTCDS0 0x(FF)FF_802B PTCIFE PTCIFE7 PTCIFE6 PTCIFE5 PTCIFE4 PTCIFE3 PTCIFE2 PTCIFE1 PTCIFE0 Address Peripheral Register Bit 7 Bit 0 0x(FF)FF_8030 PTDD PTDD7 PTDD6 PTDD5 PTDD4 PTDD3 PTDD2...
Page 87 Memory Table 4-3. Detailed Peripheral Memory Map (continued) 0x(FF)FF_806A PTGDS PTGDS7 PTGDS6 PTGDS5 PTGDS4 PTGDS3 PTGDS2 PTGDS1 PTGDS0 0x(FF)FF_806B PTGIFE PTGIFE7 PTGIFE6 PTGIFE5 PTGIFE4 PTGIFE3 PTGIFE2 PTGIFE1 PTGIFE0 Address Peripheral Register Bit 7 Bit 0 0x(FF)FF_806C KBI1 KBI1SC KBACK KBIE KBIMOD 0x(FF)FF_806D KBI1...
Page 88 Memory Table 4-3. Detailed Peripheral Memory Map (continued) 0x(FF)FF_80CE PTHPF1 0x(FF)FF_80CF PTHPF2 0x(FF)FF_80D0 PTJPF1 0x(FF)FF_80D1 PTJPF2 Address Peripheral Register Bit 7 Bit 0 0x(FF)FF_80E0 IRQSC IRQPDD IRQEDG IRQPE IRQF IRQACK IRQIE IRQMOD Address Peripheral Register Bit 7 Bit 0 0x(FF)FF_8100 ILOP ILAD 0x(FF)FF_8101...
Page 89 Memory Table 4-3. Detailed Peripheral Memory Map (continued) 0x(FF)FF_8160 SCI1 SCI1BDH LBKDIE RXEDGI SBR12 SBR11 SBR10 SBR9 SBR8 0x(FF)FF_8161 SCI1 SCI1BDL SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 0x(FF)FF_8162 SCI1 SCI1C1 LOOPS SCISWAI RSRC WAKE 0x(FF)FF_8163 SCI1 SCI1C2 TCIE ILIE 0x(FF)FF_8164 SCI1...
Page 90 Memory Table 4-3. Detailed Peripheral Memory Map (continued) 0x(FF)FF_81E0 SPI2 SPI2C1 SPIE SPTIE MSTR CPOL CPHA SSOE LSBFE 0x(FF)FF_81E1 SPI2 SPI2C2 MODFEN BIDIROE SPISWAI SPC0 0x(FF)FF_81E2 SPI2 SPI2BR SPPR SPTEF MODF 0x(FF)FF_81E3 SPI2 SPI2S SPRF 0x(FF)FF_81E4 SPI2 RESERVED — 0x(FF)FF_81E5 SPI2 SPI2D DATA...
Page 91 Memory Table 4-3. Detailed Peripheral Memory Map (continued) 0x(FF)FF_8244 MCGC3 LOLIE PLLS DIV32 VDIV 0x(FF)FF_8245 MCGC4 DMX32 DRST_DRS 0x(FF)FF_8246 RESERVED — — — — — — Address Peripheral Register Bit 7 Bit 0 0x(FF)FF_8260 TPM1 TPM1SC TOIE CPWMS CLKS 0x(FF)FF_8261 TPM1 TPM1CNTH Bit 15...
Page 92 Memory Table 4-3. Detailed Peripheral Memory Map (continued) 0x(FF)FF_82A3 MTIM1 MTIM1MOD Address Peripheral Register Bit 7 Bit 0 0x(FF)FF_82C0 RTCSC RTIF RTCLKS RTIE RTCPS 0x(FF)FF_82C1 RTCCNT RTCCNT 0x(FF)FF_82C2 RTCMOD RTCMOD Address Peripheral Register Bit 7 Bit 0 0x(FF)FF_82E0 FTSR FCDIV FDIVLD PRDIV8 FDIV...
Page 93 Memory Table 4-3. Detailed Peripheral Memory Map (continued) 0x(FF)FF_E014 FEC_TDAR TDAR 0x(FF)FF_E018 FEC_R_DES_ACT BYTE0 IVE_CL BYTE1 BYTE2 BYTE3 0x(FF)FF_E01C FEC_X_DES_ACT BYTE0 IVE_CL BYTE1 BYTE2 BYTE3 0x(FF)FF_E020 FEC_IEVENT_SE TFINT_E TXB_EN RFINT_E RXB_EN 0x(FF)FF_E024 FEC_ECR TEST-MD ETHER_E RESET 0x(FF)FF_E040 FEC_MMFR PA[4:1] PA[0] DATA[15:8] DATA[7:0] 0x(FF)FF_E044...
Page 94 Memory Table 4-3. Detailed Peripheral Memory Map (continued) 0x(FF)FF_E080 FEC_R_ACTIVATE R_ACTIV R_STATE 0x(FF)FF_E084 FEC_RCR MAX_FL[10:8] MAX_FL[7:0] BC_REJ PROM MII_MOD LOOP 0x(FF)FF_E088 FEC_R_HASH FCE_DC MUL_TC HASH 0x(FF)FF_E08C FEC_R_DATA R_DATA[31:24] R_DATA[23:16] R_DATA[15:8] R_DATA[7:0] 0x(FF)FF_E090 FEC_AR_DONE AR_HM_B AR_EM_ 0x(FF)FF_E094 FEC_R_TEST R_DATA_ BABR R_ADDR _ARM R_TEST 0x(FF)FF_E098...
Page 95 Memory Table 4-3. Detailed Peripheral Memory Map (continued) 0x(FF)FF_E0C4 FEC_TCR RFC_PAU TFC_PAU FDEN 0x(FF)FF_E0C8 FEC_BACKOFF RANDOM[9:3] RANDOM[2:0] 0x(FF)FF_E0CC FEC_X_DATA X_DATA[31:24] X_DATA[23:16] X_DATA[15:8] X_DATA[7:0] 0x(FF)FF_E0D0 FEC_X_STATUS 0x(FF)FF_E0D4 RESERVED — 0x(FF)FF_E0D7 — 0x(FF)FF_E0D8 FEC_X_TEST HBERR BABT X_SPACE X_DONE X_ACCE X_EARLY _CLSN X_TEST COLL SLOT 0x(FF)FF_E0DC...
Page 96 Memory Table 4-3. Detailed Peripheral Memory Map (continued) 0x(FF)FF_E0E8 FEC_PAUR PADDR2[15:8] PADDR2[7:0] TYPE[15:8] TYPE[7:0] 0x(FF)FF_E0EC FEC_OPD OPCODE[15:8] OPCODE[7:0] PAUSE_DUR[15:8] PAUSE_DUR[7:0] 0x(FF)FF_E100 FEC_D_INSTR_R INSTR[14:7] INSTR[6:0] 0x(FF)FF_E104 FEC_D_CONTEX TCONTEXT T_REG RCONTEXT Z_FLAG 0x(FF)FF_E108 FEC_D_TEST_CN TEST_MO READ_R HOLD 0x(FF)FF_E10C FEC_D_ACC_RE ACC_REG[31:24] ACC_REG[23:16] ACC_REG[15:8] ACC_REG[7:0] 0x(FF)FF_E110 FEC_D_ONES...
Page 97 Memory Table 4-3. Detailed Peripheral Memory Map (continued) 0x(FF)FF_E11C FEC_IALR IALR[31:24] IALR[24:16] IALR[15:8] IALR[7:0] 0x(FF)FF_E120 FEC_GAUR GAUR[31:24] GAUR[23:16] GAUR[15:8] GAUR[7:0] 0x(FF)FF_E124 FEC_GALR GALR[31:24] GALR[23:17] GALR[15:8] GALR[7:0] 0x(FF)FF_E128 FEC_RANDOM RANDOM[31:24] RANDOM[23:16] RANDOM[15:8] RANDOM[7:0] 0x(FF)FF_E12C FEC_RAND1 RAND1[31:24] RAND1[23:16] RAND1[15:8] RAND1[7:0] 0x(FF)FF_E130 FEC_TMP TMP[31:24] TMP[23:16] TMP[15:8]...
Page 98 Memory Table 4-3. Detailed Peripheral Memory Map (continued) R_BOUND[9:8] R_BOUND[7:2] 0x(FF)FF_E150 FEC_FRSR R_FSTART[9:8] R_FSTART[7:2] 0x(FF)FF_E154 FEC_R_COUNT R_COUNT 0x(FF)FF_E158 FEC_R_LAG R_LAG[9:8] R_LAG[7:2] 0x(FF)FF_E15C FEC_R_READ R_READ[9:8] R_READ[7:2] 0x(FF)FF_E160 FEC_R_WRITE R_WRITE[9:8] R_WRITE[7:2] 0x(FF)FF_E164 FEC_X_COUNT X_COUNT 0x(FF)FF_E168 FEC_X_LAG X_LAG[9:8] X_LAG[7:2] 0x(FF)FF_E16C FEC_X_RETRY X_RETRY[31:24] X_RETRY[24:16] X_RETRY[15:8] X_RETRY[7:0] 0x(FF)FF_E170...
Page 99 Memory Table 4-3. Detailed Peripheral Memory Map (continued) 0x(FF)FF_E174 FEC_X_READ X_READ[9:8] X_READ[7:2] 0x(FF)FF_E180 FEC_E_RDSR R_DES_START[31:24] R_DES_START[23:16] R_DES_START[15:8] R_DES_START[15:2] 0x(FF)FF_E184 FEC_E_TDSR X_DES_START[31:24] X_DES_START[23:16] X_DES_START[15:8] X_DES_START[15:2] 0x(FF)FF_E188 FEC_EMRBR R_BUF_SIZE[6:4] R_BUF_SIZE[3:0] 0x(FF)FF_E18C RESERVED — 0x(FF)FF_E7FF — 30/22/14/ 29/21/13/ 28/20/12/ 27/19/11/ 26/18/10/ Address Peripheral Register 25/17/9/1 31/23/15/7...
Page 100 Memory Table 4-3. Detailed Peripheral Memory Map (continued) 0x(FF)FF_E814 MBCSCR1 ASET RDAH WRAH Address Peripheral Register Bit 15/7 14/6 13/5 12/4 11/3 10/2 Bit 8/0 0x(FF)FF_FFCC INTC INTC_ORMR FECDO 0x(FF)FF_FFCD SCI3DO Address Peripheral Register Bit 7 Bit 0 0x(FF)FF_FFD3 INTC INTC_FRC LVL1 LVL2...
Page 101 Memory 16 15 Longword 0x(00)00_0000 Word 0x(00)00_0000 Word 0x(00)00_0002 Byte 0x(00)00_0000 Byte 0x(00)00_0001 Byte 0x(00)00_0002 Byte 0x(00)00_0003 Longword 0x(00)00_0004 Word 0x(00)00_0004 Word 0x(00)00_0006 Byte 0x(00)00_0004 Byte 0x(00)00_0005 Byte 0x(00)00_0006 Byte 0x(00)00_0007 Longword 0x(FF)FF_FFFC Word 0x(FF)FF_FFFC Word 0x(FF)FF_FFFE Byte 0x(FF)FF_FFFC Byte 0x(FF)FF_FFFD Byte 0x(FF)FF_FFFE Byte 0x(FF)FF_FFFF Figure 4-3.
Page 102 Memory Table 4-5. Reserved Flash Memory Addresses Address Register 0x(00)00_03FC– Reserved — — — — — — — — 0x(00)00_03FD 0x(00)00_03FE Storage of FTRIM FTRIM 0x(00)00_03FF Storage of TRIM MCGTRM 0x(00)00_0400– 8-Byte Backdoor Comparison Key 0x(00)00_0407 0x(00)00_0408– Reserved — — —...
Page 103 Memory Flash Memory The flash memory is intended primarily for program storage and read-only data. In-circuit programming allows the operating program to be loaded into the flash memory after final assembly of the application product. It is possible to program the entire array through the single-wire background debug interface. Because no special voltages are needed for flash erase and programming operations, in-application programming is also possible through other software-controlled communication paths.
Page 104 Memory • Fast program and sector erase operation • Burst program command for faster flash array program times • Single power supply program and erase • Command interface for fast program and erase operation • Up to 100,000 program/erase cycles at typical voltage and temperature •...
Page 105 Memory Table 4-8. FCDIV Field Descriptions Field Description Clock Divider Load Control. When writing to the FCDIV register for the first time after a reset, the value written FDIVLD to this bit controls the future ability to write to the FCDIV register: 0 Locks the FCDIV register contents;...
Page 106 Memory 4.4.2.3 Flash Configuration Register (FCNFG) The FCNFG register gates the security backdoor writes. KEYACC is readable and writable while all remaining bits read 0 and are not writable. KEYACC is only writable if KEYEN is set to the enabled state (see Section 4.4.2.2, “Flash Options Register (FOPT and NVOPT)”).
Page 107 Memory Table 4-11. FPROT Field Descriptions Field Description 7–1 Flash Protection Size. With FPOPEN set, the FPS bits determine the size of the protected flash address range as shown in Table 4-12. Flash Protection Open FPOPEN 0 Flash array fully protected. 1 Flash array protected address range determined by FPS bits.
Page 108 Memory Table 4-12. Flash Protection Address Range (continued) Protected Address Range Protected FPOPEN Relative to Flash Array Base Size 0x47 0x0_0000–0x1_BFFF 112 KB 0x5B 0x0_0000–0x1_1FFF 72 KB 0x5C 0x0_0000–0x1_17FF 70 KB 0x5D 0x0_0000–0x1_0FFF 68 KB 0x5E 0x0_0000–0x1_07FF 66 KB 0x5F 0x0_0000–0x0_FFFF 64 KB 0x60...
Page 109 Memory Table 4-13. FSTAT Field Descriptions Field Description Command Buffer Empty Flag. The FCBEF flag indicates that the command buffer is empty so that a new FCBEF command write sequence can be started when performing burst programming. Writing a 0 to the FCBEF flag has no effect on FCBEF.
Page 110 Memory Table 4-14. FCMD Field Descriptions Field Description Reserved, must be cleared. 6–0 Flash Command. Valid flash commands are shown below. Writing any command other than those listed sets FCMD the FACCERR flag in the FSTAT register. 0x05 Erase Verify 0x20 Program 0x25 Burst Program 0x40 Sector Erase...
Page 111 Memory N = number of cycles for SIM to release N = number of cycles for SIM to release secure state unknown / unpowered secure state unknown / unpowered internal reset. Adder of 16 imposed by the internal reset. Adder of 16 imposed by the ColdFire core.
Page 112 Memory N = number of cycles for SIM to release N = number of cycles for SIM to release secure state unknown / unpowered secure state unknown / unpowered internal reset. Adder of 16 imposed by the internal reset. Adder of 16 imposed by the ColdFire core.
Page 113 Chapter 5 Resets, Interrupts, and General System Control Introduction This section discusses basic reset and interrupt mechanisms and the various sources of reset and interrupt on an MCF51CN128 series microcontroller. Some interrupt sources from peripheral modules are discussed in greater detail within other sections of this document. This section gathers basic information about all reset and interrupt sources in one place for easy reference.
Page 114 Resets, Interrupts, and General System Control 5.3.1 Computer Operating Properly (COP) Watchdog The COP watchdog is intended to force a system reset when the application software fails to execute as expected. To prevent a system reset from the COP timer (when it is enabled), application software must reset the COP counter periodically.
Page 115 Resets, Interrupts, and General System Control The processor generates a reset in response to any of these events if CPUCR[IRD] is cleared. If this configuration bit is set, the processor generates the appropriate exception instead of forcing a reset. 5.3.3 Illegal Address Detect (ILAD) By default the V1 ColdFire core enables the generation of an MCU reset in response to any processor-detected address error, bus error termination, RTE format error or fault-on-fault condition.
Page 116 Resets, Interrupts, and General System Control interrupted. After the exception stack frame is stored in memory, the processor accesses the 32-bit pointer from the exception vector table using the vector number as the offset, and then jumps to that address to begin execution of the service routine.
Page 117 Resets, Interrupts, and General System Control The IRQ pin, when enabled, defaults to use an internal pull device (IRQPDD = 0), configured as a pull-up or pull-down depending on the polarity chosen. To use an external pull-up or pull-down, the IRQPDD can be set to turn off the internal device.
Page 118 Resets, Interrupts, and General System Control Table 5-1. MC51CN128 Exception and Interrupt Vector Table (continued) Vector Stacked Vector Address Program Vector Description Enable Source Name Offset Counter 0x118 Next TPM1_ovfl TPM1_SC[TOIE] TPM1_SC[TOF] Vtpm1ovf 0x11C Next MTIM1_ovfl MTIM1_TOIE MTIM1_TOF 0x120 Next TPM2_ch0 TPM2_C0SC[CH0IE] TPM2_C0SC[CH0F...
Page 119 Resets, Interrupts, and General System Control Table 5-1. MC51CN128 Exception and Interrupt Vector Table (continued) Vector Stacked Vector Address Program Vector Description Enable Source Name Offset Counter 0x14C Next SCI2_rx SCI2_C2[RIE] SCI2_S1[RDRF] Vsci2rx SCI2_C2[ILIE] SCI2_S1[IDLE] SCI2_BDH[LBKDIE] SCI2_S2[LBKDIF] SCI2_BDH[RXEDGIE] SCI2_S2[RXEDGIF 0x150 Next SCI2_tx SCI2_C2[TCIE]...
Page 120 Resets, Interrupts, and General System Control Table 5-1. MC51CN128 Exception and Interrupt Vector Table (continued) Vector Stacked Vector Address Program Vector Description Enable Source Name Offset Counter 0x198 Next SCI3_tx SCI3_C2[TCIE] SCI3_S1[TC] Vsci3tx SCI3_C2[TIE] SCI3_S1[TDRE] 0x19C Next Level 7 Software Interrupt Force_lvl7 0x1A0 Next...
Page 121 Resets, Interrupts, and General System Control The CPU configuration register (CPUCR) within the supervisor programming model allows you to determine if specific ColdFire exception conditions are to generate a normal exception or a system reset. The default state of the CPUCR forces a system reset for any of the exception types listed in Table 5-3.
Page 122 Resets, Interrupts, and General System Control Exception vector numbers not appearing in this table are not applicable to the V1 core and are reserved. The execution of the ILLEGAL instruction (0x4AFC) always generates an illegal instruction exception, regardless of the state of CPUCR[30]. Low-Voltage Detect (LVD) System The MCF51CN128 series microcontroller includes a system to protect against low voltage conditions to protect memory contents and control microcontroller system states during supply voltage variations.
Page 123 Resets, Interrupts, and General System Control Peripheral Clock Gating The MCF51CN128 series microcontroller includes a clock gating system to manage the bus clock sources to the individual peripherals. Using this system, you can enable or disable the bus clock to each of the peripherals at the clock source, eliminating unnecessary clocks to peripherals which are not in use;...
Page 124 Resets, Interrupts, and General System Control Table 5-4. IRQSC Register Field Descriptions Field Description Reserved, must be cleared. Interrupt Request (IRQ) Pull Device Disable — This read/write control bit disables the internal IRQPDD pull-up/pull-down device when the IRQ pin is enabled (IRQPE = 1) allowing for an external device to be used. 0 IRQ pull device is enabled if IRQPE = 1.
Page 125 Resets, Interrupts, and General System Control ILOP ILAD Writing any value to SRS address clears COP watchdog timer. POR: LVD: Any other reset: Any of these reset sources that are active at the time of reset entry causes the corresponding bit to set; bits corresponding to sources that are not active at the time of reset entry are cleared.
Page 126 Resets, Interrupts, and General System Control Table 5-5. SRS Register Field Descriptions (continued) Field Description Loss-of-Clock Reset — Reset was caused by a loss of external clock. MCGC3[CME] must be set for this func- tion to operate. 0 Reset not caused by a loss of external clock. 1 Reset caused by a loss of external clock.
Page 127 Resets, Interrupts, and General System Control Table 5-6. SOPT1 Field Descriptions (continued) Field Description COP Watchdog Clock Select — This write-once bit selects the clock source of the COP watchdog. COPCLKS 0 Internal 1 kHz clock is source to COP. 1 Bus clock is source to COP.
Page 128 Resets, Interrupts, and General System Control Table 5-8. SOPT2 Field Descriptions Field Description Reserved. must be cleared. RSVD 6–5 Flash Configuration — These bits specify the amount of flash memory available on this device. 00 64 KB Memory Map 01 Reserved 10 96 KB Memory Map 11 128 KB Memory Map 4–0...
Page 129 Resets, Interrupts, and General System Control Additional configuration information about the ColdFire core and memory system is loaded into the 32-bit D0 (core) and D1 (memory) registers at reset. This information can be stored into memory by the system startup code for later use by configuration-sensitive application code. See Section 7.3.3.14, “Reset Exception,”...
Page 130 Resets, Interrupts, and General System Control LVDF LVDIE LVDRE LVDSE LVDE BGBE LVDACK Reset: LVDF is set when V transitions below the trip point or after reset and V is already below V Supply Supply This bit can be written only one time after reset. Additional writes are ignored. Figure 5-8.
Page 131 Resets, Interrupts, and General System Control LPRS PPDF LPWUI PPDE PPDC PPDACK Reset: – Figure 5-9. System Power Management Status and Control 2 Register (SPMSC2) PPDE is a write-once bit that can be used to permanently disable the PPDC bit. Table 5-13.
Page 132 Resets, Interrupts, and General System Control LVWF LVDV LVWV LVWIE LVWACK POR: LVR: Any other reset: LVWF is set when V transitions below the trip point or after reset and V is already below V Supply Supply U = Unaffected by MCU Reset. Figure 5-10.
Page 133 Resets, Interrupts, and General System Control 5.7.10 System Clock Gating Control 1 Register (SCGC1) This register contains control bits to enable or disable the bus clock to three of the timers (MTIM2 is controlled by SCGC4), ADC, IICs and two of the three SCI modules on the chip. Gating off the clocks to unused peripherals reduces the microcontroller’s run and wait currents.
Page 134 Resets, Interrupts, and General System Control 5.7.11 System Clock Gating Control 2 Register (SCGC2) This register contains control bits to enable or disable the bus clock to the SCI3, FTSR, IRQ, keyboard, RTC, and SPI modules. Gating off the clocks to unused peripherals reduces the microcontroller’s run and wait currents.
Page 135 Resets, Interrupts, and General System Control 5.7.12 System Clock Gating Control 3 Register (SCGC3) This register contains control bits to enable or disable the bus clock to the PTA-H modules. Gating off the clocks to unused peripherals reduces the microcontroller’s run and wait currents. See Section 5.6, “Peripheral Clock Gating,”...
Page 136 Resets, Interrupts, and General System Control peripherals reduces the microcontroller’s run and wait currents. See Section 5.6, “Peripheral Clock Gating,” for more information. MTIM2 Reset: Figure 5-14. System Clock Gating Control 3 Register (SCGC4) 1 in 80-pin packages, 0 in 64-pin and 48-pin package. 1 in 80-pin and 64-pin packages, 0 in 48-pin package.
Page 137 Resets, Interrupts, and General System Control Table 5-20. SIMIPS Register Field Descriptions Field Description Reserved, must be cleared. TPM2 External Clock Select — This bit selects which external package pin supplies an external clock signal to TPM2 the TPM2 module. Note that the package pin must also be configured properly using the I/O mux controls discussed in Section 9.7, “Pin Mux Controls.”...
Page 138 Chapter 6 Multipurpose Clock Generator (MCG) Introduction The multipurpose clock generator (MCG) module provides several clock source choices for this device. The module contains a frequency-locked loop (FLL) and a phase-locked loop (PLL) that are controllable by either an internal or an external reference clock. The module can select either of the FLL or PLL clocks, or either of the internal or external reference clocks as a source for the MCU system clock.
Page 139 Multipurpose Clock Generator (MCG) 6.1.1 Features Key features of the MCG module are: • Frequency-locked loop (FLL) • Internal or external reference clock can be used to control the FLL • Phase-locked loop (PLL) — Voltage-controlled oscillator (VCO) — Modulo VCO frequency divider —...
Page 140 Multipurpose Clock Generator (MCG) External Reference Clock Crystal Oscillator (XOSC) (required) MCGERCLK ERCLKEN EREFS IRCLKEN EREFSTEN MCGIRCLK Clock CLKS BDIV Monitor RANGE MCGOUT n=0-3 DMX32 OSCINIT MCGPLLSCLK DCOH DIV32 DCOOUT Filter DCOM Lock Detector DCOL RDIV PLLS LOLS LOCK MCGFFCLK MCGLCLK n=0-7 IREFS...
Page 141 Multipurpose Clock Generator (MCG) 6.1.2 Modes of Operation There are several modes of operation for the MCG. For details, see Section 6.4.1, “MCG Modes of Operation.” External Signal Description There are no MCG signals that connect off chip. Register Definition 6.3.1 MCG Control Register 1 (MCGC1) CLKS...
Page 142 Multipurpose Clock Generator (MCG) Table 6-2. FLL External Reference Divide Factor Divide Factor RDIV RANGE:DIV32 RANGE:DIV32 RANGE:DIV32 1024 Reserved Table 6-3. PLL External Reference Divide Factor RDIV Divide Factor MCF51CN128 Reference Manual, Rev. 6 Freescale Semiconductor...
Page 143 Multipurpose Clock Generator (MCG) 6.3.2 MCG Control Register 2 (MCGC2) BDIV RANGE EREFS ERCLKEN EREFSTEN Reset: Figure 6-3. MCG Control Register 2 (MCGC2) Table 6-4. MCG Control Register 2 Field Descriptions Field Description Bus Frequency Divider — Selects the amount to divide down the clock source selected by the CLKS bits in the BDIV MCGC1 register.
Page 144 Multipurpose Clock Generator (MCG) 6.3.3 MCG Trim Register (MCGTRM) TRIM Figure 6-4. MCG Trim Register (MCGTRM) A value for TRIM is loaded during reset from a factory programmed location when not in any BDM mode. If in a BDM mode, a default value of 0x80 is loaded. Table 6-5.
Page 145 Multipurpose Clock Generator (MCG) 6.3.4 MCG Status and Control Register (MCGSC) LOLS LOCK PLLST IREFST CLKST OSCINIT FTRIM Reset: Figure 6-5. MCG Status and Control Register (MCGSC) A value for FTRIM is loaded during reset from a factory programmed location when not in any BDM mode. If in a BDM mode, a default value of 1’b0 is loaded.
Page 146 Multipurpose Clock Generator (MCG) Table 6-6. MCG Status and Control Register Field Descriptions (continued) Field Description OSC Initialization — If the external reference clock is selected by ERCLKEN or by the MCG being in FEE, FBE, OSCINIT PEE, PBE, or BLPE mode, and if EREFS is set, then this bit is set after the initialization cycles of the crystal oscillator clock have completed.
Page 147 Multipurpose Clock Generator (MCG) Table 6-7. MCG PLL Register Field Descriptions (continued) Field Description Divide-by-32 Enable — Controls an additional divide-by-32 factor to the external reference clock for the FLL DIV32 when RANGE bit is set. When the RANGE bit is 0, this bit has no effect. Writes to this bit are ignored if PLLS bit is set.
Page 148 Multipurpose Clock Generator (MCG) Table 6-8. MCG Test and Control Register Field Descriptions Field Description Reserved for test, user code should not write 1’s to these bits. DCO Maximum frequency with 32.768 kHz reference — The DMX32 bit controls whether or not the DCO DMX32 frequency range is narrowed to its maximum frequency with a 32.768 kHz reference.
Page 149 Multipurpose Clock Generator (MCG) Table 6-10. MCG Modes of Operation Mode Related field values Description FLL Engaged • MCGC1[IREFS] = 1 Default. MCGOUT is derived from the FLL clock, which is controlled by Internal (FEI) • MCGC1[CLKS] = 00 the internal reference clock. The FLL clock frequency locks to 1024 times •...
Page 150 Multipurpose Clock Generator (MCG) Table 6-10. MCG Modes of Operation (continued) Mode Related field values Description PLL Bypassed • MCGC1[IREFS] = 0 MCGOUT is derived from the external reference clock; the PLL is External (PBE) • MCGC1[CLKS] = 10 operational, but its output clock is not used. This mode is useful to allow •...
Page 151 Multipurpose Clock Generator (MCG) BLPE BLPI Returns to the state that was active before Entered from any state when the MCU entered Stop mode, unless a Stop the MCU enters Stop mode reset occurs while in Stop mode. Figure 6-8. MCG Mode State Diagram 6.4.3 Mode Switching The IREFS bit can be changed at anytime, but the actual switch to the newly selected clock is shown by...
Page 152 Multipurpose Clock Generator (MCG) 6.4.4 Bus Frequency Divider The BDIV bits can be changed at anytime and the actual switch to the new frequency occurs immediately. 6.4.5 Low Power Bit Usage The low power bit (LP) is provided to allow the FLL or PLL to be disabled and thus conserve power when these systems are not being used.
Page 153 Multipurpose Clock Generator (MCG) 6.4.8 Fixed Frequency Clock The MCG presents the divided reference clock as MCGFFCLK for use as an additional clock source. The MCGFFCLK frequency must be no more than 1/4 of the MCGOUT frequency to be valid. This clock is intended for use in systems that include a USB interface.
Page 154 Multipurpose Clock Generator (MCG) RDIV bits should also be set appropriately here according to the external reference frequency because although the FLL is bypassed, it remains on in FBE mode. — The internal reference can optionally be kept running by setting the IRCLKEN bit. This is useful if the application switches back and forth between internal and external modes.
Page 155 Multipurpose Clock Generator (MCG) To change from FEI clock mode to FBI clock mode, follow this procedure: 1. Change the CLKS bits in MCGC1 to %01 so that the internal reference clock is selected as the system clock source. 2. Wait for the CLKST bits in the MCGSC register to change to %01, indicating that the internal reference clock has been appropriately selected.
Page 156 Multipurpose Clock Generator (MCG) The RDIV and IREFS bits should always be set properly before changing the PLLS bit so that the FLL or PLL clock has an appropriate reference clock frequency to switch to. The table below shows MCGOUT frequency calculations using RDIV, BDIV, and VDIV settings for each clock mode.
Page 157 Multipurpose Clock Generator (MCG) b) Loop until OSCINIT (bit 1) in MCGSC is 1, indicating the crystal selected by the EREFS bit has been initialized. c) Because RANGE = 1, set DIV32 (bit 4) in MCGC3 to allow access to the proper RDIV bits while in an FLL external mode.
Page 158 Multipurpose Clock Generator (MCG) b) Now, With an RDIV of divide-by-8, a BDIV of divide-by-1, and a VDIV of multiply-by-32, MCGOUT = [(8 MHz / 8) * 32] / 1 = 32 MHz, and the bus frequency is MCGOUT / 2, or 16 MCF51CN128 Reference Manual, Rev.
Page 159 Multipurpose Clock Generator (MCG) START N FEI MODE MCGC3 = 0x58 MCGC2 = 0x36 BLPE MODE ? (LP=1) CHECK OSCINIT = 1 ? MCGC2 = 0x36 (LP = 0) MCGC3 = 0x11 (DIV32 = 1) MCGC1 = 0x98 CHECK PLLST = 1? CHECK IREFST = 0? CHECK...
Page 160 Multipurpose Clock Generator (MCG) 6.5.3.2 Example 2: Moving from PEE to BLPI Mode: Bus Frequency =16 kHz In this example, the MCG moves through the proper operational modes from PEE mode with an 8MHz crystal configured for an 16 MHz bus frequency (see previous example) to BLPI mode with a 16 kHz bus frequency.First, the code sequence is described.
Page 161 Multipurpose Clock Generator (MCG) 4. Lastly, FBI transitions into BLPI mode. a) MCGC2 = 0x08 (%00001000) – LP (bit 3) in MCGSC is 1 – RANGE, HGO, EREFS, ERCLKEN, and EREFSTEN bits are ignored when the IREFS bit (bit2) in MCGC is set. They can remain set, or be cleared at this point. MCF51CN128 Reference Manual, Rev.
Page 162 Multipurpose Clock Generator (MCG) START IN PEE MODE MCGC1 = 0x98 CHECK PLLST = 0? CHECK CLKST = %10 ? OPTIONAL: CHECK LOCK = 1? ENTER BLPE MODE ? MCGC1 = 0x5C MCGC2 = 0x3E (LP = 1) CHECK IREFST = 0? MCGC3 = 0x18 CHECK CLKST = %01?
Page 163 Multipurpose Clock Generator (MCG) 6.5.3.3 Example 3: Moving from BLPI to FEE Mode: External Crystal = 8 MHz, Bus Frequency = 16 MHz In this example, the MCG moves through the proper operational modes from BLPI mode at a 16 kHz bus frequency running off of the internal reference clock (see previous example) to FEE mode using an 8MHz crystal configured for a 16 MHz bus frequency.
Page 164 Multipurpose Clock Generator (MCG) START N BLPI MODE CHECK IREFST = 0? MCGC2 = 0x00 OPTIONAL: OPTIONAL: CHECK LOCK CHECK LOCK = 1? = 1? MCGC2 = 0x36 CHECK CLKST = %00? CHECK OSCINIT = 1 ? CONTINUE IN FEE MODE MCGC1 = 0x18 Figure 6-11.
Page 165 Multipurpose Clock Generator (MCG) approach to search for the best trim value is recommended. In example #4 later in this section, this approach is demonstrated. If a user specified trim value has been found for a device (to replace the factory trim value), this value can be stored in flash memory to save the value.
Page 166 Multipurpose Clock Generator (MCG) Initial conditions: 1) Clock supplied from ATE has 500 μsec duty period 2) MCG configured for internal reference with 8MHz bus START TRIM PROCEDURE TRMVAL = 0x100 MEASURE INCOMING CLOCK WIDTH (COUNT = # OF BUS CLOCKS / 8) COUNT <...
Page 167 Chapter 7 ColdFire Core Introduction ® This section describes the organization of the Version 1 (V1) ColdFire processor core and an overview of the program-visible registers. For detailed information on instructions, see the ISA_C definition in the ColdFire Family Programmer’s Reference Manual. 7.1.1 Overview As with all ColdFire cores, the V1 ColdFire core is comprised of two separate pipelines decoupled by an...
Page 168 ColdFire Core instruction, fetches the required operands, and then executes the required function. Because the IFP and OEP pipelines are decoupled by an instruction buffer serving as a FIFO queue, the IFP is able to prefetch instructions in advance of their actual use by the OEP thereby minimizing time stalled waiting for instructions.
Page 169 ColdFire Core • 16-bit status register (SR) • 32-bit supervisor stack pointer (SSP) • 32-bit vector base register (VBR) • 32-bit CPU configuration register (CPUCR) Table 7-1. ColdFire Core Programming Model Width Written with BDM Command Register Access Reset Value Section/Page (bits) MOVEC...
Page 170 ColdFire Core NOTE Registers D0 and D1 contain hardware configuration details after reset. See Section 7.3.3.14, “Reset Exception” for more details. BDM: Load: 0x60 + n; n = 0-7 (Dn) Access: User read/write BDM read/write Store: 0x40 + n; n = 0-7 (Dn) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Data Reset...
Page 171 ColdFire Core To support dual stack pointers, the following two supervisor instructions are included in the ColdFire instruction set architecture to load/store the USP: move.l Ay,USP;move to USP move.l USP,Ax;move from USP These instructions are described in the ColdFire Family Programmer’s Reference Manual. All other instruction references to the stack pointer, explicit or implicit, access the active A7 register.
Page 172 ColdFire Core Table 7-2. CCR Field Descriptions (continued) Field Description Negative condition code bit. Set if most significant bit of the result is set; otherwise cleared. Zero condition code bit. Set if result equals zero; otherwise cleared. Overflow condition code bit. Set if an arithmetic overflow occurs implying the result cannot be represented in operand size;...
Page 173 ColdFire Core BDM: 0x801 (VBR) Access: Supervisor read/write BDM read/write Load: 0xE1 (VBR) Store: 0xC1 (VBR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 R 0 0 0 0 0 0 0 0 –...
Page 174 ColdFire Core Table 7-3. CPUCR Field Descriptions (continued) Field Description Buffered write disable. The ColdFire core is capable of marking processor memory writes as bufferable or non-bufferable. 0 Writes are buffered and the bus cycle is terminated immediately with zero wait states. 1 Disable the buffering of writes.
Page 175 ColdFire Core Table 7-4. SR Field Descriptions (continued) Field Description Supervisor/user state. 0 User mode 1 Supervisor mode Master/interrupt state. Bit is cleared by an interrupt exception and software can set it during execution of the RTE or move to SR instructions. Reserved, must be cleared.
Page 176 ColdFire Core Table 7-5. Instruction Enhancements over Revision ISA_A Instruction Description BITREV The contents of the destination data register are bit-reversed; that is, new Dn[31] equals old Dn[0], new Dn[30] equals old Dn[1], ..., new Dn[0] equals old Dn[31]. BYTEREV The contents of the destination data register are byte-reversed;...
Page 177 ColdFire Core All ColdFire processors use an instruction restart exception model. Exception processing includes all actions from fault condition detection to the initiation of fetch for first handler instruction. Exception processing is comprised of four major steps: 1. The processor makes an internal copy of the SR and then enters supervisor mode by setting the S bit and disabling trace mode by clearing the T bit.
Page 178 ColdFire Core Table 7-6. Exception Vector Assignments (continued) Stacked Vector Vector Program Assignment Number(s) Offset (Hex) Counter 0x008 Fault Access error 0x00C Fault Address error 0x010 Fault Illegal instruction 5–7 0x014–0x01C — Reserved 0x020 Fault Privilege violation 0x024 Next Trace 0x028 Fault Unimplemented line-A opcode...
Page 179 ColdFire Core 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 → Format FS[3:2] Vector FS[1:0] Status Register + 0x4 Program Counter Figure 7-10. Exception Stack Frame Form The 16-bit format/vector word contains three unique fields: •...
Page 180 ColdFire Core 7.3.3 Processor Exceptions 7.3.3.1 Access Error Exception The default operation of the V1 ColdFire processor is the generation of an illegal address reset event if an access error (also known as a bus error) is detected. If CPUCR[ARD] is set, the reset is disabled and a processor exception is generated as detailed below.
Page 181 ColdFire Core 7.3.3.3 Illegal Instruction Exception The default operation of the V1 ColdFire processor is the generation of an illegal opcode reset event if an illegal instruction is detected. If CPUCR[IRD] is set, the reset is disabled and a processor exception is generated as detailed below.
Page 182 ColdFire Core In the original M68000 ISA definition, lines A and F were effectively reserved for user-defined operations (line A) and co-processor instructions (line F). Accordingly, there are two unique exception vectors associated with illegal opwords in these two lines. Any attempted execution of an illegal 16-bit opcode (except for line-A and line-F opcodes) generates an illegal instruction exception (vector 4).
Page 183 ColdFire Core If the processor is not in trace mode and executes a stop instruction where the immediate operand sets SR[T], hardware loads the SR and generates a trace exception. The PC in the exception stack frame points to the instruction after the stop, and the SR reflects the value loaded in step 2. Because ColdFire processors do not support any hardware stacking of multiple exceptions, it is the responsibility of the operating system to check for trace mode after processing other exception types.
Page 184 ColdFire Core The selection of the format value provides some limited debug support for porting code from M68000 applications. On M68000 family processors, the SR was located at the top of the stack. On those processors, bit 30 of the longword addressed by the system stack pointer is typically zero. Thus, if an RTE is attempted using this old format, it generates a format error on a ColdFire processor.
Page 185 ColdFire Core 7.3.3.14 Reset Exception Asserting the reset input signal (RESET) to the processor causes a reset exception. The reset exception has the highest priority of any exception; it provides for system initialization and recovery from catastrophic failure. Reset also aborts any processing in progress when the reset input is recognized. Processing cannot be recovered.
Page 186 ColdFire Core Table 7-10. D0 Hardware Configuration Info Field Description Field Description 31–24 Processor family. This field is fixed to a hex value of 0xCF indicating a ColdFire core is present. 23–20 ColdFire core version number. Defines the hardware microarchitecture version of ColdFire core. 0001 V1 ColdFire core (This is the value used for this device.) 0010 V2 ColdFire core 0011 V3 ColdFire core...
Page 187 ColdFire Core Information loaded into D1 defines the local memory hardware configuration as shown in the figure below. BDM: Load: 0x61 (D1) Access: User read-only BDM read-only Store: 0x41 (D1) FLASHSZ Reset ROMSZ SRAMSZ Reset The FLASHSZ size depends on memory size. The size shown is for 128 KB flash. Figure 7-13.
Page 188 ColdFire Core 7.3.4 Instruction Execution Timing This section presents processor instruction execution times in terms of processor-core clock cycles. The number of operand references for each instruction is enclosed in parentheses following the number of processor clock cycles. Each timing entry is presented as C(R/W) where: •...
Page 189 ColdFire Core 7.3.4.2 MOVE Instruction Execution Times Table 7-13 lists execution times for MOVE.{B,W} instructions; Table 7-14 lists timings for MOVE.L. NOTE For all tables in this section, the execution time of any instruction using the PC-relative effective addressing modes is the same for the comparable An-relative mode.
Page 190 ColdFire Core Table 7-14. MOVE Long Execution Times (continued) Destination Source (Ax) (Ax)+ -(Ax) (d16,Ax) (d8,Ax,Xi*SF) xxx.wl (d8,Ay,Xi*SF) 3(1/0) 3(1/1) 3(1/1) 3(1/1) — — — xxx.w 2(1/0) 2(1/1) 2(1/1) 2(1/1) — — — xxx.l 2(1/0) 2(1/1) 2(1/1) 2(1/1) — — —...
Page 191 ColdFire Core 7.3.4.4 Standard Two Operand Instruction Execution Times Table 7-16. Two Operand Instruction Execution Times Effective Address Opcode <EA> (d16,An) (d8,An,Xn*SF) (An) (An)+ -(An) xxx.wl #xxx (d16,PC) (d8,PC,Xn*SF) ADD.L <ea>,Rx 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0) ADD.L Dy,<ea>...
Page 192 ColdFire Core Table 7-16. Two Operand Instruction Execution Times (continued) Effective Address Opcode <EA> (d16,An) (d8,An,Xn*SF) (An) (An)+ -(An) xxx.wl #xxx (d16,PC) (d8,PC,Xn*SF) SUB.L <ea>,Rx 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0) SUB.L Dy,<ea> — 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) —...
Page 193 ColdFire Core Table 7-17. Miscellaneous Instruction Execution Times (continued) Effective Address Opcode <EA> (An) (An)+ -(An) (d16,An) (d8,An,Xn*SF) xxx.wl #xxx WDDATA <ea> — 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) — WDEBUG <ea> — 5(2/0) — — 5(2/0) — — — The n is the number of registers moved by the MOVEM opcode.
Page 194 Chapter 8 Interrupt Controller (CF1_INTC) Introduction The CF1_INTC interrupt controller (CF1_INTC) is intended for use in low-cost microcontroller designs using the Version 1 (V1) ColdFire processor core. In keeping with the general philosophy for devices based on this low-end 32-bit processor, the interrupt controller generally supports less programmability compared to similar modules in other ColdFire microcontrollers and embedded microprocessors.
Page 195 Interrupt Controller (CF1_INTC) Table 8-1. Exception Processing Comparison (continued) Attribute HCS08 V1 ColdFire Software IACK Exit Instruction from ISR 8.1.1 Overview Interrupt exception processing includes interrupt recognition, aborting the current instruction execution stream, storing an 8-byte exception stack frame in the memory, calculation of the appropriate vector, and passing control to the specified interrupt service routine.
Page 196 Interrupt Controller (CF1_INTC) type determines whether the program counter placed in the exception stack frame defines the location of the faulting instruction (fault) or the address of the next instruction to be executed (next). For interrupts, the stacked PC is always the address of the next instruction to be executed. 4.
Page 197 Interrupt Controller (CF1_INTC) Table 8-2. MC51CN128 Series Exception and Interrupt Vector Table (continued) Vector Stacked Vector Address Program Vector Description Enable Source Name Offset Counter 0x110 Next TPM1_ch1 TPM1_C1SC[CH1IE] TPM1_C1SC[CH1F Vtpm1ch1 0x114 Next TPM1_ch2 TPM1_C2SC[CH1IE] TPM1_C2SC[CH2F Vtpm1ch2 0x118 Next TPM1_ovfl TPM1_SC[TOIE] TPM1_SC[TOF] Vtpm1ovf...
Page 198 Interrupt Controller (CF1_INTC) Table 8-2. MC51CN128 Series Exception and Interrupt Vector Table (continued) Vector Stacked Vector Address Program Vector Description Enable Source Name Offset Counter 0x148 Next SCI2_err SCI2_C3[ORIE] SCI2_S1[OR] Vsci2err SCI2_C3[FEIE] SCI2_S1[FE] SCI2_C3[NEIE] SCI2_S1[NF] SCI2_C3[PEIE] SCI2_S1[PF] 0x14C Next SCI2_rx SCI2_C2[RIE] SCI2_S1[RDRF] Vsci2rx...
Page 199 Interrupt Controller (CF1_INTC) Table 8-2. MC51CN128 Series Exception and Interrupt Vector Table (continued) Vector Stacked Vector Address Program Vector Description Enable Source Name Offset Counter 0x194 Next SCI3_rx SCI3_C2[RIE] SCI3_S1[RDRF] Vsci3rx SCI3_C2[ILIE] SCI3_S1[IDLE] SCI3_BDH[LBKDIE] SCI3_S2[LBKDIF] SCI3_BDH[RXEDGIE] SCI3_S2[RXEDGIF 0x198 Next SCI3_tx SCI3_C2[TCIE] SCI3_S1[TC] Vsci3tx...
Page 200 Interrupt Controller (CF1_INTC) The basic ColdFire interrupt controller supports up to 63 request sources mapped as nine priorities for each of the seven supported levels (7 levels × 9 priorities per level). Within the nine priorities within a level, the mid-point is typically reserved for package-level IRQ inputs.
Page 201 Interrupt Controller (CF1_INTC) Interrupt Source Number data to module CF1_INTC address decode INTC_WCR INTC_FRC Enable Wakeup ≥ > ≥ Prioritization Vector Gen IACK Vector Mux Spurious Vector Level n Vector data from module Peripheral Bus Wakeup Interrupt Level & Vector to V1 ColdFire core Figure 8-1.
Page 202 Interrupt Controller (CF1_INTC) — Exactly matches HCS08 interrupt request priorities — Up to two requests can be remapped to the highest maskable level + priority • Unique vector number for each interrupt source — ColdFire vector number = 62 + HCS08 vector number —...
Page 203 Interrupt Controller (CF1_INTC) Table 8-4. CF1_INTC Memory Map Offset Width Section/ Register Name Register Description Access Reset Value Address (bits) Page 0x0C INTC_ORMR CF1_INTC OR Mask Register 0x0140 8.3.1/8-10 0x10 INTC_FRC CF1_INTC Force Interrupt Register 0x00 8.3.2/8-11 0x18 INTC_PL6P7 CF1_INTC Programmable Level 6, Priority 7 0x00 8.3.3/8-12 0x19...
Page 204 Interrupt Controller (CF1_INTC) Offset: CF1_INTC_BASE + 0x0C (INTC_ORMR) Access: Read/Write FECDO Reset SCI3DO Reset Figure 8-2. Interrupt OR Mask Register (INTC_ORMR) Table 8-5. INTC_ORMR Register Descriptions Field Description 15-9 Reserved, must be cleared. Disable (mask) FEC_Other interrupt request FECDO 0 FEC_Other interrupt request is enabled; all individual FEC interrupt requests except FEC_TXF and FEC_RXF are disabled 1 FEC_Other interrupt request is disabled;...
Page 205 Interrupt Controller (CF1_INTC) Offset: CF1_INTC_BASE + 0x10 (INTC_FRC) Access: Read/Write LVL1 LVL2 LVL3 LVL4 LVL5 LVL6 LVL7 Reset Figure 8-3. Force Interrupt Register (INTC_FRC) Table 8-6. INTC_FRC Field Descriptions Field Description Reserved, must be cleared. Force Level 1 interrupt. LVL1 0 Negates the forced level 1 interrupt request.
Page 206 Interrupt Controller (CF1_INTC) NOTE The requests associated with the INTC_FRC register have a fixed level and priority that cannot be altered. The INTC_PL6P7 register specifies the highest-priority, maskable interrupt request that is defined as the level six, priority seven request. The INTC_PL6P6 register specifies the second-highest-priority, maskable interrupt request defined as the level six, priority six request.
Page 207 Interrupt Controller (CF1_INTC) Typically, the interrupt mask level loaded into the processor's status register field (SR[I]) during the execution of the stop instruction matches the INTC_WCR[MASK] value. The interrupt controller's wait mode wakeup signal is defined as: wait wakeup = INTC_WCR[ENB] & (level of any asserted_int_request > INTC_WCR[MASK]) Offset: CF1_INTC_BASE + 0x1B (INTC_WCR) Access: Read/Write MASK...
Page 208 Interrupt Controller (CF1_INTC) Table 8-9. INTC_SFRC Field Descriptions Field Description 7–6 Reserved, must be cleared. 5–0 For data values within the 56–62 range, the corresponding bit in the INTC_FRC register is set, as defined below. 0x38 Bit 56, INTC_FRC[LVL7] is set 0x39 Bit 57, INTC_FRC[LVL6] is set 0x3A Bit 58, INTC_FRC[LVL5] is set 0x3B Bit 59, INTC_FRC[LVL4] is set...
Page 209 Interrupt Controller (CF1_INTC) 8.3.7 INTC Software and Level-n IACK Registers (n = 1,2,3,...,7) The eight read-only interrupt acknowledge (IACK) registers can be explicitly addressed by the memory-mapped accesses or implicitly addressed by a processor-generated interrupt acknowledge cycle during exception processing when CPUCR[IAE] is set. In either case, the interrupt controller's actions are similar.
Page 210 Interrupt Controller (CF1_INTC) Table 8-12. INTC_SWIACK, INTC_LVLnIACK Field Descriptions Field Description Reserved, must be cleared. 6–0 Vector number. Indicates the appropriate vector number. VECN For the SWIACK register, it is the highest-level, highest-priority request currently being asserted in the CF1_INTC module.
Page 211 Interrupt Controller (CF1_INTC) disables interrupts. The ColdFire architecture defines seven interrupt levels, controlled by the 3-bit interrupt priority mask field in the status register, SR[I], and the hardware automatically supports nesting of interrupts. To emulate the HCS08’s 1-level IRQ capabilities on V1 ColdFire, only two SR[I] settings are used: •...
Page 212 Interrupt Controller (CF1_INTC) The reset state of the INTC_PL6P{7,6} registers disables any request remapping. 8.6.3 More on Software IACKs As previously mentioned, the notion of a software IACK refers to the ability to query the interrupt controller near the end of an interrupt service routine (after the current interrupt request has been cleared) to determine if there are any pending (but currently masked) interrupt requests.
Page 213 Interrupt Controller (CF1_INTC) vector numbers. The result is the conditional branch (PC = 0x5C8) is taken if there are no pending requests or if the pending request is a level seven. If there is a pending non-level seven request, execution continues with a three instruction sequence to calculate and then branch to the appropriate alternate ISR entry point.
Page 214 Chapter 9 Parallel Input/Output Control Overview of MCF51CN128 I/O Functions 9.1.1 Summary This section explains software controls related to parallel input/output (I/O) and pin control. The MCF51CN128 series MCUs have up to nine parallel I/O ports which include a total of 70 I/O pins. See Chapter 2, “Pins and Connections,”...
Page 215 Parallel Input/Output Control Port D is assosiated with RGPIO[7:0]. Table 9-2 shows RGPIO pin mapping to the port I/O pins. Table 9-2. Port D Pin Mapping to RGPIO Port pin PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0 KBI1 pin RGPIO7 RGPIO6 RGPIO5...
Page 216 Parallel Input/Output Control • Low drive strength selected (PTxDS[n] = 0) • Internal pull-ups disabled (PTxPE[n] = 0) Two exceptions to this are the RESET and BKGD/MS pins, which have pull-ups enabled at reset. 9.1.5.2 Port J Port J has only 6 pins, versus the usual 8, associated with it. Always write the upper two bits their reset defaults described in the programming models sections.
Page 217 Parallel Input/Output Control Pin Controls This section shows the superset of pin control functions which may be present on V1 ColdFire devices. Some devices may not include all of these controls. See the summary table earlier in the chapter for specific capabilities for your device.
Page 218 Parallel Input/Output Control NOTE The full complement of pin controls may not be present on all Freescale devices. See the summary table earlier in the chapter to determine which of these are present on your device. Table 9-6. Register Set Summary Register Description Access...
Page 219 Parallel Input/Output Control 9.2.2.2 Port x Slew Rate Enable Register (PTxSE) Slew rate control can be enabled for each port pin by setting the corresponding bit in the slew rate control register (PTxSE[n]). When enabled, slew control limits the rate at which an output can transition in order to reduce EMC emissions.
Page 220 Parallel Input/Output Control 9.2.2.4 Port x Input Filter Enable Register (PTxIFE) The pad cells on this device incorporate optional low pass filters on the digital input functions. These are enabled by setting the appropriate bit in the input filter enable register (PTxIFE[n]). When set, a low pass filter (10MHz to 30MHz bandwidth) is enabled in the logic input path.
Page 221 Parallel Input/Output Control Read xDD Write xDD Port Output Enable PTxDD[n] Write xD Port Data Out PTxD[n] Read xD Port Data In Figure 9-6. GPIO Bit Block Diagram Pin mux controls leave GPIO input buffers enabled for all digital functions, regardless of mux control selection.
Page 222 Parallel Input/Output Control 9.3.2.1 Port x Data Register (PTxD) The data register of each port allows software to interact with the pins of the chip. Each bit of each data register controls one pin on the chip. When the port bit is configured as an input (PTxDD[n]=0), a read of the port returns the logic value of the external pin input for that bit location.
Page 223 Parallel Input/Output Control V1 ColdFire Rapid GPIO Functionality The V1 ColdFire core can perform higher speed I/O via its local bus, which does not have latency penalties associated with the on-chip peripheral bus bridge. The Rapid GPIO module contains separate set/clear/data registers based at address 0x(00)C0_0000.
Page 224 Parallel Input/Output Control 9.5.1.2 Edge and Level Sensitivity A valid edge or level on an enabled port pin sets the KBIxSC[KBF] bit. If KBIxSC[KBIE] is set, an interrupt request is generated to the CPU. Write a 1 to KBIxSC[KBACK] to clear KBF, provided all enabled port inputs are at their deasserted levels.
Page 225 Parallel Input/Output Control 9.5.2.1 KBIx Interrupt Status and Control Register (KBIxSC) KBIE KBIMOD KBACK Reset: Figure 9-10. KBIx Interrupt Status and Control Register (KBIxSC) Table 9-15. KBIxSC Field Descriptions Field Description 7–4 Reserved, must be cleared. KBIx Interrupt Flag — KBF indicates when a KBIx interrupt is detected. Writes have no effect on KBF. 0 No KBIx interrupt detected.
Page 226 Parallel Input/Output Control 9.5.2.3 KBIx Interrupt Edge Select Register (KBIxES) KBEDG7 KBEDG6 KBEDG5 KBEDG4 KBEDG3 KBEDG2 KBEDG1 KBEDG0 Reset: Figure 9-12. KBIx Edge Select Register (KBIxES) Table 9-17. KBIxES Field Descriptions Field Description 7–0 KBIx Edge Selects — Each of the KBEDGn bits serves a dual purpose by selecting the polarity of the active KBEDGn interrupt edge as well as selecting a pull-up or pull-down device if enabled.
Page 227 Chapter 10 Rapid GPIO (RGPIO) 10.1 Introduction The Rapid GPIO (RGPIO) module provides a 16-bit general-purpose I/O module directly connected to the processor’s high-speed 32-bit local bus. This connection plus support for single-cycle, zero wait-state data transfers allows the RGPIO module to provide improved pin performance when compared to more traditional GPIO modules located on the internal slave peripheral bus.
Page 228 Rapid GPIO (RGPIO) A simplified block diagram of the RGPIO module is shown in Figure 10-1. The details of the pin muxing and pad logic are device-specific. RGPIO module data to module address decode Control Pin Enables Direction Write D ata Read D ata rgpio_enable rgpio_direction...
Page 229 Rapid GPIO (RGPIO) – Register for reading current pin state – The two data registers (read, write) are mapped to a single program-visible location — Alternate addresses to perform data set, clear, and toggle functions using simple writes — Separate read and write programming model views enable simplified driver software –...
Page 230 Rapid GPIO (RGPIO) 10.3 Memory Map/Register Definition The RGPIO module provides a compact 16-byte programming model based at a system memory address of 0x(00)C0_0000 (noted as RGPIO_BASE throughout the chapter). As previously noted, the programming model views are different between reads and writes as this enables simplified software for manipulation of the RGPIO pins.
Page 231 Rapid GPIO (RGPIO) 10.3.1 RGPIO Data Direction (RGPIO_DIR) The read/write RGPIO_DIR register defines whether a properly-enabled RGPIO pin is configured as an input or output: • Setting any bit in RGPIO_DIR configures a properly-enabled RGPIO port pin as an output •...
Page 232 Rapid GPIO (RGPIO) Offset: RGPIO_Base + 0x2 (RGPIO_DATA) Access: Read/write Read/Indirect Write RGPIO_Base + 0x6 Read/Indirect Write RGPIO_Base + 0xA Read/Indirect Write RGPIO_Base + 0xE DATA Reset Figure 10-3. RGPIO Data Register (RGPIO_DATA) Table 10-6. RGPIO_DATA Field Descriptions Field Description 15–0 RGPIO data.
Page 233 Rapid GPIO (RGPIO) Setting it has no effect. The RGPIO_CLR register is write-only; reads of this address return the RGPIO_DATA register. Offset: RGPIO_Base + 0x6 (RGPIO_CLR) Access: Write-only Reset — — — — — — — — — — — —...
Page 234 Rapid GPIO (RGPIO) Offset: RGPIO_Base + 0xE (RGPIO_TOG) Access: Write-only Reset — — — — — — — — — — — — — — — — Figure 10-7. RGPIO Toggle Data Register (RGPIO_TOG) Table 10-10. RGPIO_TOG Field Descriptions Field Description 15–0 Toggle data.
Page 235 Rapid GPIO (RGPIO) 10.6.1 Application 1: Simple Square-Wave Generation In this example, several different instruction loops are executed, each generating a square-wave output with a 50% duty cycle. For this analysis, the executed code is mapped into the processor’s RAM. This configuration is selected to remove any jitter from the output square wave caused by the limitations defined by the two-cycle flash memory accesses and restrictions on the initiation of a flash access.
Page 236 Rapid GPIO (RGPIO) For this example, the processing of the SPI message is considerably more complex than the generation of a simple square wave of the previous example. The code snippet used to extract the data bit from the message and build the required GPIO data register writes is shown in Figure 10-9.
Page 237 Rapid GPIO (RGPIO) Table 10-12. Emulated SPI Performance using GPIO Outputs Peripheral Bus-mapped GPIO RGPIO SPI Speed @ Relative SPI Speed @ Relative CPU f = 50 MHz Speed CPU f = 50 MHz Speed 2.063 Mbps 1.00x 3.809 Mbps 1.29x MCF51CN128 Reference Manual, Rev.
Page 238 Chapter 11 Mini-FlexBus 11.1 Introduction This chapter describes external bus data transfer operations and error conditions. It describes transfers initiated by the ColdFire processor (or any other bus master) and includes detailed timing diagrams showing the interaction of signals in supported bus operations. The Mini-FlexBus is a subset of the FlexBus module found on other ColdFire microprocessors.
Page 239 Mini-FlexBus 11.1.2 Features Key Mini-FlexBus features include: • Two independent, user-programmable chip-select signals (FB_CS[1:0]) that can interface with external SRAM, PROM, EPROM, EEPROM, flash, and other peripherals • 8- and 16-bit port sizes with configuration for multiplexed or non-multiplexed address and data buses •...
Page 240 Mini-FlexBus In multiplexed mode, the FB_AD[ :0] bus carries the address and data. The full -bit address is driven on the first clock of a bus cycle (address phase). Following the first clock, the data is driven on the bus (data phase).
Page 241 Mini-FlexBus Table 11-2. Mini-FlexBus Chip Select Memory Map Width Section/ Offset Register Access Reset Value (bits) Page 0x00 Chip-Select Address Register (CSARn) 0x0000_0000 11.3.1/11-4 0x0C n = 0 – 1 0x04 Chip-Select Mask Register (CSMRn) 0x0000_0000 11.3.2/11-4 0x10 n = 0 – 1 0x08 Chip-Select Control Register (CSCRn) See Section...
Page 242 Mini-FlexBus Table 11-4. CSMRn Field Descriptions Field Description 31–16 Base address mask. Defines the chip-select block size by masking address bits. Setting a BAM bit causes the corresponding CSAR bit to be a don’t care in the decode. 0 Corresponding address bit is used in chip-select decode. 1 Corresponding address bit is a don’t care in chip-select decode.
Page 243 Mini-FlexBus Table 11-5. CSCRn Field Descriptions Field Description 31–22 Reserved, must be cleared 21–20 Address setup. This field controls the assertion of the chip-select with respect to assertion of a valid address and ASET attributes. The address and attributes are considered valid at the same time FB_ALE asserts. 00 Assert FB_CSn on first rising clock edge after address is asserted.
Page 244 Mini-FlexBus Table 11-5. CSCRn Field Descriptions (continued) Field Description 7–6 Port size. Specifies the data port width associated with each chip-select. It determines where data is driven during write cycles and where data is sampled during read cycles. 00 Reserved 01 8-bit port size.
Page 245 Mini-FlexBus connect its address lines to the appropriate FB_AD bits from FB_AD0 upward. Its data bus must be connected to FB_AD[7:0] in non-multiplexed mode (CSCR[MUX] = 0) or FB_AD0 to FB_ADn in multiplexed mode (CSCR[MUX] = 1) where n = 15 if CSCR[PS] = 1x or n = 7 if CSCR[PS] = 01. No bit ordering is required when connecting address and data lines to the FB_AD bus.
Page 246 Mini-FlexBus 11.4.4 Address/Data Bus Multiplexing The interface supports a single -bit wide multiplexed address and data bus (FB_AD[ :0]). The full -bit address is always driven on the first clock of a bus cycle. During the data phase, the FB_AD[ lines used for data are determined by the programmed port size for the corresponding chip select.
Page 247 Mini-FlexBus 11.4.5.1 Data Transfer Cycle States An on-chip state machine controls the data-transfer operation in the device. Figure 11-5 shows the state-transition diagram for basic read and write cycles. Next Cycle Wait States Figure 11-5. Data-Transfer-State-Transition Diagram Table 11-9 describes the states as they appear in subsequent timing diagrams. Table 11-9.
Page 248 Mini-FlexBus NOTE Throughout this chapter FB_AD[X:0] indicates a 16-, or 8-bit wide data bus. FB_AD[ 19:X+1 ] is an address bus that can be 12-, or 4 -bits in width. ColdFire device System 1. Set FB_R/W to read. 2. Place address on FB_AD[19:0]. 3.
Page 249 Mini-FlexBus FB_CLK FB_AD[19:X+1] ADDR[19:X+1] Mux’d Bus FB_AD[X:0] ADDR[X:0] DATA FB_A[19:0] ADDR[19:0] Non-Mux’d Bus FB_D[7:0] DATA FB_R/W FB_ALE FB_CSn, FB_OE Figure 11-7. Basic Read-Bus Cycle 11.4.6.2 Basic Write Bus Cycle During a write cycle, the device sends data to memory or to a peripheral device. Figure 11-8 shows the write cycle flowchart.
Page 250 Mini-FlexBus Figure 11-9 shows the write cycle timing diagram. FB_CLK FB_AD[19:X+1] ADDR[19:X+1] Mux’d Bus FB_AD[X:0] ADDR[X:0] DATA ADDR[19:0] FB_A[19:0] Non-Mux’d Bus FB_D[7:0] DATA FB_R/W FB_ALE FB_CSn FB_OE Figure 11-9. Basic Write-Bus Cycle 11.4.6.3 Bus Cycle Sizing This section shows timing diagrams for various port size scenarios. Figure 11-10 illustrates the basic byte read transfer to an 8-bit device with no wait states.
Page 251 Mini-FlexBus the first clock. The device tristates FB_AD[ 7:0] on the second clock and continues to drive address on FB_AD[ 19:8 ] throughout the bus cycle. The external device returns the read data on FB_AD[7:0]. FB_CLK FB_AD[19:8] ADDR[19:8] Mux’d Bus FB_AD[7:0] ADDR[7:0] DATA[7:0]...
Page 252 Mini-FlexBus Figure 11-12 illustrates the basic word read transfer to a 16-bit device with no wait states. The address is driven on the full FB_AD[19:0] bus in the first clock. The device tristates FB_AD[ 15:0] on the second clock and continues to drive the address on FB_AD[ 19:16 ] throughout the bus cycle.
Page 253 Mini-FlexBus FB_CLK FB_AD[19:16] ADDR[19:16] Mux’d Bus FB_AD[15:0] ADDR[15:0] DATA[15:0] FB_R/W FB_ALE FB_CSn FB_OE Figure 11-13. Single Word-Write Transfer 11.4.6.4 Timing Variations The Mini-FlexBus module has several features that can change the timing characteristics of a basic read- or write-bus cycle to provide additional address setup, address hold, and time for a device to provide or latch data.
Page 254 Mini-FlexBus Figure 11-14 Figure 11-15 show the basic read and write bus cycles (also shown in Figure 11-7 Figure 11-12) with the default of no wait states. FB_CLK FB_AD[19:X+1] ADDR[19:X+1] Mux’d Bus FB_AD[X:0] ADDR[X:0] DATA FB_A[19:0] ADDR[19:0] Non-Mux’d Bus FB_D[7:0] DATA FB_R/W FB_ALE...
Page 255 Mini-FlexBus If wait states are used, the S1 state repeats continuously until the the chip-select auto-acknowledge unit asserts internal transfer acknowledge. Figure 11-16 Figure 11-17 show a read and write cycle with one wait state. FB_CLK FB_AD[19:X+1] ADDR[19:X+1] Mux’d Bus FB_AD[X:0] ADDR[X:0] DATA...
Page 256 Mini-FlexBus 11.4.6.4.2 Address Setup and Hold The timing of the assertion and negation of the chip selects, byte selects, and output enable can be programmed on a chip-select basis. Each chip-select can be programmed to assert one to four clocks after address-latch enable (FB_ALE) is asserted.
Page 257 Mini-FlexBus In addition to address setup, a programmable address hold option for each chip select exists. Address and attributes can be held one to four clocks after chip-select, byte-selects, and output-enable negate. Figure 11-20 Figure 11-21 show read and write bus cycles with two clocks of address hold. FB_CLK FB_AD[19:8] ADDR[19:8]...
Page 258 Mini-FlexBus Figure 11-22 shows a bus cycle using address setup, wait states, and address hold. FB_CLK FB_AD[19:X+1] ADDR[19:X+1] Mux’d Bus FB_AD[X:0] ADDR[X:0] DATA FB_A[19:0] ADDR[19:0] Non-Mux’d Bus FB_D[7:0] DATA FB_R/W FB_ALE FB_CSn FB_OE Figure 11-22. Write Cycle with Two-Clock Address Setup and Two-Clock Hold (One Wait State) 11.4.7 Bus Errors...
Page 259 Chapter 12 Real-Time Counter (RTC) 12.1 Introduction The Real-Time Counter (RTC) module consists of one 8-bit counter, one 8-bit comparator, several binary-based and decimal-based prescaler dividers, two clock sources, and one programmable periodic interrupt. This module can be used for time-of-day, calendar or any task scheduling functions. It can also serve as a cyclic wakeup from low power modes without the need of external components.
Page 260 Real-Time Counter (RTC) 12.1.1 Features Features of the RTC module include: • 8-bit up-counter — 8-bit modulo match limit — Software controllable periodic interrupt on match • Three software selectable clock sources for input to prescaler with selectable binary-based and decimal-based divider values —...
Page 261 Real-Time Counter (RTC) 12.1.3 Block Diagram The block diagram for the RTC module is shown in Figure 12-1. Clock Source ERCLK Select IRCLK 8-Bit Modulo (RTCMOD) RTCLKS Background RTIF Interrupt Mode Request RTCPS 8-Bit Comparator RTCLKS[0] RTIE Write 1 to Prescaler 8-Bit Counter Clock...
Page 262 Real-Time Counter (RTC) 12.3.1 RTC Status and Control Register (RTCSC) RTCSC contains the real-time interrupt status flag (RTIF), the clock select bits (RTCLKS), the real-time interrupt enable bit (RTIE), and the prescaler select bits (RTCPS). RTIF RTCLKS RTIE RTCPS Reset: Figure 12-2.
Page 263 Real-Time Counter (RTC) 12.3.2 RTC Counter Register (RTCCNT) RTCCNT is the read-only value of the current RTC count of the 8-bit counter. RTCCNT Reset: Figure 12-3. RTC Counter Register (RTCCNT) Table 12-4. RTCCNT Field Descriptions Field Description RTC Count. These eight read-only bits contain the current value of the 8-bit counter. Writes have no effect to this RTCCNT register.
Page 264 Real-Time Counter (RTC) RTCPS and the RTCLKS[0] bit select the desired divide-by value. If a different value is written to RTCPS, the prescaler and RTCCNT counters are reset to 0x00. Table 12-6 shows different prescaler period values. Table 12-6. Prescaler Period 1-kHz Internal Clock 1-MHz External Clock 32-kHz Internal Clock...
Page 265 Real-Time Counter (RTC) Internal 1-kHz Clock Source RTC Clock (RTCPS = 0xA) RTCCNT 0x52 0x53 0x54 0x55 0x00 0x01 RTIF RTCMOD 0x55 Figure 12-5. RTC Counter Overflow Example In the example of Figure 12-5, the selected clock source is the 1-kHz internal oscillator clock source. The prescaler (RTCPS) is set to 0xA or divide-by-4.
Page 266 Real-Time Counter (RTC) RTCSC.byte = RTCSC.byte | 0x80; /* RTC interrupts every 1 Second */ Seconds++; /* 60 seconds in a minute */ if (Seconds > 59){ Minutes++; Seconds = 0; /* 60 minutes in an hour */ if (Minutes > 59){ Hours++;...
Page 267 Chapter 13 Serial Communication Interface (SCI) 13.1 Introduction The SCI allows asynchronous serial communications with peripheral devices and other CPUs. NOTE • MCF51CN128 series devices do not include stop1 low-power mode. Ignore references to stop1 in this chapter. • For details on low-power mode operation, refer to Table 3-5 Chapter 3, “Modes of Operation”.
Page 268 Serial Communication Interface (SCI) ipi_int_sci_err ipp_ind_sci_rx RECEIVER SBR12-SBR0 ipi_int_sci_rx BAUDRATE MODULE SINGLE WIRE/ GENERATOR ipp_ind_sci_tx CLOCK LOOP CONTROL ipp_do_sci_tx ÷ TRANSMITTER ipi_int_sci_tx Figure 13-1. SCI Module Block Diagram MCF51CN128 Reference Manual, Rev. 6 13-2 Freescale Semiconductor...
Page 269 Serial Communication Interface (SCI) 13.1.2 Features Features of SCI module include: • Full-duplex, standard non-return-to-zero (NRZ) format • Double-buffered transmitter and receiver with separate enables • Programmable baud rates (13-bit modulo divider) • Interrupt-driven or polled operation: — Transmit data register empty and transmission complete —...
Page 270 Serial Communication Interface (SCI) 13.1.4 Block Diagram Figure 13-2 shows the transmitter portion of the SCI. Internal Bus (Write-Only) LOOPS SCID – Tx Buffer RSRC Loop To Receive 11-BIT Transmit Shift Register Control Data In To TxD Pin 1 × Baud Rate Clock SHIFT DIRECTION TXINV...
Page 271 Serial Communication Interface (SCI) Figure 13-3 shows the receiver portion of the SCI. Internal Bus (Read-only) 16 × Baud Divide SCID – Rx Buffer Rate Clock By 16 From Transmitter 11-Bit Receive Shift Register LOOPS Single-Wire Loop Control RSRC LBKDE From RxD Pin RXINV Data Recovery...
Page 272 Serial Communication Interface (SCI) 13.2 Register Definition The SCI has eight 8-bit registers to control baud rate, select SCI options, report SCI status, and for transmit/receive data. Refer to the direct-page register summary in Chapter 4, “Memory,” or the absolute address assignments for all SCI registers.
Page 273 Serial Communication Interface (SCI) Table 13-2. SCIxBDL Field Descriptions Field Description 7–0 Baud Rate Modulo Divisor. These 13 bits in SBR[12:0] are referred to collectively as BR, and they set the modulo SBR[7:0] divide rate for the SCI baud rate generator. When BR is cleared, the SCI baud rate generator is disabled to reduce supply current.
Page 274 Serial Communication Interface (SCI) Table 13-3. SCIxC1 Field Descriptions (continued) Field Description Parity Enable. Enables hardware parity generation and checking. When parity is enabled, the most significant bit (msb) of the data character (eighth or ninth data bit) is treated as the parity bit. 0 No hardware parity generation or checking.
Page 275 Serial Communication Interface (SCI) Table 13-4. SCIxC2 Field Descriptions (continued) Field Description Transmitter Enable 0 Transmitter off. 1 Transmitter on. TE must be 1 to use the SCI transmitter. When TE is set, the SCI forces the TxD pin to act as an output for the SCI system.
Page 276 Serial Communication Interface (SCI) Table 13-5. SCIxS1 Field Descriptions Field Description Transmit Data Register Empty Flag. TDRE is set out of reset and when a transmit data value transfers from the TDRE transmit data buffer to the transmit shifter, leaving room for a new character in the buffer. To clear TDRE, read SCIxS1 with TDRE set and then write to the SCI data register (SCIxD).
Page 277 Serial Communication Interface (SCI) Table 13-5. SCIxS1 Field Descriptions (continued) Field Description Framing Error Flag. FE is set at the same time as RDRF when the receiver detects a logic 0 where the stop bit was expected. This suggests the receiver was not properly aligned to a character frame. To clear FE, read SCIxS1 with FE set and then read the SCI data register (SCIxD).
Page 278 Serial Communication Interface (SCI) Table 13-6. SCIxS2 Field Descriptions (continued) Field Description LIN Break Detection Enable. LBKDE selects a longer break character detection length. While LBKDE is set, LBKDE framing error (FE) and receive data register full (RDRF) flags are prevented from setting. 0 Break character is detected at length of 10 bit times (11 if M = 1).
Page 279 Serial Communication Interface (SCI) Table 13-7. SCIxC3 Field Descriptions (continued) Field Description Transmit Data Inversion. Setting this bit reverses the polarity of the transmitted data output. TXINV 0 Transmit data not inverted 1 Transmit data inverted Overrun Interrupt Enable. This bit enables the overrun flag (OR) to generate hardware interrupt requests. ORIE 0 OR interrupts disabled (use polling).
Page 280 Serial Communication Interface (SCI) Modulo Divide By (1 through 8191) Divide By Tx Baud Rate SCI Module Clock SBR[12:0] Rx Sampling Clock Baud Rate Generator (16 × Baud Rate) Off If [SBR12:SBR0] = 0 SCI Module Clock Baud Rate = SBR[12:0] ×...
Page 281 Serial Communication Interface (SCI) Writing 0 to TE does not immediately release the pin to be a general-purpose I/O pin. Any transmit activity in progress must first be completed. This includes data characters in progress, queued idle characters, and queued break characters. 13.3.2.1 Send Break and Queued Idle The SBK control bit in SCIxC2 sends break characters originally used to gain the attention of old teletype...
Page 282 Serial Communication Interface (SCI) status flag is set. If RDRF was already set indicating the receive data register (buffer) was already full, the overrun (OR) status flag is set and the new data is lost. Because the SCI receiver is double-buffered, the program has one full character time after RDRF is set before the data in the receive data buffer must be read to avoid a receiver overrun.
Page 283 Serial Communication Interface (SCI) the end of a message, or at the beginning of the next message, all receivers automatically force RWU to 0 so all receivers wake up in time to look at the first character(s) of the next message. 13.3.3.2.1 Idle-Line Wakeup When wake is cleared, the receiver is configured for idle-line wakeup.
Page 284 Serial Communication Interface (SCI) interrupts, software polling may be used to monitor the TDRE and TC status flags if the corresponding TIE or TCIE local interrupt masks are cleared. When a program detects that the receive data register is full (RDRF = 1), it gets the data from the receive data register by reading SCIxD.
Page 285 Serial Communication Interface (SCI) 13.3.5.2 Stop Mode Operation During all stop modes, clocks to the SCI module are halted. In stop1 and stop2 modes, all SCI register data is lost and must be re-initialized upon recovery from these two stop modes. No SCI module registers are affected in stop3 mode. The receive input active edge detect circuit remains active in stop3 mode, but not in stop2.
Page 286 Chapter 14 Serial Peripheral Interface (SPI) 14.1 Introduction The serial peripheral interface (SPI) module provides for full-duplex, synchronous, serial communication between the MCU and peripheral devices. These peripheral devices can include other microcontrollers, analog-to-digital converters, shift registers, sensors, memories, etc. The SPI runs at a baud rate up to the bus clock divided by two in master mode and up to the bus clock divided by 4 in slave mode.
Page 287 Serial Peripheral Interface (SPI) 14.1.1 Features Features of the SPI module include: • Master or slave mode operation • Full-duplex or single-wire bidirectional option • Programmable transmit bit rate • Double-buffered transmit and receive • Serial clock phase and polarity options •...
Page 288 Serial Peripheral Interface (SPI) The most common uses of the SPI system include connecting simple shift registers for adding input or output ports or connecting small peripheral devices such as serial A/D or D/A converters. Although Figure 14-1 shows a system where data is exchanged between two MCUs, many practical systems involve simpler connections where data is unidirectionally transferred from the master MCU to a slave or from a slave to the master MCU.
Page 289 Serial Peripheral Interface (SPI) Pin Control MOSI (MOMI) Tx Buffer (Write SPIxD) Enable MISO SPI System (SISO) Shift Shift SPI Shift Register SPC0 Rx Buffer (Read SPIxD) BIDIROE Shift Shift Rx Buffer Tx Buffer LSBFE Direction Clock Full Empty Master Clock Bus Rate SPIBR Clock...
Page 290 Serial Peripheral Interface (SPI) Prescaler Clock Rate Divider Master Divide By Divide By Bus Clock 1, 2, 3, 4, 5, 6, 7, or 8 2, 4, 8, 16, 32, 64, 128, or 256 Bit Rate SPPR[2:0] SPR[2:0] Figure 14-3. SPI Baud Rate Generation 14.2 External Signal Description The SPI optionally shares four port pins.
Page 291 Serial Peripheral Interface (SPI) 14.3 Modes of Operation 14.3.1 SPI in Stop Modes The SPI is disabled in all stop modes, regardless of the settings before executing the STOP instruction. During either stop1 or stop2 mode, the SPI module is fully powered down. Upon wake-up from stop1 or stop2 mode, the SPI module is in the reset state.
Page 292 Serial Peripheral Interface (SPI) Table 14-1. SPIxC1 Field Descriptions (continued) Field Description Master/Slave Mode Select MSTR 0 SPI module configured as a slave SPI device 1 SPI module configured as a master SPI device Clock Polarity — This bit effectively places an inverter in series with the clock signal from a master SPI or to a CPOL slave SPI device.
Page 293 Serial Peripheral Interface (SPI) Table 14-3. SPIxC2 Register Field Descriptions Field Description Master Mode-Fault Function Enable — When the SPI is configured for slave mode, this bit has no meaning or MODFEN effect. (The SS pin is the slave select input.) In master mode, this bit determines how the SS pin is used (refer to Table 14-2 for more details).
Page 294 Serial Peripheral Interface (SPI) Table 14-5. SPI Baud Rate Prescaler Divisor SPPR2:SPPR1:SPPR0 Prescaler Divisor 0:0:0 0:0:1 0:1:0 0:1:1 1:0:0 1:0:1 1:1:0 1:1:1 Table 14-6. SPI Baud Rate Divisor SPR2:SPR1:SPR0 Rate Divisor 0:0:0 0:0:1 0:1:0 0:1:1 1:0:0 1:0:1 1:1:0 1:1:1 14.4.4 SPI Status Register (SPIxS) This register has three read-only status bits.
Page 295 Serial Peripheral Interface (SPI) Table 14-7. SPIxS Register Field Descriptions Field Description SPI Read Buffer Full Flag — SPRF is set at the completion of an SPI transfer to indicate that received data may SPRF be read from the SPI data register (SPIxD). SPRF is cleared by reading SPRF while it is set, then reading the SPI data register.
Page 296 Serial Peripheral Interface (SPI) 14.5 Functional Description An SPI transfer is initiated by checking for the SPI transmit buffer empty flag (SPTEF = 1) and then writing a byte of data to the SPI data register (SPIxD) in the master SPI device. When the SPI shift register is available, this byte of data is moved from the transmit data buffer to the shifter, SPTEF is set to indicate there is room in the buffer to queue another transmit character if desired, and the SPI serial transfer starts.
Page 297 Serial Peripheral Interface (SPI) MOSI output pin from a master and the MISO waveform applies to the MISO output from a slave. The SS OUT waveform applies to the slave select output from a master (provided MODFEN and SSOE = 1). The master SS output goes to active low one-half SPSCK cycle before the start of the transfer and goes back high at the end of the eighth bit time of the transfer.
Page 298 Serial Peripheral Interface (SPI) setting in LSBFE. Both variations of SPSCK polarity are shown, but only one of these waveforms applies for a specific transfer, depending on the value in CPOL. The Sample In waveform applies to the MOSI input of a slave or the MISO input of a master. The MOSI waveform applies to the MOSI output pin from a master and the MISO waveform applies to the MISO output from a slave.
Page 299 Serial Peripheral Interface (SPI) fault flag (MODF). The SPI transmit interrupt enable mask (SPTIE) enables interrupts from the SPI transmit buffer empty flag (SPTEF). When one of the flag bits is set, and the associated interrupt mask bit is set, a hardware interrupt request is sent to the CPU. If the interrupt mask bits are cleared, software can poll the associated flag bits instead of using interrupts.
Page 300 Chapter 15 Analog-to-Digital Converter (ADC12) 15.1 Introduction The 12-bit analog-to-digital converter (ADC) is a successive approximation ADC designed for operation within an integrated microcontroller system-on-chip. NOTE • MCF51CN128 series devices do not include stop1 mode and pin control registers. Ignore references to stop1 and pin control registers. For details on low-power mode operation, refer to Table 3-5 Chapter 3, “Modes...
Page 301 Analog-to-Digital Converter (ADC12) Table 15-1. ADC Channel Assignment ADCH Channel Input ADCH Channel Input 00000 PTE2/KBI2P2/SS2/ADP0 10000 AD16 Reserved 00001 PTE1/KBI2P1/MOSI2/ADP1 10001 AD17 Reserved 00010 PTE0/KBI2P0/MISO2/ADP2 10010 AD18 Reserved 00011 PTD7RGPIO7/SPSCK2/ADP3 10011 AD19 Reserved 00100 PTD3RGPIO3/RXD2/ADP4 10100 AD20 Reserved 00101 PTD2/RGPIO2/TXD2/ADP5 10101 AD21...
Page 302 Analog-to-Digital Converter (ADC12) 15.1.2.3 Hardware Trigger The RTC on this device can be enabled as a hardware trigger for the ADC module by setting the ADCSC2[ADTRG] bit. When enabled, the ADC is triggered every time RTCCNT matches RTCMOD. The RTC interrupt does not have to be enabled to trigger the ADC. The RTI can be configured to cause a hardware trigger in MCU run, wait, and stop3.
Page 303 Analog-to-Digital Converter (ADC12) 15.1.3 Features Features of the ADC module include: • Linear successive approximation algorithm with 12-bit resolution • Up to 28 analog inputs • Output formatted in 12-, 10-, or 8-bit right-justified unsigned format • Single or continuous conversion (automatic return to idle after single conversion) •...
Page 304 Analog-to-Digital Converter (ADC12) Compare true ADCSC1 ADCCFG Async Clock Gen ADACK Bus Clock MCU STOP ADCK Clock Control Sequencer Divide ADHWT ÷2 ALTCLK AIEN Interrupt COCO ADVIN SAR Converter AD27 REFH Data Registers REFL Compare true Compare Logic ADCSC2 Compare Value Registers Figure 15-1.
Page 305 Analog-to-Digital Converter (ADC12) 15.2.1 Analog Power (V DDAD The ADC analog portion uses V as its power connection. In some packages, V is connected DDAD DDAD internally to V . If externally available, connect the V pin to the same voltage potential as V DDAD External filtering may be necessary to ensure clean V for good results.
Page 306 Analog-to-Digital Converter (ADC12) COCO AIEN ADCO ADCH Reset: Figure 15-2. Status and Control Register (ADCSC1) Table 15-3. ADCSC1 Field Descriptions Field Description Conversion Complete Flag. The COCO flag is a read-only bit set each time a conversion is completed when the COCO compare function is disabled (ACFE = 0).
Page 307 Analog-to-Digital Converter (ADC12) 15.3.2 Status and Control Register 2 (ADCSC2) The ADCSC2 register controls the compare function, conversion trigger, and conversion active of the ADC module. ADACT ADTRG ACFE ACFGT Reset: Figure 15-3. Status and Control Register 2 (ADCSC2) Bits 1 and 0 are reserved bits that must always be written to 0. Table 15-5.
Page 308 Analog-to-Digital Converter (ADC12) If the MODE bits are changed, any data in ADCRH becomes invalid. ADR11 ADR10 ADR9 ADR8 Reset: Figure 15-4. Data Result High Register (ADCRH) 15.3.4 Data Result Low Register (ADCRL) ADCRL contains the lower eight bits of the result of a 12-bit or 10-bit conversion, and all eight bits of an 8-bit conversion.
Page 309 Analog-to-Digital Converter (ADC12) In 10-bit mode, the ADCCVH register holds the upper two bits of the 10-bit compare value (ADCV9 – ADCV8). These bits are compared to the upper two bits of the result following a conversion in 10-bit mode when the compare function is enabled.
Page 310 Analog-to-Digital Converter (ADC12) Table 15-6. ADCCFG Register Field Descriptions (continued) Field Description Conversion Mode Selection. MODE bits are used to select between 12-, 10-, or 8-bit operation. See Table 15-8. MODE Input Clock Select. ADICLK bits select the input clock source to generate the internal clock ADCK. See ADICLK Table 15-9.
Page 311 Analog-to-Digital Converter (ADC12) When the conversion is completed, the result is placed in the data registers (ADCRH and ADCRL). In 10-bit mode, the result is rounded to 10 bits and placed in the data registers (ADCRH and ADCRL). In 8-bit mode, the result is rounded to 8 bits and placed in ADCRL. The conversion complete flag (COCO) is then set and an interrupt is generated if the conversion complete interrupt has been enabled (AIEN = 1).
Page 312 Analog-to-Digital Converter (ADC12) is observed. The hardware trigger function operates in conjunction with any of the conversion modes and configurations. 15.4.4 Conversion Control Conversions can be performed in 12-bit mode, 10-bit mode, or 8-bit mode as determined by the MODE bits.
Page 313 Analog-to-Digital Converter (ADC12) • A write to ADCSC2, ADCCFG, ADCCVH, or ADCCVL occurs. This indicates a mode of operation change has occurred and the current conversion is therefore invalid. • The MCU is reset. • The MCU enters stop mode with ADACK not enabled. When a conversion is aborted, the contents of the data registers, ADCRH and ADCRL, are not altered.
Page 314 Analog-to-Digital Converter (ADC12) Table 15-10. Total Conversion Time vs. Control Conditions Conversion Type ADICLK ADLSMP Max Total Conversion Time Subsequent continuous 10-bit or 12-bit; 20 ADCK cycles > f ADCK Subsequent continuous 8-bit; 37 ADCK cycles > f ADCK Subsequent continuous 10-bit or 12-bit; 40 ADCK cycles >...
Page 315 Analog-to-Digital Converter (ADC12) completion. Conversions can be initiated while the MCU is in wait mode by means of the hardware trigger or if continuous conversions are enabled. The bus clock, bus clock divided by two, and ADACK are available as conversion clock sources while in wait mode.
Page 316 Analog-to-Digital Converter (ADC12) 15.4.8 MCU Stop2 Mode Operation The ADC module is automatically disabled when the MCU enters stop2 mode. All module registers contain their reset values following exit from stop2. Therefore, the module must be re-enabled and re-configured following exit from stop2. 15.5 Initialization Information This section gives an example that provides some basic direction on how to initialize and configure the...
Page 317 Analog-to-Digital Converter (ADC12) Bit 6 ADTRG Software trigger selected Bit 5 ACFE Compare function disabled Bit 4 ACFGT Not used in this example Bit 3:2 Reserved, always reads zero Bit 1:0 Reserved for Freescale’s internal use; always write zero ADCSC1 = 0x41 (%01000001) Bit 7 COCO Read-only flag set when a conversion completes...
Page 318 Analog-to-Digital Converter (ADC12) 15.6 Application Information This section contains information for using the ADC module in applications. The ADC has been designed to be integrated into a microcontroller for use in embedded control applications requiring an A/D converter. 15.6.1 External Pins and Routing The following sections discuss the external pins associated with the ADC module and how they should be used for best results.
Page 319 Analog-to-Digital Converter (ADC12) 15.6.1.3 Analog Input Pins The external analog inputs are typically shared with digital I/O pins on MCU devices. The pin I/O control is disabled by setting the appropriate control bit in one of the pin control registers. Conversions can be performed on inputs without the associated pin control register bit set.
Page 320 Analog-to-Digital Converter (ADC12) 15.6.2.3 Noise-Induced Errors System noise that occurs during the sample or conversion process can affect the accuracy of the conversion. The ADC accuracy numbers are guaranteed as specified only if the following conditions are met: There is a 0.1 μF low-ESR capacitor from V •...
Page 321 Analog-to-Digital Converter (ADC12) For 12-bit conversions the code transitions only after the full code width is present, so the quantization error is −1 lsb to 0 lsb and the code width of each step is 1 lsb. 15.6.2.5 Linearity Errors The ADC may also exhibit non-linearity of several forms.
Page 322 Chapter 16 Fast Ethernet Controller (FEC) 16.1 Introduction This chapter provides a feature-set overview, a functional block diagram, and transceiver connection information for the 10 and 100 Mbps MII (media independent interface), as well as the 7-wire serial interface. Additionally, detailed descriptions of operation and the programming model are included. NOTE •...
Page 323 Fast Ethernet Controller (FEC) 16.1.2 Block Diagram Figure 16-1 shows the block diagram of the FEC. The FEC is implemented with a combination of hardware and microcode. The off-chip (Ethernet) interfaces are compliant with industry and IEEE 802.3 standards. Internal Bus Crossbar Switch Master Bus Internal Bus...
Page 324 Fast Ethernet Controller (FEC) You control the FEC by writing into control registers located in each block. The CSR (control and status registers) block provides global control (Ethernet reset and enable) and interrupt managing registers. The MII block provides a serial channel for control/status communication with the external physical layer device (transceiver).
Page 325 Fast Ethernet Controller (FEC) 16.2.1 Full and Half Duplex Operation Full duplex mode is for use on point-to-point links between switches or end node to switch. Half duplex mode works in connections between an end node and a repeater or between repeaters. TCR[FDEN] controls duplex mode selection.
Page 326 Fast Ethernet Controller (FEC) Table 16-1. FEC Signal Descriptions Signal Name Description FEC_COL Asserted upon detection of a collision and remains asserted while the collision persists. This signal is not defined for full-duplex mode. FEC_CRS — When asserted, indicates that transmit or receive medium is not idle. FEC_MDC —...
Page 327 Fast Ethernet Controller (FEC) Table 16-2 shows the FEC register memory map. Table 16-2. FEC Register Memory Map Width Offset Register Access Reset Value Section/Page (bits) 0x004 Interrupt Event Register (EIR) 0x0000_0000 16.4.1/16-6 0x008 Interrupt Mask Register (EIMR) 0x0000_0000 16.4.2/16-8 0x010 Receive Descriptor Active Register (RDAR) 0x0000_0000...
Page 328 Fast Ethernet Controller (FEC) Offset: 0x004 Access: User read/write BABR BABT GRA W w1c Reset Reset Figure 16-2. Ethernet Interrupt Event Register (EIR) Table 16-3. EIR Field Descriptions Field Description Heartbeat error. Indicates TCR[HBC] is set and that the COL input was not asserted within the heartbeat window HBERR following a transmission.
Page 329 Fast Ethernet Controller (FEC) Table 16-3. EIR Field Descriptions (continued) Field Description Collision retry limit. Indicates a collision occurred on each of 16 successive attempts to transmit the frame. The frame is discarded without being transmitted and transmission of the next frame commences. This error can only occur in half duplex mode.
Page 330 Fast Ethernet Controller (FEC) ECR[ETHER_EN] is also set). After the FEC polls a receive descriptor whose empty bit is not set, FEC clears the RDAR bit and ceases receive descriptor ring polling until the user sets the bit again, signifying that additional descriptors are placed into the receive descriptor ring.
Page 331 Fast Ethernet Controller (FEC) Table 16-6. TDAR Field Descriptions (continued) Field Description Set to 1 when this register is written, regardless of the value written. Cleared by the FEC device when no additional TDAR ready descriptors remain in the transmit ring. Also cleared when ECR[ETHER_EN] is cleared. 23–0 Reserved, must be cleared.
Page 332 Fast Ethernet Controller (FEC) Offset: 0x040 Access: User read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 DATA Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Figure 16-7.
Page 333 Fast Ethernet Controller (FEC) the original value written except for the DATA field whose contents are replaced by the value read from the PHY register. If the MMFR register is written while frame generation is in progress, the frame contents are altered. Software must use the MII interrupt to avoid writing to the MMFR register while frame generation is in progress.
Page 334 Fast Ethernet Controller (FEC) Table 16-10. Programming Examples for MSCR Internal FEC Clock MSCR[MII_SPEED] FEC_MDC frequency Frequency 25 MHz 2.50 MHz 33 MHz 2.36 MHz 40 MHz 2.50 MHz 50 MHz 2.50 MHz 66 MHz 2.36 MHz 16.4.8 Receive Control Register (RCR) RCR controls the operational mode of the receive block and must be written only when ECR[ETHER_EN] is cleared (initialization time).
Page 335 Fast Ethernet Controller (FEC) Table 16-11. RCR Field Descriptions (continued) Field Description Media independent interface mode. Selects the external interface mode for transmit and receive blocks. MII_MODE 0 7-wire mode (used only for serial 10 Mbps) 1 MII mode Disable receive on transmit. 0 Receive path operates independently of transmit (use for full duplex or to monitor transmit activity in half duplex mode).
Page 336 Fast Ethernet Controller (FEC) Table 16-12. TCR Field Descriptions (continued) Field Description Heartbeat control. If set, the heartbeat check performs following end of transmission and the HB bit in the status register is set if the collision input does not assert within the heartbeat window. This bit should only be modified when ECR[ETHER_EN] is cleared.
Page 337 Fast Ethernet Controller (FEC) Offset: 0x0E8 Access: User read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 TYPE PADDR2 Reset — — — — — — — — — — — — — — — — 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 Figure 16-12.
Page 338 Fast Ethernet Controller (FEC) Offset: 0x118 Access: User read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 IADDR1 Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Figure 16-14.
Page 339 Fast Ethernet Controller (FEC) Table 16-18. GAUR Field Descriptions Field Description 31–0 The GADDR1 register contains the upper 32 bits of the 64-bit hash table used in the address recognition process for GADDR1 receive frames with a multicast address. Bit 31 of GADDR1 contains hash index bit 63. Bit 0 of GADDR1 contains hash index bit 32.
Page 340 Fast Ethernet Controller (FEC) Table 16-20. TFWR Field Descriptions Field Description 31–2 Reserved, must be cleared. 1–0 Number of bytes written to transmit FIFO before transmission of a frame begins TFWR 00 64 bytes written 01 64 bytes written 10 128 bytes written 11 192 bytes written 16.4.18 FIFO Receive Bound Register (FRBR) FRBR indicates the upper address bound of the FIFO RAM.
Page 341 Fast Ethernet Controller (FEC) Table 16-22. FRSR Field Descriptions Field Description 31–11 Reserved, must be cleared. Reserved, must be set. 9–2 Address of first receive FIFO location. Acts as delimiter between receive and transmit FIFOs. For proper R_FSTART operation, ensure that R_FSTART is set to 0x48 or greater. 1–0 Reserved, must be cleared.
Page 342 Fast Ethernet Controller (FEC) Table 16-24. ETDSR Field Descriptions Field Description 31–2 Pointer to start of transmit buffer descriptor queue. X_DES_START 1–0 Reserved, must be cleared. 16.4.22 Receive Buffer Size Register (EMRBR) The EMRBR is a user-programmable register that dictates the maximum size of all receive buffers. This value should take into consideration that the receive CRC is always written into the last receive buffer.
Page 343 Fast Ethernet Controller (FEC) 16.5.1 Buffer Descriptors This section provides a description of the operation of the driver/DMA via the buffer descriptors. It is followed by a detailed description of the receive and transmit descriptor fields. 16.5.1.1 Driver/DMA Operation with Buffer Descriptors The data for the FEC frames resides in one or more memory buffers external to the FEC.
Page 344 Fast Ethernet Controller (FEC) In the FEC, the driver notifies the DMA that new transmit frame(s) are available by writing to TDAR. When this register is written to (data value is not significant) the FEC, RISC tells the DMA to read the next transmit BD in the ring.
Page 345 Fast Ethernet Controller (FEC) Offset + 0 — — — Offset + 2 Data Length Offset + 4 Rx Data Buffer Pointer - A[31:16] Offset + 6 Rx Data Buffer Pointer - A[15:0] Figure 16-24. Receive Buffer Descriptor (RxBD) Table 16-26. Receive Buffer Descriptor Field Definitions Word Field Description...
Page 346 Fast Ethernet Controller (FEC) Table 16-26. Receive Buffer Descriptor Field Definitions (continued) Word Field Description Offset + 0 Overrun. Written by the FEC. A receive FIFO overrun occurred during frame reception. If this bit is set, the other status bits, M, LG, NO, CR, and CL lose their normal meaning and are zero. This bit is valid only if the L-bit is set.
Page 347 Fast Ethernet Controller (FEC) Table 16-27. Transmit Buffer Descriptor Field Definitions Word Field Description Offset + 0 Ready. Written by the FEC and you. 0 The data buffer associated with this BD is not ready for transmission. You are free to manipulate this BD or its associated data buffer.
Page 348 Fast Ethernet Controller (FEC) 16.5.2 Initialization Sequence This section describes which registers are reset due to hardware reset, which are reset by the FEC RISC, and what locations you must initialize prior to enabling the FEC. 16.5.2.1 Hardware Controlled Initialization In the FEC, hardware resets registers and control logic that generate interrupts.
Page 349 Fast Ethernet Controller (FEC) Table 16-30. FEC User Initialization (Before ECR[ETHER_EN]) Description Initialize FRSR (optional) Initialize EMRBR Initialize ERDSR Initialize ETDSR Initialize (Empty) Transmit Descriptor ring Initialize (Empty) Receive Descriptor ring 16.5.4 Microcontroller Initialization In the FEC, the descriptor control RISC initializes some registers after ECR[ETHER_EN] is asserted. After the microcontroller initialization sequence is complete, hardware is ready for operation.
Page 350 Fast Ethernet Controller (FEC) Table 16-32. MII Mode Signal Description EMAC pin Transmit Clock FEC_TXCLK Transmit Enable FEC_TXEN Transmit Data FEC_TXD[3:0] Transmit Error FEC_TXER Collision FEC_COL Carrier Sense FEC_CRS Receive Clock FEC_RXCLK Receive Data Valid FEC_RXDV Receive Data FEC_RXD[3:0] Receive Error FEC_RXER Management Data Clock FEC_MDC...
Page 351 Fast Ethernet Controller (FEC) busy (FEC_CRS is asserted). Before transmitting, the controller waits for carrier sense to become inactive, then determines if carrier sense stays inactive for 60 bit times. If so, transmission begins after waiting an additional 36 bit times (96 bit times after carrier sense originally became inactive). See Section 16.5.15.1, “Transmission Errors,”...
Page 352 Fast Ethernet Controller (FEC) 16.5.8 FEC Frame Reception The FEC receiver works with almost no intervention from the host and can perform address recognition, CRC checking, short frame checking, and maximum frame length checking. The Ethernet controller receives serial data lsb first. When the driver enables the FEC receiver by setting ECR[ETHER_EN], it immediately starts processing receive frames.
Page 353 Fast Ethernet Controller (FEC) group address is determined by the I/G bit in the destination address field. A flowchart for address recognition on received frames appears in the figures below. Address recognition is accomplished through the use of the receive block and microcode running on the microcontroller.
Page 354 Fast Ethernet Controller (FEC) Accept/Reject Frame True False Broadcast Addr Receive Address Recognition True False Hash Match BC_REJ = 1 False True Receive Frame Receive Frame Set MC bit in RCV BD if multicast Set BC bit in RCV BD True Exact Match False...
Page 355 Fast Ethernet Controller (FEC) Receive Address Recognition Group Individual I/G Address False True True Exact Match False True False Pause Address Hash Search Individual Table Receive Frame Receive Frame Hash Search Group Table True Match True Match False Receive Frame False Reject Frame Receive Frame...
Page 356 Fast Ethernet Controller (FEC) The user must initialize the hash table registers. Use this CRC32 polynomial to compute the hash: Eqn. 16-2 Table 16-34 contains example destination addresses and corresponding hash values. Table 16-34. Destination Address to 6-Bit Hash 6-bit Hash Hash Decimal 48-bit DA (in hex)
Page 357 Fast Ethernet Controller (FEC) Table 16-34. Destination Address to 6-Bit Hash (continued) 6-bit Hash Hash Decimal 48-bit DA (in hex) Value 59FF_FFFF_FFFF 0x1C 79FF_FFFF_FFFF 0x1D 29FF_FFFF_FFFF 0x1E 19FF_FFFF_FFFF 0x1F D1FF_FFFF_FFFF 0x20 F1FF_FFFF_FFFF 0x21 B1FF_FFFF_FFFF 0x22 91FF_FFFF_FFFF 0x23 11FF_FFFF_FFFF 0x24 31FF_FFFF_FFFF 0x25 71FF_FFFF_FFFF 0x26...
Page 358 Fast Ethernet Controller (FEC) Table 16-34. Destination Address to 6-Bit Hash (continued) 6-bit Hash Hash Decimal 48-bit DA (in hex) Value FDFF_FFFF_FFFF 0x3C DDFF_FFFF_FFFF 0x3D 9DFF_FFFF_FFFF 0x3E BDFF_FFFF_FFFF 0x3F 16.5.11 Full Duplex Flow Control Full-duplex flow control allows you to transmit pause frames and to detect received pause frames. Upon detection of a pause frame, MAC data frame transmission stops for a given pause duration.
Page 359 Fast Ethernet Controller (FEC) When the transmitter pauses due to receiver/microcontroller pause frame detection, TCR[TFC_PAUSE] may remain set and cause the transmission of a single pause frame. In this case, the EIR[GRA] interrupt is not asserted. 16.5.12 Inter-Packet Gap (IPG) Time The minimum inter-packet gap time for back-to-back transmission is 96 bit times.
Page 360 Fast Ethernet Controller (FEC) 16.5.15.1 Transmission Errors 16.5.15.1.1 Transmitter Underrun If this error occurs, the FEC sends 32 bits that ensure a CRC error and stops transmitting. All remaining buffers for that frame are then flushed and closed, and EIR[UN] is set. The FEC then continues to the next transmit buffer descriptor and begin transmitting the next frame.
Page 361 Fast Ethernet Controller (FEC) 16.5.15.2.3 CRC Error When a CRC error occurs with no dribble bits, FEC closes the buffer and sets RxBD[CR]. CRC checking cannot be disabled, but the CRC error can be ignored if checking is not required. 16.5.15.2.4 Frame Length Violation When the receive frame length exceeds MAX_FL bytes the BABR interrupt is generated, and RxBD[LG] is set.
Page 362 Chapter 17 Inter-Integrated Circuit (IIC) 17.1 Introduction The inter-integrated circuit (IIC) provides a method of communication between a number of device. The interface is designed to operate up to 100 kbps with maximum bus loading and timing. The device is capable of operating at higher baud rates, up to a maximum of clock/20, with reduced bus loading.
Page 363 Inter-Integrated Circuit (IIC) 17.1.1 Features The IIC includes these distinctive features: • Compatible with IIC bus standard • Multi-master operation • Software programmable for one of 64 different serial clock frequencies • Software selectable acknowledge bit • Interrupt driven byte-by-byte data transfer •...
Page 364 Inter-Integrated Circuit (IIC) 17.1.3 Block Diagram Figure 17-1 is a block diagram of the IIC. ADDRESS DATA BUS INTERRUPT ADDR_DECODE DATA_MUX CTRL_REG FREQ_REG ADDR_REG STATUS_REG DATA_REG INPUT FILTER SYNC IN/OUT START DATA STOP SHIFT ARBITRATION REGISTER ACK/NACK TIMEOUTS CONTROL CLOCK ADDRESS CONTROL COMPARE...
Page 365 Inter-Integrated Circuit (IIC) 17.3 Register Definition 17.3.1 Module Memory Map The IIC has 10 8-bit registers. The base address of the module is hardware programmable. The IIC register map is fixed and begins at the module’s base address. Table 17-1 summarizes the IIC module’s address space.
Page 366 Inter-Integrated Circuit (IIC) Table 17-2. IICA1 Field Descriptions Field Description Slave Address 1— The AD[7:1] field contains the slave address for the IIC module. This field is used on the 7-bit AD[7:1] address scheme and the lower seven bits of the 10-bit address scheme. 17.3.3 IIC Frequency Divider Register (IICF) MULT...
Page 367 Inter-Integrated Circuit (IIC) Hold times (μs) MULT SCL Start SCL Stop 0x00 3.500 3.000 5.500 0x07 2.500 4.000 5.250 0x0B 2.250 4.000 5.250 0x14 2.125 4.250 5.125 0x18 1.125 4.750 5.125 MCF51CN128 Reference Manual, Rev. 6 17-6 Freescale Semiconductor...
Page 368 Inter-Integrated Circuit (IIC) Table 17-4. IIC Divider and Hold Values SCL Hold SDA Hold SCL Hold SCL Hold SDA Hold SDA Hold (Start) (Stop) (Start) (Stop) (hex) Divider Value (hex) Divider Value Value Value Value Value 1024 1152 1280 1536 1920 1280 1536...
Page 369 Inter-Integrated Circuit (IIC) 17.3.4 IIC Control Register (IICC1) IICEN IICIE TXAK RSTA Reset = Unimplemented or Reserved Figure 17-4. IIC Control Register (IICC1) Table 17-5. IICC1 Field Descriptions Field Description IIC Enable — The IICEN bit determines whether the IIC module is enabled. IICEN 0 IIC is not enabled.
Page 370 Inter-Integrated Circuit (IIC) 17.3.5 IIC Status Register (IICS) BUSY RXAK IAAS ARBL IICIF Reset = Unimplemented or Reserved Figure 17-5. IIC Status Register (IICS) Table 17-6. IICS Field Descriptions Field Description Transfer Complete Flag — This bit is set on the completion of a byte and acknowledge bit transfer. Note that this bit is only valid during or immediately following a transfer to the IIC module or from the IIC module.The TCF bit is cleared by reading the IICD register in receive mode or writing to the IICD in transmit mode.
Page 371 Inter-Integrated Circuit (IIC) Table 17-6. IICS Field Descriptions (continued) Field Description IIC Interrupt Flag — The IICIF bit is set when an interrupt is pending. This bit must be cleared by software, by IICIF writing a 1 to it in the interrupt routine. One of the following events can set the IICIF bit: •...
Page 372 Inter-Integrated Circuit (IIC) Reading the IICD returns the last byte received while the IIC is configured in either master receive or slave receive modes. The IICD does not reflect every byte that is transmitted on the IIC bus, nor can software verify that a byte has been written to the IICD correctly by reading it back.
Page 373 Inter-Integrated Circuit (IIC) 17.3.7 IIC Control Register 2 (IICC2) GCAEN ADEXT AD10 Reset = Unimplemented or Reserved Figure 17-7. IIC Control Register (IICC2) Table 17-8. IICC2 Field Descriptions Field Description General Call Address Enable — The GCAEN bit enables or disables general call address. GCAEN 0 General call address is disabled 1 General call address is enabled.
Page 374 Inter-Integrated Circuit (IIC) 17.3.8 IIC SMBus Control and Status Register (IICSMB) SHTF FACK ALERTEN SIICAEN TCKSEL SLTF Reset = Unimplemented or Reserved NOTE Table 17-9. IICSMB Field Descriptions Field Description Fast NACK/ACK enable — For SMBus Packet Error Checking, CPU should be able to issue an ACK or NACK FACK according to the result of receiving data byte.
Page 375 Inter-Integrated Circuit (IIC) 17.3.9 IIC Address Register 2 (IICA2) SAD7 SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 Reset = Unimplemented or Reserved Field Description SMBUs Address — The AD[7:1] field contains the slave address to be used by the SMBus. This field is used on SAD[7:1] the device default address or other related address.
Page 376 Inter-Integrated Circuit (IIC) 17.3.12 IIC Programmable Input Glitch Filter (IICFLT) FLT3 FLT2 FLT1 FLT0 Reset Unimplemented or Reserved Table 17-10. IICFLT Field Descriptions Field Description IIC Programmable Filter Factor contains the programming controls for the width of glitch (in terms of bus clock cycles) the filter should absorb;...
Page 377 Inter-Integrated Circuit (IIC) 17.4 Functional Description This section provides a complete functional description of the IIC module. 17.4.1 IIC Protocol The IIC bus system uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. All devices connected to it must have open drain or open collector outputs.
Page 378 Inter-Integrated Circuit (IIC) 17.4.1.1 START Signal When the bus is free; i.e., no master device is engaging the bus (both SCL and SDA lines are at logical high), a master may initiate communication by sending a START signal. As shown in Figure 17-8, a START signal is defined as a high-to-low transition of SDA while SCL is high.
Page 379 Inter-Integrated Circuit (IIC) 17.4.1.4 STOP Signal The master can terminate the communication by generating a STOP signal to free the bus. However, the master may generate a START signal followed by a calling command without generating a STOP signal first. This is called repeated START. A STOP signal is defined as a low-to-high transition of SDA while SCL at logical 1 (see Figure 17-8).
Page 380 Inter-Integrated Circuit (IIC) START COUNTING HIGH PERIOD DELAY SCL1 SCL2 INTERNAL COUNTER RESET Figure 17-9. IIC Clock Synchronization 17.4.1.8 Handshaking The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices may hold the SCL low after completion of one byte transfer (9 bits). In such case, it halts the bus clock and forces the master clock into wait states until the slave releases the SCL line.
Page 381 Inter-Integrated Circuit (IIC) 17.4.2 10-bit Address For 10-bit addressing, 11110b is used for the first 5 bits of the first address byte. Various combinations of read/write formats are possible within a transfer that includes 10-bit addressing. 17.4.2.1 Master-Transmitter Addresses a Slave-Receiver The transfer direction is not changed (see Table 17-11).
Page 382 Inter-Integrated Circuit (IIC) 17.4.3 Address Matching All received Addresses can be requested in 7-bit or 10-bit address. IIC Address Register 1, which contains IIC primary slave address, always participates the address matching process. If the GCAEN bit is set, general call participates the address matching process. If the ALERTEN bit is set, alert response participates the address matching process.
Page 383 Inter-Integrated Circuit (IIC) 17.4.4.1.2 SCL High (SMBus Free) Timeout The IIC shall assume that the bus is idle, when it has determined that the SMBCLK and SMBDAT signals are high for at least THIGH:MAX. HIGH timeout can occur in two ways: 1.
Page 384 Inter-Integrated Circuit (IIC) 17.4.4.2 FAST ACK and NACK To improve reliability and communication robustness, implementation of Packet Error Checking (PEC) by SMBus devices is optional for SMBus devices but required for devices participating in and only during the Address Resolution Protocol (ARP) process. The PEC is a CRC-8 error checking byte, calculated on all the message bytes.
Page 385 Inter-Integrated Circuit (IIC) NOTE In Master receive mode the FACK should be set zero before the last byte transfer. Table 17-13. Interrupt Summary Interrupt Source Status Flag Local Enable Complete 1-byte transfer IICIF IICIE Match of received calling address IAAS IICIF IICIE Arbitration Lost...
Page 386 Inter-Integrated Circuit (IIC) 17.6.5 Programmable input glitch filter An IIC glitch filter are added outside the IIC legacy modules, but within the IIC package. This filter can absorb glitches on the IIC clock and data lines for I2C module. The width of the glitch to absorb can be specified in terms of number of half bus clock cycles.
Page 387 Inter-Integrated Circuit (IIC) 17.7 Initialization/Application Information Module Initialization (Slave) Write: IICC2 — to enable or disable general call — to select 10-bit or 7-bit addressing mode Write: IICA1 — to set the slave address Write: IICC1 — to enable IIC and interrupts Initialize RAM variables (IICEN = 1 and IICIE = 1) for transmit data Initialize RAM variables used to achieve the routine shown in Figure 17-11...
Page 388 Inter-Integrated Circuit (IIC) IICSLTH SSLT[15:8] IIC SCL Low Time Out Register High SSLT[7:0] IICSLTL IIC SCL Low Time Out Register Low IICFLT FLT0 FLT3 FLT2 FLT1 IIC Programmable Input Glitch Filter MCF51CN128 Reference Manual, Rev. 6 Freescale Semiconductor 17-27...
Page 389 Inter-Integrated Circuit (IIC) Clear IICIF Master Mode Arbitration Tx/Rx Lost Last Byte Clear ARBL Transmitted Last RXAK=0 IAAS=1 IAAS=1 Byte to Be Read Data Transfer Address Transfer See Note 2 See Note 1 End of 2nd Last (Read) Addr Cycle SRW=1 TX/RX Byte to Be Read...
Page 390 Inter-Integrated Circuit (IIC) SLTF? FACK? Clear IICIF Flow Chart1 See Note 2 Master Mode Arbitration Tx/Rx Lost Last Byte Clear ARBL Transmitted Last RXAK=0 IAAS=1 IAAS=1 Byte to Be Read Address Transfer See Note 1 End of 2nd Last (Read) Addr Cycle SRW=1 TX/RX...
Page 391 Chapter 18 Modulo Timer (MTIM) 18.1 Introduction The MTIM is a simple 8-bit timer with several software selectable clock sources and a programmable interrupt. NOTE • For MCUs that have more than one MTIM, the MTIMs are collectively called MTIMx. For example, MTIMx for an MCU with two MTIMs refers to MTIM1 and MTIM2.
Page 392 Modulo Timer (MTIM) 18.1.1 Features Timer system features include: • 8-bit up-counter — Free-running or 8-bit modulo limit — Software controllable interrupt on overflow — Counter reset bit (TRST) — Counter stop bit (TSTP) • Four software selectable clock sources for input to prescaler: —...
Page 393 Modulo Timer (MTIM) 18.1.3 Block Diagram The block diagram for the modulo timer module is shown Figure 18-1. BUSCLK Prescale And Clock TRST 8-Bit Counter XCLK Select Divide Source TSTP (MTIMCNT) TCLK Select SYNC 8-Bit Comparator CLKS MTIM Interrupt Request 8-Bit Modulo (MTIMMOD) TOIE...
Page 394 Modulo Timer (MTIM) Table 18-1. External Signal Description Signal Function TCLK External clock source input into MTIM The TCLK input must be synchronized by the bus clock. Also, variations in duty cycle and clock jitter must be accommodated. Therefore, the TCLK signal must be limited to one-fourth of the bus frequency. The TCLK pin can be muxed with a general-purpose port pin.
Page 395 Modulo Timer (MTIM) 18.3.1 MTIM Status and Control Register (MTIMSC) MTIMSC contains the overflow status flag and control bits that are used to configure the interrupt enable, reset the counter, and stop the counter. TOIE TSTP TRST Reset: Figure 18-3. MTIM Status and Control Register Table 18-2.
Page 396 Modulo Timer (MTIM) 18.3.2 MTIM Clock Configuration Register (MTIMCLK) MTIMCLK contains the clock select bits (CLKS) and the prescaler select bits (PS). CLKS Reset: Figure 18-4. MTIM Clock Configuration Register Table 18-3. MTIMCLK Field Descriptions Field Description Unused register bits, always read 0. Clock Source Select —...
Page 397 Modulo Timer (MTIM) 18.3.3 MTIM Counter Register (MTIMCNT) MTIMCNT is the read-only value of the current MTIM count of the 8-bit counter. COUNT Reset: Figure 18-5. MTIM Counter Register Table 18-4. MTIM Field Descriptions Field Description MTIM Count — These eight read-only bits contain the current value of the 8-bit counter. Writes have no effect to COUNT this register.
Page 398 Modulo Timer (MTIM) 18.4 Functional Description The MTIM is composed of a main 8-bit up-counter with an 8-bit modulo register, a clock source selector, and a prescaler block with nine selectable values. The module also contains software selectable interrupt logic. The MTIM counter (MTIMCNT) has three modes of operation: stopped, free-running, and modulo.
Page 399 Modulo Timer (MTIM) 18.4.1 MTIM Operation Example This section shows an example of the MTIM operation as the counter reaches a matching value from the modulo register. selected clock source MTIM clock (PS=%0010) MTIMCNT 0xA7 0xA8 0xA9 0xAA 0x00 0x01 MTIMMOD: 0xAA Figure 18-7.
Page 400 Chapter 19 Timer/PWM Module (TPM) 19.1 Introduction The TPM is a one-to-eight-channel timer system that supports traditional input capture, output compare, or edge-aligned PWM on each channel. A control bit configures the TPM so all channels are used for center-aligned PWM functions. Timing functions are based on a 16-bit counter with prescaler and modulo features to control frequency and range (period between overflows) of the time reference.
Page 401 Timer/PWM Module (TPM) 19.1.1 Features The TPM includes these distinctive features: • One to eight channels: — Each channel is input capture, output compare, or edge-aligned PWM — Rising-edge, falling-edge, or any-edge input capture trigger — Set, clear, or toggle output compare action —...
Page 402 Timer/PWM Module (TPM) The value of a 16-bit modulo register plus 1 sets the period of the PWM output signal. The channel value register sets the duty cycle of the PWM output signal. You can also choose the polarity of the PWM output signal.
Page 403 Timer/PWM Module (TPM) no clock selected (TPM counter disable) bus clock Prescaler ³(1, 2, 4, 8, 16, 32, 64 or 128) fixed frequency clock synchronizer external clock PS[2:0] CLKSB:CLKSA CPWMS TPM counter Interrupt (16-bit counter) counter reset logic TOIE 16-bit comparator TPMxMODH:TPMxMODL ELS0B ELS0A...
Page 404 Timer/PWM Module (TPM) The TPM channels are programmable independently as input capture, output compare, or edge-aligned PWM channels. Alternately, the TPM can be configured to produce CPWM outputs on all channels. When the TPM is configured for CPWMs (the counter operates as an up/down counter) input capture, output compare, and EPWM functions are not practical.
Page 405 Timer/PWM Module (TPM) be reliably detected—on an input capture pin is four bus clock periods (with ideal clock pulses as near as two bus clocks can be detected). When a channel is configured for output compare (CPWMS = 0, MSnB:MSnA = 0:1, and ELSnB:ELSnA ≠...
Page 406 Timer/PWM Module (TPM) set when the TPM counter is counting down, and the channel value register matches the TPM counter. If ELSnA is set, the corresponding TPMxCHn pin is set when the TPM counter is counting up and the channel value register matches the TPM counter; and it is cleared when the TPM counter is counting down and the channel value register matches the TPM counter.
Page 407 Timer/PWM Module (TPM) 19.3 Register Definition 19.3.1 TPM Status and Control Register (TPMxSC) TPMxSC contains the overflow status flag and control bits used to configure the interrupt enable, TPM configuration, clock source, and prescale factor. These controls relate to all channels within this timer module.
Page 408 Timer/PWM Module (TPM) Table 19-3. TPM Clock Selection (continued) CLKSB:CLKSA TPM Clock to Prescaler Input Fixed frequency clock External clock Table 19-4. Prescale Factor Selection PS[2:0] TPM Clock Divided-by 19.3.2 TPM-Counter Registers (TPMxCNTH:TPMxCNTL) The two read-only TPM counter registers contain the high and low bytes of the value in the TPM counter. Reading either byte (TPMxCNTH or TPMxCNTL) latches the contents of both bytes into a buffer where they remain latched until the other half is read.
Page 409 Timer/PWM Module (TPM) When BDM is active, the timer counter is frozen (this is the value you read). The coherency mechanism is frozen so the buffer latches remain in the state they were in when the BDM became active, even if one or both counter halves are read while BDM is active.
Page 410 Timer/PWM Module (TPM) Reset the TPM counter before writing to the TPM modulo registers to avoid confusion about when the first counter overflow occurs. 19.3.4 TPM Channel n Status and Control Register (TPMxCnSC) TPMxCnSC contains the channel-interrupt-status flag and control bits that configure the interrupt enable, channel configuration, and pin function.
Page 411 Timer/PWM Module (TPM) Table 19-6. Mode, Edge, and Level Selection CPWMS MSnB:MSnA ELSnB:ELSnA Mode Configuration Pin is not controlled by TPM. It is reverted to general purpose I/O or other peripheral control Input capture Capture on rising edge only Capture on falling edge only Capture on rising or falling edge Output compare Software compare only...
Page 412 Timer/PWM Module (TPM) When BDM is active, the coherency mechanism is frozen (unless reset by writing to TPMxCnSC register) so the buffer latches remain in the state they were in when the BDM became active, even if one or both halves of the channel register are read while BDM is active.
Page 413 Timer/PWM Module (TPM) activity depend upon the operating mode, these topics are covered in the associated mode explanation sections. 19.4.1 Counter All timer functions are based on the main 16-bit counter (TPMxCNTH:TPMxCNTL). This section discusses selection of the clock, end-of-count overflow, up-counting vs. up/down counting, and manual counter reset.
Page 414 Timer/PWM Module (TPM) 19.4.1.3 Counting Modes The main timer counter has two counting modes. When center-aligned PWM is selected (CPWMS = 1), the counter operates in up/down counting mode. Otherwise, the counter operates as a simple up counter. As an up counter, the timer counter counts from 0x0000 through its terminal count and continues with 0x0000.
Page 415 Timer/PWM Module (TPM) Writes to any of TPMxCnVH and TPMxCnVL registers actually write to buffer registers. In output compare mode, the TPMxCnVH:TPMxCnVL registers are updated with the value of their write buffer only after both bytes were written and according to the value of CLKSB:CLKSA bits: •...
Page 416 Timer/PWM Module (TPM) (TPMxMODH:TPMxMODL). If the TPM counter is a free-running counter, the update is made when the TPM counter changes from 0xFFFE to 0xFFFF. 19.4.2.4 Center-Aligned PWM Mode This type of PWM output uses the up/down counting mode of the timer counter (CPWMS=1). The channel match value in TPMxCnVH:TPMxCnVL determines the pulse width (duty cycle) of the PWM signal while the period is determined by the value in TPMxMODH:TPMxMODL.
Page 417 Timer/PWM Module (TPM) Input capture, output compare, and edge-aligned PWM functions do not make sense when the counter is operating in up/down counting mode so this implies that all active channels within a TPM must be used in CPWM mode when CPWMS is set. The timer channel registers are buffered to ensure coherent 16-bit updates and to avoid unexpected PWM pulse widths.
Page 418 Timer/PWM Module (TPM) Table 19-7. Interrupt Summary Local Interrupt Source Description Enable TOIE Counter overflow Set each time the TPM counter reaches its terminal count (at transition to its next count value) CHnF CHnIE Channel event An input capture event or channel match took place on channel n The TPM module provides high-true interrupt signals.
Page 419 Timer/PWM Module (TPM) 19.6.2.2.1 Input Capture Events When a channel is configured as an input capture channel, the ELSnB:ELSnA bits select if channel pin is not controlled by TPM, rising edges, falling edges, or any edge as the edge that triggers an input capture event.
Page 420 Chapter 20 Version 1 ColdFire Debug (CF1_DEBUG) 20.1 Introduction This chapter describes the capabilities defined by the Version 1 ColdFire debug architecture. The Version 1 ColdFire core supports BDM functionality using the HCS08’s single-pin interface. The traditional 3-pin full-duplex ColdFire BDM serial communication protocol based on 17-bit data packets is replaced with the HCS08 debug protocol where all communication is based on an 8-bit data packet using a single package pin (BKGD).
Page 421 Version 1 ColdFire Debug (CF1_DEBUG) Version 1 ColdFire Core (CF1Core) Central Processing Unit (CF1Cpu) addr attb RESET IPL_B[2:0] rdata wdata Debug (CF1Dbg) PST/ DDATA BKGD — Instruction fetch pipeline — Operand execution pipeline — Background debug controller CFxBDM — ColdFire background debug module PST/DDATA —...
Page 422 Version 1 ColdFire Debug (CF1_DEBUG) concurrent operation of the processor and BDM-initiated memory commands. In addition, the option is provided to allow interrupts to occur. See Section 20.4.2, “Real-Time Debug Support”. • Program trace support—The ability to determine the dynamic execution path through an application is fundamental for debugging.
Page 423 Version 1 ColdFire Debug (CF1_DEBUG) to clear security, which involves mass erasing the on-chip flash memory. No other debug access is allowed. Secure mode can be used in conjunction with each of the wait and stop low-power modes. If the BDM interface is not enabled, access to the debug resources is limited in the same manner as a secure device.
Page 424 Version 1 ColdFire Debug (CF1_DEBUG) While in halt mode, the core waits for serial background commands rather than executing instructions from the application program. Debug CPU clock/2 is used Halt Return to Halt via as the BDM clock ENBDM=1 BACKGROUND command, HALT instruction, or BDM GO (POR or BDFR=1) with BKGD=0 or...
Page 425 Version 1 ColdFire Debug (CF1_DEBUG) 20.3 Memory Map/Register Definition In addition to the BDM commands that provide access to the processor’s registers and the memory subsystem, the debug module contains a number of registers. Most of these registers (all except the PST/DDATA trace buffer) are also accessible (write-only) from the processor’s supervisor programming model by executing the WDEBUG instruction.
Page 426 Version 1 ColdFire Debug (CF1_DEBUG) Table 20-4. Debug Module Memory Map (continued) Width Section/ Register Name Access Reset Value (bits) Page 0x18 PC breakpoint register 1 (PBR1) PBR1[0] = 0 20.3.8/20-22 0x1A PC breakpoint register 2 (PBR2) PBR2[0] = 0 20.3.8/20-22 0x1B PC breakpoint register 3 (PBR3)
Page 427 Version 1 ColdFire Debug (CF1_DEBUG) DRc[4:0]: 0x00 (CSR) Access: Supervisor write-only BDM read/write BSTAT TRG HALT BKPT Reset Reset Figure 20-3. Configuration/Status Register (CSR) Table 20-5. CSR Field Descriptions Field Description 31–28 Breakpoint status. Provides read-only status (from the BDM port only) information concerning hardware BSTAT breakpoints.
Page 428 Version 1 ColdFire Debug (CF1_DEBUG) Table 20-5. CSR Field Descriptions (continued) Field Description Breakpoint disable. Disables the BACKGROUND command functionality, and allows the execution of the BACKGROUND command to generate a debug interrupt. 0 Normal operation 1 The receipt of a BDM BACKGROUND command signals a debug interrupt to the ColdFire core. The processor makes this interrupt request pending until the next sample point occurs, when the exception is initiated.
Page 429 Version 1 ColdFire Debug (CF1_DEBUG) Table 20-5. CSR Field Descriptions (continued) Field Description Ignore pending interrupts when in single-step mode. 0 Core services any pending interrupt requests signalled while in single-step mode. 1 Core ignores any pending interrupt requests signalled while in single-step mode. Single-step mode enable.
Page 430 Version 1 ColdFire Debug (CF1_DEBUG) DRc: 0x01 (XCSR) Access: Supervisor write-only BDM read/write R CPU CSTAT HALT STOP ESEQC ERASE Reset APCSC Reset Figure 20-4. Extended Configuration/Status Register (XCSR) Table 20-7. XCSR Field Descriptions Field Description Indicates that the CPU is in the halt state. The CPU state may be running, stopped, or halted, which is determined CPUHALT by the CPUHALT and CPUSTOP bits as shown below.
Page 431 Version 1 ColdFire Debug (CF1_DEBUG) Table 20-7. XCSR Field Descriptions (continued) Field Description 29–27 During reads, indicates the BDM command status. CSTAT (R) 000 Command done, no errors ESEQC (W) 001 Command done, data invalid 01x Command done, illegal 1xx Command busy, overrun If an overrun is detected (CSTAT = 1xx), the following sequence is suggested to clear the source of the error: 1.
Page 432 Version 1 ColdFire Debug (CF1_DEBUG) Table 20-7. XCSR Field Descriptions (continued) Field Description 2–1 Automatic PC synchronization control. Determines the periodic interval of PC address captures, if APCSC XCSR[APCENB] is set. When the selected interval is reached, a SYNC_PC command is sent to the ColdFire CPU.
Page 433 Version 1 ColdFire Debug (CF1_DEBUG) Table 20-8. CSR2 Reference Summary (continued) Method Reference Details – WRITE_DREG Writes CSR2[23 0] from the BDM interface. Classified as a non-intrusive BDM command. – WDEBUG Instruction Writes CSR2[23 0] during the core’s execution of WDEBUG instruction. This instruction is a privileged supervisor-mode instruction.
Page 434 Version 1 ColdFire Debug (CF1_DEBUG) Table 20-9. CSR2 Field Descriptions (continued) Field Description Reserved, must be cleared. BDM force halt on BDM reset. Determines operation of the device after a BDM reset. This bit is cleared after a BFHBR power-on reset and is unaffected by any other reset. 0 The device enters normal operation mode following a BDM reset.
Page 435 Version 1 ColdFire Debug (CF1_DEBUG) Table 20-9. CSR2 Field Descriptions (continued) Field Description Automatic PC synchronization divide cycle counts by 16. This bit divides the cycle counts for automatic SYNC_PC APCDIV16 command insertion by 16. See the APCSC and APCENB field descriptions. Reserved, must be cleared.
Page 436 Version 1 ColdFire Debug (CF1_DEBUG) Table 20-10. CSR3 Reference Summary (continued) Method Reference Details – READ_DREG Reads CSR3[31 0] from the BDM interface. Classified as a non-intrusive BDM command. – WRITE_DREG Writes CSR3[23 0] from the BDM interface. Classified as a non-intrusive BDM command. WDEBUG Instruction No operation during the core’s execution of a WDEBUG instruction DRc: 0x03 (CSR3) Access: Supervisor write-only...
Page 437 Version 1 ColdFire Debug (CF1_DEBUG) development system. BAAR is loaded any time AATR is written and is initialized to a value of 0x05, setting supervisor data as the default address space. The upper 24 bits of this register are reserved for future use and any attempted write of these bits is ignored.
Page 438 Version 1 ColdFire Debug (CF1_DEBUG) Table 20-13. AATR Field Descriptions Field Description 31–16 Reserved, must be cleared. Read/write mask. Masks the R bit in address comparisons. 14–13 Size mask. Masks the corresponding SZ bit in address comparisons. 12–11 Transfer type mask. Masks the corresponding TT bit in address comparisons. 10–8 Transfer modifier mask.
Page 439 Version 1 ColdFire Debug (CF1_DEBUG) A write to TDR clears the CSR trigger status bits, CSR[BSTAT]. TDR is accessible in supervisor mode as debug control register 0x07 using the WDEBUG instruction and through the BDM port using the WRITE_DREG command. DRc: 0x07 (TDR) Access: Supervisor write-only BDM write-only...
Page 440 Version 1 ColdFire Debug (CF1_DEBUG) Table 20-14. TDR Field Descriptions (continued) Field Description Level 2 data breakpoint invert. Inverts the logical sense of all the data breakpoint comparators. This can develop a L2DI trigger based on the occurrence of a data value other than the DBR contents. 0 No inversion 1 Invert data breakpoint comparators.
Page 441 Version 1 ColdFire Debug (CF1_DEBUG) Table 20-14. TDR Field Descriptions (continued) Field Description 12–6 Enable level 1 data breakpoint. Setting an L1ED bit enables the corresponding data breakpoint condition based on L1ED the size and placement on the processor’s local data bus. Clearing all L1ED bits disables data breakpoints. TDR Bit Description Data longword.
Page 442 Version 1 ColdFire Debug (CF1_DEBUG) valid bit. These registers’ contents are compared with the processor’s program counter register when TDR is configured appropriately. The PC breakpoint registers are accessible in supervisor mode using the WDEBUG instruction and through the BDM port using the WRITE_DREG command using values shown in Section 20.4.1.4, “BDM Command Set Descriptions”.
Page 443 Version 1 ColdFire Debug (CF1_DEBUG) DRc: 0x09 (PBMR) Access: Supervisor write-only BDM write-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Mask Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Figure 20-12.
Page 444 Version 1 ColdFire Debug (CF1_DEBUG) Table 20-18. ABLR Field Description Field Description 31–0 Low address. Holds the 32-bit address marking the lower bound of the address breakpoint range. Breakpoints for Address specific addresses are programmed into ABLR. Table 20-19. ABHR Field Description Field Description 31–0...
Page 445 Version 1 ColdFire Debug (CF1_DEBUG) Table 20-22. Access Size and Operand Data Location – Address[1 Access Size Operand Location – Byte D[31 – Byte D[23 – Byte D[15 – Byte – Word D[31 – Word D[15 – Longword D[31 20.3.10.1 Resulting Set of Possible Trigger Combinations The resulting set of possible breakpoint trigger combinations consists of the following options where || denotes logical OR, &&...
Page 446 Version 1 ColdFire Debug (CF1_DEBUG) Core register number (CRN) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 0x10 TB #00 TB #01 TB #02 TB #03 TB #04 05[5:4] 0x11...
Page 447 Version 1 ColdFire Debug (CF1_DEBUG) Based on these features, BDM is useful for the following reasons: • In-circuit emulation is not needed, so physical and electrical characteristics of the system are not affected. • BDM is always available for debugging the system and provides a communication link for upgrading firmware in existing systems.
Page 448 Version 1 ColdFire Debug (CF1_DEBUG) Table 20-23. CPU Halt Sources (continued) Halt Source Halt Timing Description BDM disabled or Illegal command response and BACKGROUND command is ignored. flash secure Halt is made pending in the processor. The processor samples for pending halt and interrupt conditions Processor is once per instruction.
Page 449 Version 1 ColdFire Debug (CF1_DEBUG) communication clock rate determined by the target BDC clock rate. The BDC clock rate may be the system bus clock frequency or an alternate frequency source depending on the state of XCSR[CLKSW]. All communication is initiated and controlled by the host which drives a high-to-low edge to signal the beginning of each bit time.
Page 450 Version 1 ColdFire Debug (CF1_DEBUG) changes to clock generator settings, it knows when a different BDC communication speed should be used. The host programmer also knows that no unexpected change in bus frequency could occur to disrupt BDC communications. Normally, setting CLKSW should not be used for general debugging because there is no way to ensure the application program does not change the clock generator settings.
Page 451 Version 1 ColdFire Debug (CF1_DEBUG) MCU drives a brief active-high speedup pulse seven cycles after the perceived start of the bit time. The host should sample the bit level about 10 cycles after it started the bit time. BDC CLOCK (TARGET MCU) HOST DRIVE HIGH-IMPEDANCE...
Page 452 Version 1 ColdFire Debug (CF1_DEBUG) BDC CLOCK (TARGET MCU) HOST DRIVE HIGH-IMPEDANCE TO BKGD PIN SPEEDUP TARGET MCU PULSE DRIVE AND SPEED-UP PULSE PERCEIVED START OF BIT TIME BKGD PIN 10 CYCLES EARLIEST START OF NEXT BIT 10 CYCLES HOST SAMPLES BKGD PIN Figure 20-18.
Page 453 Version 1 ColdFire Debug (CF1_DEBUG) Miscellaneous Commands MSCMD Optional Command Extension Byte (Data) Memory Commands MCMD W if addr, Command Extension Bytes (Address, Data) R/W if data Core Register Commands Command Extension Bytes (Data) PST Trace Buffer Read Commands – Trace Buffer Data[31 24], see Figure 20-15...
Page 454 Version 1 ColdFire Debug (CF1_DEBUG) Table 20-24. BDM Command Field Descriptions Field Description Read/Write. 0 Command is performing a write operation. 1 Command is performing a read operation. 3–0 Miscellaneous command. Defines the miscellaneous command to be performed. MSCMD 0000 No operation 0001 Display the CPU’s program counter (PC) plus optional capture in the PST trace buffer 0010 Enable the BDM acknowledge communication mode 0011 Disable the BDM acknowledge communication mode...
Page 455 Version 1 ColdFire Debug (CF1_DEBUG) 20.4.1.5 BDM Command Set Summary Table 20-25 summarizes the BDM command set. Subsequent paragraphs contain detailed descriptions of each command. The nomenclature below is used in Table 20-25 to describe the structure of the BDM commands.
Page 456: Table Of Contents
Version 1 ColdFire Debug (CF1_DEBUG) Table 20-25. BDM Command Summary (continued) Command Command Command Description Mnemonic Classification if Enb? Structure DUMP_MEM.sz_WS Non-Intrusive (0x33+4 x sz)/d/ss/rd.sz Dump (read) memory based on operand size (sz) and report status. Used with READ_MEM{_WS} to dump large blocks of memory.
Page 457: Classification If Enb
Version 1 ColdFire Debug (CF1_DEBUG) Table 20-25. BDM Command Summary (continued) Command Command Command Description Mnemonic Classification if Enb? Structure SYNC_PC Non-Intrusive 0x01/d Display the CPU’s current PC and capture it in the PST trace buffer WRITE_CREG Active (0xC0+CRN)/wd32/d Write one of the CPU’s control registers Background WRITE_DREG Non-Intrusive...
Page 458 Version 1 ColdFire Debug (CF1_DEBUG) 2. Delays 16 cycles to allow the host to stop driving the high speed-up pulse. 3. Drives BKGD low for 128 BDC clock cycles. 4. Drives a 1-cycle high speed-up pulse to force a fast rise time on BKGD. 5.
Page 459: Non-Intrusive No (0X33+4 X Sz)/D/Ss/Rd.sz
Version 1 ColdFire Debug (CF1_DEBUG) 20.4.1.5.4 BACKGROUND Enter active background mode (if enabled) Non-intrusive 0x04 host → target Provided XCSR[ENBDM] is set (BDM enabled), the BACKGROUND command causes the target MCU to enter active background (halt) mode as soon as the current CPU instruction finishes. If ENBDM is cleared (its default value), the BACKGROUND command is ignored.
Page 460 Version 1 ColdFire Debug (CF1_DEBUG) DUMP_MEM.sz_WS Read memory specified by debug address register with status, Non-intrusive then increment address Memory 0x33 XCSR_SB data[7-0] host → target → target → target host host Memory Memory 0x37 XCSR_SB data[15-8] data[7-0] host → target →...
Page 461 Version 1 ColdFire Debug (CF1_DEBUG) 20.4.1.5.6 FILL_MEM.sz, FILL_MEM.sz_WS FILL_MEM.sz Write memory specified by debug address register, then Non-intrusive increment address Memory 0x12 data[7-0] host → host → target target Memory Memory 0x16 data[15-8] data[7-0] host → host → host → target target target...
Page 462 Version 1 ColdFire Debug (CF1_DEBUG) the core status byte (XCSR_SB) contained in XCSR[31–24] is returned after the write data. XCSR_SB reflects the state after the memory write was performed. NOTE FILL_MEM{_WS} does not check for a valid address; it is a valid command only when preceded by NOP, WRITE_MEM{_WS}, or another FILL_MEM{_WS} command.
Page 463: Read_Creg
Version 1 ColdFire Debug (CF1_DEBUG) 20.4.1.5.9 READ_CREG Read CPU control register Active Background CREG data CREG data CREG data CREG data 0xE0+CRN [31-24] [23-16] [15-8] [7-0] host → target → target → target → target → target host host host host If the processor is halted, this command reads the selected control register and returns the 32-bit result.
Page 464: Read_Mem.sz_Ws
Version 1 ColdFire Debug (CF1_DEBUG) 20.4.1.5.11 READ_MEM.sz, READ_MEM.sz_WS READ_MEM.sz Read memory at the specified address Non-intrusive Memory 0x30 Address[23-0] data[7-0] host → host → target → target target host Memory Memory 0x34 Address[23-0] data[15-8] data[7-0] host → host → target → target →...
Page 465: Read_Pstb
Version 1 ColdFire Debug (CF1_DEBUG) The examples show the READ_MEM.B{_WS}, READ_MEM.W{_WS} and READ_MEM.L{_WS} commands. 20.4.1.5.12 READ_PSTB Read PST trace buffer at the specified address Non-intrusive PSTB data PSTB data PSTB data PSTB data 0x40+CRN [31-24] [23-16] [15-8] [7-0] host → target →...
Page 466: Read_Csr2_Byte
Version 1 ColdFire Debug (CF1_DEBUG) 20.4.1.5.15 READ_CSR2_BYTE Read CSR2 Status Byte Always Available CSR2 0x2E [31–24] host → target → target host Read the most significant byte of CSR2 (CSR2[31–24]). This command can be executed in any mode. 20.4.1.5.16 READ_CSR3_BYTE Read CSR3 Status Byte Always Available CSR3...
Page 467 Version 1 ColdFire Debug (CF1_DEBUG) monitoring as the execution of this command is considerably less obtrusive to the real-time operation of an application than a BACKGROUND/read-PC/GO command sequence. 20.4.1.5.18 WRITE_CREG Write CPU control register Active Background CREG data CREG data CREG data CREG data 0xC0+CRN...
Page 468 Version 1 ColdFire Debug (CF1_DEBUG) 20.4.1.5.20 WRITE_MEM.sz, WRITE_MEM.sz_WS WRITE_MEM.sz Write memory at the specified address Non-intrusive Memory 0x10 Address[23-0] data[7–0] host → host → host → target target target Memory Memory 0x14 Address[23-0] data[15–8] data[7–0] host → host → host → host →...
Page 469 Version 1 ColdFire Debug (CF1_DEBUG) 20.4.1.5.21 WRITE_Rn Write general-purpose CPU register Active Background Rn data Rn data Rn data Rn data 0x40+CRN [31–24] [23–16] [15–8] [7–0] host → host → host → host → host → target target target target target If the processor is halted, this command writes the 32-bit operand to the selected CPU general-purpose register (An, Dn).
Page 470 Version 1 ColdFire Debug (CF1_DEBUG) 20.4.1.6 Serial Interface Hardware Handshake Protocol BDC commands that require CPU execution are ultimately treated at the core clock rate. Because the BDC clock source can be asynchronous relative to the bus frequency when CLKSW is cleared, it is necessary to provide a handshake protocol so the host can determine when an issued command is executed by the CPU.
Page 471 Version 1 ColdFire Debug (CF1_DEBUG) Figure 20-21 shows the ACK handshake protocol in a command level timing diagram. A READ_MEM.B command is used as an example: 1. The 8-bit command code is sent by the host, followed by the address of the memory location to be read.
Page 472 Version 1 ColdFire Debug (CF1_DEBUG) 20.4.1.7 Hardware Handshake Abort Procedure The abort procedure is based on the SYNC command. To abort a command that has not responded with an ACK pulse, the host controller generates a sync request (by driving BKGD low for at least 128 serial clock cycles and then driving it high for one serial clock cycle as a speedup pulse).
Page 473 Version 1 ColdFire Debug (CF1_DEBUG) 3. The host reads the channel status using a READ_XCSR_BYTE command. 4. If XCSR[CSTAT] is 000 then the status is okay; proceed else Halt the CPU using a BDM BACKGROUND command Repeat steps 1,2,3 If XCSR[CSTAT] is 000, then proceed, else reset the device Figure 20-22 shows a SYNC command aborting a READ_MEM.B.
Page 474 Version 1 ColdFire Debug (CF1_DEBUG) AT LEAST 128 CYCLES BDC CLOCK (TARGET MCU) ACK PULSE TARGET MCU HIGH-IMPEDANCE DRIVES TO BKGD PIN ELECTRICAL CONFLICT SPEEDUP PULSE HOST AND TARGET HOST DRIVE TO BKGD PIN DRIVES SYNC TO BKGD PIN HOST SYNC REQUEST PULSE BKGD PIN 16 CYCLES Figure 20-23.
Page 475 Version 1 ColdFire Debug (CF1_DEBUG) 20.4.2 Real-Time Debug Support The ColdFire family supports debugging real-time applications. For these types of embedded systems, the processor must continue to operate during debug. The foundation of this area of debug support is that while the processor cannot be halted to allow debugging, the system can generally tolerate the small intrusions with minimal effect on real-time operation.
Page 476 Version 1 ColdFire Debug (CF1_DEBUG) Table 20-26. CF1 Debug Processor Status Encodings PST[4:0] Definition 0x00 Continue execution. Many instructions execute in one processor cycle. If an instruction requires more processor clock cycles, subsequent clock cycles are indicated by driving PST with this encoding. 0x01 Begin execution of one instruction.
Page 477 Version 1 ColdFire Debug (CF1_DEBUG) Table 20-26. CF1 Debug Processor Status Encodings (continued) PST[4:0] Definition 0x1B This value signals there has been a change in the breakpoint trigger state machine. It appears as a single marker for each state change and is immediately followed by a DDATA value signaling the new breakpoint trigger state encoding.
Page 478 Version 1 ColdFire Debug (CF1_DEBUG) Another example of a variant branch instruction is a JMP (A0) instruction. Figure 20-24 shows the PSTB entries that indicate a JMP (A0) execution, assuming CSR[BTB] was programmed to display the lower two bytes of an address. PST/DDATA Values Description 0x05...
Page 479 Version 1 ColdFire Debug (CF1_DEBUG) 01074: 46fc 2700 mov.w &0x2700,%sr # disable interrupts 01078: 2f08 mov.l %a0,-(%sp) # save a0 0107a: 2f00 mov.l %d0,-(%sp) # save d0 0107c: 302f 0008 mov.w (8,%sp),%d0 # load format/vector word 01080: e488 lsr.l &2,%d0 # align vector number 01082: 0280 0000 00ff andi.l...
Page 480 Version 1 ColdFire Debug (CF1_DEBUG) 010b4: 4e73 # pst = 07, 03, 05, 0d # ddata = 29, 21, 2a, 22 trg_addr = 2a19 << 1 trg_addr = 5432 As the PSTs are compressed, the resulting stream of 6-bit hexadecimal entries is loaded into consecutive locations in the PST trace buffer: PSTB[*]= 1c, 1c, 05, 0d, // interrupt exception...
Page 481 Version 1 ColdFire Debug (CF1_DEBUG) Table 20-27. PST/DDATA Specification for User-Mode Instructions (continued) Instruction Operand Syntax PST/DDATA addi.l #<data>,Dx PST = 0x01 addq.l #<data>,<ea>x PST = 0x01, {PST = 0x0B, DD = source}, {PST = 0x0B, DD = destination} addx.l Dy,Dx PST = 0x01 and.l...
Page 482 Version 1 ColdFire Debug (CF1_DEBUG) Table 20-27. PST/DDATA Specification for User-Mode Instructions (continued) Instruction Operand Syntax PST/DDATA eori.l #<data>,Dx PST = 0x01 ext.l PST = 0x01 ext.w PST = 0x01 extb.l PST = 0x01 illegal PST = 0x01 <ea>y PST = 0x05, {PST = 0x0[DE], DD = target address} <ea>y PST = 0x05, {PST = 0x0[DE], DD = target address}, {PST = 0x0B, DD = destination operand}...
Page 483 Version 1 ColdFire Debug (CF1_DEBUG) Table 20-27. PST/DDATA Specification for User-Mode Instructions (continued) Instruction Operand Syntax PST/DDATA PST = 0x01 not.l PST = 0x01 or.l <ea>y,Dx PST = 0x01, {PST = 0x0B, DD = source operand} or.l Dy,<ea>x PST = 0x01, {PST = 0x0B, DD = source}, {PST = 0x0B, DD = destination} ori.l #<data>,Dx PST = 0x01...
Page 484 Version 1 ColdFire Debug (CF1_DEBUG) During normal exception processing, the PSTB is loaded with two successive 0x1C entries indicating the exception processing state. The exception stack write operands, as well as the vector read and target address of the exception handler may also be displayed.
Page 485 Version 1 ColdFire Debug (CF1_DEBUG) The move-to-SR, STLDSR, and RTE instructions include an optional PST = 0x3 value, indicating an entry into user mode. Similar to the exception processing mode, the stopped state (PST = 0x1E) and the halted state (PST = 0x1F) display this status for two entries when the ColdFire processor enters the given mode.
Page 486: Version 1 Coldfire Debug (Cf1_Debug)
Appendix A Revision History This appendix lists major changes between versions of the MCF51CN128RM document. Changes Between Rev. 2 and Rev. 3 Table 20-29. MCF51CN128RM Rev. 2 to Rev. 3 Changes Chapter Description Parallel/Input/Output Controls Removed set/clear/toggle functionality for GPIO only. This functionality is available for RGPIO.
Page 487 Revision History Changes Between Rev. 4 and Rev. 5 Table 20-31. MCF51CN128RM Rev. 4 to Rev. 5 Changes Chapter Description Memory Table 4-3, changed bit 7 of the SOPT3 register to 0 and grayed out. Analog-to-Digital Converter (ADC12) Section 15.4.4.5, “Sample Time and Total Conversion Time,”...