Pwm Control Register: Low (Pwm_Ctrll) - NXP Semiconductors MC9S08SU16 Reference Manual

Memory Map and Register Descriptions
Absolute
address
(hex)
1820 PWM Configure Register: Low (PWM_CNFGL)
1821 PWM Configure Register: High (PWM_CNFGH)
1822 PWM Channel Control Register: Low (PWM_CCTRLL)
1823 PWM Channel Control Register: High (PWM_CCTRLH)
1826 PWM Pulse Edge Control Register: Low (PWM_PECTRLL)
1829 PWM Compare Invert Register: High (PWM_CINVH)

26.4.1 PWM Control Register: Low (PWM_CTRLL)

Address: 40h base + 0h offset = 40h
Bit 7
Read
PRSC
Write
Reset 0
Field
7–6 Prescaler
PRSC
These buffered read/write bits select the PWM clock frequency illustrated in the table below.
NOTE: Reading the PRSCn bits reads the buffered values and not necessarily the values currently in
00 f
IPBus
01 f
IPBus
10 f
IPBus
11 f
IPBus
5 PWM Reload Interrupt Enable
PWMRIE
This read/write bit enables the PWMF flag to generate interrupt requests. Reset clears PWMRIE.
0 PWMF interrupt requests disabled.
1 PWMF interrupt requests enabled.
4 PWM Reload Flag
PWMF
506
PWM memory map (continued)
Register name
6 5
PWMRIE
0 0
PWM_CTRLL field descriptions
effect. The PRSCn bits take effect at the beginning of the next PWM cycle and only when the
load okay bit, LDOK, is set.
For this device, the f is the high speed clock HSCLK.
IPBus
/2
/4
/8
Table continues on the next page...
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Width
(in bits)
8
8
8
8
8
8
4 3
0
PWMF
0 0
Description
Section/
Access Reset value
26.4.20/
R/W 00h
26.4.21/
R/W 00h
26.4.22/
R/W 00h
26.4.23/
R/W 40h
26.4.24/
R/W 03h
26.4.25/
R/W 00h
2 1
LDOK PWMEN
0 0
NXP Semiconductors
page
520
521
522
524
524
525
0
0