Run Mode - NXP Semiconductors MC9S08SU16 Reference Manual

16.2.3.1 Run mode

This is the basic mode of operation.
16.2.3.2 Low-power modes (Wait or Stop)
Any CRC calculation in progress stops when the MCU enters a low-power mode that
disables the module clock. It resumes after the clock is enabled or via the system reset for
exiting the low-power mode. Clock gating for this module is dependent on the MCU.
16.3 Memory map and register descriptions
Absolute
address
(hex)
1890 CRC Data register: High 1 (CRC_DH1)
1891 CRC Data register: High 0 (CRC_DH0)
1892 CRC Data register: Low 1 (CRC_DL1)
1893 CRC Data register: Low 0 (CRC_DL0)
1894 CRC Polynomial Register: High 1 (CRC_PH1)
1895 CRC Polynomial Register: High 0 (CRC_PH0)
1896 CRC Polynomial Register: Low 1 (CRC_PL1)
1897 CRC Polynomial Register: Low 0 (CRC_PL0)
1898 CRC Control register (CRC_CTRL)
16.3.1 CRC Data register: High 1 (CRC_DH1)
This section describes the function of CRC data registers (DH1:DH0:DL1:DL0). The set
of CRC data registers contains the value of seed, data, and checksum. When
CTRL[WAS] is set, any write to the data registers will be regarded as seed for CRC
module. When CTRL[WAS] is de-asserted, any write to the data registers will be
regarded as data for CRC module for general CRC computation.
When programming the seed value in 16-bit CRC mode, the DH1:DH0 are not used and
reads to these registers returns an indeterminate value. For 32-bit CRC, all registers are
used.
When programming data values for CRC calculation, data must be provided in DL0
register only. Writes to other bytes of data regsiters are ignored.
NXP Semiconductors
CRC memory map
Register name
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 16 Cyclic redundancy check (CRC)
Width
Access Reset value
(in bits)
8 R/W FFh
8 R/W FFh
8 R/W FFh
8 R/W FFh
8 R/W 00h
8 R/W 00h
8 R/W 10h
8 R/W 21h
8 R/W 00h
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