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NXP Semiconductors ColdFire MCF52235 Reference Manual

NXP Semiconductors ColdFire MCF52235 Reference Manual

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MCF52235 ColdFire

Integrated

Microcontroller Reference Manual

Devices Supported:

MCF52230

MCF52231

MCF52233

MCF52234

MCF52235

Document Number:

MCF52235RM

Rev. 0

04/2006

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Summary of Contents for NXP Semiconductors ColdFire MCF52235

Page 1 ® MCF52235 ColdFire Integrated Microcontroller Reference Manual Devices Supported: MCF52230 MCF52231 MCF52233 MCF52234 MCF52235 Document Number: MCF52235RM Rev. 0 04/2006...
Page 2 How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com Europe, Middle East, and Africa: Information in this document is provided solely to enable system and Freescale Halbleiter Deutschland GmbH software implementers to use Freescale Semiconductor products.
Page 3: Table Of Contents
Table of Contents Chapter 1 Overview MCF52235 Family Configurations ....................2 Block Diagram ..........................2 Part Numbers and Packaging ......................4 Features .............................4 Chapter 2 Signal Descriptions Introduction ............................1 Overview ............................1 Reset Signals .............................8 PLL and Clock Signals ........................8 Mode Selection ..........................8 External Interrupt Signals ........................8 Queued Serial Peripheral Interface (QSPI) ..................9 Fast Ethernet Controller PHY Signals ....................10 C I/O Signals ..........................10...
Page 4 Standard Two Operand Instruction Execution Times ..............21 3.10 Miscellaneous Instruction Execution Times ...................22 3.11 EMAC Instruction Execution Times ....................23 3.12 Branch Instruction Execution Times ....................24 Chapter 4 Enhanced Multiply-Accumulate Unit (EMAC) Multiply-Accumulate Unit ........................1 Introduction to the MAC ........................2 General Operation ..........................2 Memory Map/Register Definition .....................5 EMAC Instruction Set Summary ....................11 Chapter 5...
Page 5 Functional Description ........................12 Initialization/Application Information ....................13 Chapter 9 Power Management Introduction ............................1 Memory Map/Register Definition .....................1 IPS Bus Timeout Monitor .......................10 Functional Description ........................11 Chapter 10 Reset Controller Module 10.1 Introduction ............................1 10.2 Features .............................1 10.3 Block Diagram ..........................1 10.4 Signals ...............................2 10.5 Memory Map and Registers ......................2 10.6 Functional Description ........................5 Chapter 11...
Page 6 Chapter 14 General Purpose I/O Module 14.1 Introduction ............................1 14.2 Overview ............................2 14.3 Features .............................3 14.4 Signal Descriptions ...........................3 14.5 Memory Map/Register Definition .....................4 14.6 Register Descriptions ........................6 14.7 Ports Interrupts ..........................15 Chapter 15 Interrupt Controller Module 15.1 68K/ColdFire Interrupt Architecture Overview ................1 15.2 Memory Map .............................4 15.3 Register Descriptions ........................5 15.4 Low-Power Wakeup Operation .......................18...
Page 7 19.3 Memory Map and Register Descriptions ..................5 19.4 Functional Description ........................21 Chapter 20 DMA Controller Module 20.1 Introduction ............................1 20.2 M-bus Priority Level (MPL) ......................4 20.3 DMA Transfer Overview ........................4 20.4 Memory Map/Register Definition .....................5 20.5 Functional Description ........................16 Chapter 21 EzPort 21.1 Features .............................1 21.2 Modes of Operation ...........................1...
Page 8 Chapter 25 Queued Serial Peripheral Interface (QSPI) 25.1 Introduction ............................1 25.2 External Signal Description ......................2 25.3 Memory Map/Register Definition .....................3 25.4 Functional Description ........................10 25.5 Initialization/Application Information ....................16 Chapter 26 UART Modules 26.1 Introduction ............................1 26.2 External Signal Description ......................3 26.3 Memory Map/Register Definition .....................4 26.4 Functional Description ........................18 Chapter 27...
Page 9 Chapter 31 Debug Module 31.1 Introduction ............................1 31.2 External Signal Description ......................2 31.3 Real-Time Trace Support ........................3 31.4 Memory Map/Register Definition .....................6 31.5 Background Debug Mode (BDM) ....................17 31.6 Real-Time Debug Support .......................37 31.7 Processor Status, DDATA Definition ....................40 31.8 Freescale-Recommended BDM Pinout ...................44 Chapter 32 IEEE 1149.1 Test Access Port (JTAG) 32.1 Introduction ............................1...
Page 10 MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor Preliminary...
Page 11 Chapter 1 Overview This chapter provides an overview of the major features and functional components of the MCF52235 ® family of microcontrollers. The MCF52235 family is a highly integrated implementation of the ColdFire family of reduced instruction set computing (RISC) microcontrollers that also includes the MC52230, MCF52231, MC52233 and MC52234 .
Page 12: Overview
Overview MCF52235 Family Configurations Table 1. MCF52235 Family Configurations Module 52230 52231 52233 52234 52235 ColdFire Version 2 Core with EMAC (Enhanced Multiply-Accumulate Unit) System Clock 60 MHz Performance (Dhrystone 2.1 MIPS) Flash / Static RAM (SRAM) 128/32 Kbytes 128/32 Kbytes 256/32 Kbytes Interrupt Controllers (INTC0/INTC1) Fast Analog-to-Digital Converter (ADC)
Page 13 Overview EzPD EzPCK EPHY_TX EzPort EPHY_RX EzPCS EzPQ ICOCn QSPI_DIN, QSPI_DOUT Interrupt Interrupt EPHY Arbiter Controller 1 Controller 2 QSPI_SCK, QSPI_PCSn C_SDA Fast C_SCL Ethernet Controller UnTXD (FEC) UART UART UART UnRXD QSPI UnRTS 4 CH DMA UnCTS DTINn/DTOUTn DTIM DTIM DTIM DTIM...
Page 14: Part Numbers And Packaging
Overview Part Numbers and Packaging Table 1-2. Part Number Summary Part Number Flash / SRAM Key Features Package Speed MCF52230 128 Kbytes / 32 Kbytes 3 UARTs, I C, QSPI, A/D, FEC EPHY, DMA, 80-pin TQFP 60 MHz 16-/32-bit/PWM Timers 112-pin LQFP MCF52231 128 Kbytes / 32 Kbytes 3 UARTs, I...
Page 15 Overview • On-chip memories — 32-Kbyte dual-ported SRAM on CPU internal bus, supporting core and DMA access with standby power supply support — 256 Kbytes of interleaved Flash memory supporting 2-1-1-1 accesses • Power management — Fully static operation with processor sleep and whole chip stop modes —...
Page 16 Overview — “Time stamp” based on 16-bit free-running timer — Global network time, synchronized by a specific message — Maskable interrupts • Three universal asynchronous/synchronous receiver transmitters (UARTs) — 16-bit divider for clock generation — Interrupt control logic with maskable interrupts —...
Page 17 Overview — Output compare with programmable mode for the output pin — Free run and restart modes — Maskable interrupts on input capture or output compare — DMA trigger capability on input capture or output compare • Four-channel general purpose timer —...
Page 18 Overview • Two periodic interrupt timers (PITs) — 16-bit counter — Selectable as free running or count down • Software watchdog timer — 32-bit counter — Low power mode support • Clock Generation Features — 25 MHz crystal input — On-chip PLL can generate core frequencies up to maximum 60MHz operating frequency —...
Page 19 Overview – Low-voltage detection (LVD) — Status flag indication of source of last reset • Chip integration module (CIM) — System configuration during reset — Selects one of three clock modes — Configures output pad drive strength — Unique part identification number and part revision number •...
Page 20 Overview The trigger event can be programmed to generate a processor halt or initiate a debug interrupt exception. The MCF52235 implements revision B+ of the coldfire Debug Architecture. The MCF52235 ’s interrupt servicing options during emulator mode allow real-time critical interrupt service routines to be serviced while processing a debug interrupt event, thereby ensuring that the system continues to operate even during debugging.
Page 21 Overview The SRAM module is also accessible by the DMA. The dual-ported nature of the SRAM makes it ideal for implementing applications with double-buffer schemes, where the processor and a DMA device operate in alternate regions of the SRAM to maximize system performance. 1.4.4.2 Flash The ColdFire Flash module (CFM) is a non-volatile memory (NVM) module that connects to the...
Page 22 Overview 1.4.8 UARTs The MCF52235 has three full-duplex UARTs that function independently. The three UARTs can be clocked by the system bus clock, eliminating the need for an external clock source. On smaller packages, the third UART is multiplexed with other digital I/O functions. 1.4.9 C Bus The I...
Page 23 Overview 1.4.13 General Purpose Timer (GPT) The general purpose timer (GPT) is a 4-channel timer module consisting of a 16-bit programmable counter driven by a 7-stage programmable prescaler. Each of the four channels can be configured for input capture or output compare. Additionally, one of the channels, channel 3, can be configured as a pulse accumulator. A timer overflow function allows software to extend the timing capability of the system beyond the 16-bit range of the counter.
Page 24 Overview 1.4.18 Interrupt Controller (INTC0/INTC1) There are two interrupt controllers on the MCF52235. These interrupt controllers are organized as seven levels with up to nine interrupt sources per level. Each interrupt source has a unique interrupt vector, and provide each peripheral with all necessary interrupts. Each internal interrupt has a programmable level [1-7] and priority within the level.
Page 25: Signal Descriptions
Signal Descriptions Chapter 2 Signal Descriptions Introduction This chapter describes signals implemented on this device and includes an alphabetical listing of signals that characterizes each signal as an input or output, defines its state at reset, and identifies whether a pull-up resistor should be used.
Page 26 Signal Descriptions EzPD EzPCK EPHY_TX EzPort EPHY_RX EzPCS EzPQ ICOCn QSPI_DIN, QSPI_DOUT Interrupt Interrupt EPHY Arbiter Controller 1 Controller 2 QSPI_SCK, QSPI_PCSn C_SDA Fast C_SCL Ethernet Controller UnTXD (FEC) UART UART UART UnRXD QSPI UnRTS 4 CH DMA UnCTS DTINn/DTOUTn DTIM DTIM DTIM...
Page 27 Table 2-1. Pin Functions by Primary and Alternate Purpose Drive Primary Secondary Tertiary Quaternary Wired OR Pull-up / Pin on121 Pin on 112 Pin on 80 Strength / Notes Group Function Function Function Function Control Pull-down MAPBGA LQFP LQFP Control —...
Page 28 Drive Primary Secondary Tertiary Quaternary Wired OR Pull-up / Pin on121 Pin on 112 Pin on 80 Strength / Notes Group Function Function Function Function Control Pull-down MAPBGA LQFP LQFP Control Ethernet ACTLED — — PLD[0] PDSR[32] PWOR[8] — — LEDs COLLED —...
Page 29 Drive Primary Secondary Tertiary Quaternary Wired OR Pull-up / Pin on121 Pin on 112 Pin on 80 Strength / Notes Group Function Function Function Function Control Pull-down MAPBGA LQFP LQFP Control Interrupts IRQ15 — — PGP[7] PSDR[47] — pull-up — —...
Page 30 Drive Primary Secondary Tertiary Quaternary Wired OR Pull-up / Pin on121 Pin on 112 Pin on 80 Strength / Notes Group Function Function Function Function Control Pull-down MAPBGA LQFP LQFP Control PWM7 — — PTD[3] PDSR[31] — — — — PWM5 —...
Page 31 Drive Primary Secondary Tertiary Quaternary Wired OR Pull-up / Pin on121 Pin on 112 Pin on 80 Strength / Notes Group Function Function Function Function Control Pull-down MAPBGA LQFP LQFP Control UART 0 CTS0 CANRX FEC_RXCLK PUA[3] PDSR[11] — — —...
Page 32: Reset Signals
Signal Descriptions Reset Signals Table 2-2 describes signals that are used to either reset the chip or as a reset indication. Table 2-2. Reset Signals Signal Name Abbreviation Function Reset In RSTI Primary reset input to the device. Asserting RSTI immediately resets the CPU and peripherals.
Page 33: Queued Serial Peripheral Interface (Qspi)
Signal Descriptions Queued Serial Peripheral Interface (QSPI) Table 2-6 describes the QSPI signals. Table 2-6. Queued Serial Peripheral Interface (QSPI) Signals Signal Name Abbreviation Function QSPI Synchronous QSPI_DOUT Provides the serial data from the QSPI and can be programmed to be Serial Output driven on the rising or falling edge of QSPI_CLK.
Page 34: Fast Ethernet Controller Phy Signals
Signal Descriptions Fast Ethernet Controller PHY Signals Table 7 describes the Fast Ethernet Controller (FEC) Signals. Table 7. Fast Ethernet Controller (FEC) Signals Signal Name Abbreviation Function Twisted Pair Input + Differential Ethernet twisted-pair input pin. This pin is high-impedance out of reset.
Page 35: Uart Module Signals
Signal Descriptions 2.10 UART Module Signals Table 2-9 describes the UART module signals. Table 2-9. UART Module Signals Signal Name Abbreviation Function Transmit Serial Data Output UTXDn Transmitter serial data outputs for the UART modules. The output is held high (mark condition) when the transmitter is disabled, idle, or in the local loopback mode.
Page 36: 2.13 General Purpose Timer Signals
Signal Descriptions 2.13 General Purpose Timer Signals Table 2-12 describes the general purpose timer signals. Table 2-12. GPT Signals Signal Name Abbreviation Function General Purpose Timer GPT[3:0] Inputs to or outputs from the general purpose timer module Input/Output 2.14 Pulse Width Modulator Signals Table 2-13 describes the PWM signals.
Page 37: 2.16 Ezport Signal Descriptions
Signal Descriptions Table 2-14. Debug Support Signals (continued) Signal Name Abbreviation Function Development Serial Development Serial Input. Internally synchronized input that provides Input data input for the serial communication port to the debug module, once the DSCLK has been seen as high (logic 1). Development Serial Development Serial Output.
Page 38: 2.17 Power And Ground Pins
Signal Descriptions 2.17 Power and Ground Pins The pins described in Table 2-16 provide system power and ground to the chip. Multiple pins are provided for adequate current capability. All power supply pins must have adequate decoupling (bypass capacitance) for high-frequency noise suppression. Table 2-16.
Page 39 Signal Descriptions 0.22µF 1000pF 10µF 0.1µF 0.1µF 10µH Tantalum 0.1µF SSX1 0.1µF 3.3V MCF52235 DDX1 DDX2 0.1µF SSX2 Pin numbering is shown for the 80-lead TQFP 0.22µF 0.22µF 0.22µF 0.22µF 0.22µF 12.4KΩ optional Figure 2. Suggested connection scheme for Power and Ground MCF52235 ColdFire®...
Page 40 Signal Descriptions MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 0 2-16 Freescale Semiconductor Preliminary...
Page 41: Coldfire Core
Chapter 3 ColdFire Core ® This section describes the organization of the Version 2 (V2) ColdFire processor core and an overview of the program-visible registers. For detailed information on instructions, see the ISA_A+ definition in the ColdFire Family Programmer’s Reference Manual. Processor Pipelines Figure 3-1 is a block diagram showing the processor pipelines of a V2 ColdFire core.
Page 42: Memory Map/Register Description
ColdFire Core instruction, fetches the required operands and then executes the required function. Since the IFP and OEP pipelines are decoupled by an instruction buffer which serves as a FIFO queue, the IFP is able to prefetch instructions in advance of their actual use by the OEP thereby minimizing time stalled waiting for instructions.
Page 43 ColdFire Core • 16-bit status register (SR) • 32-bit supervisor stack pointer (SSP) • 32-bit vector base register (VBR) • Two 32-bit memory base address registers (RAMBAR, FLASHBAR) Table 3-1. ColdFire Core Programming Model Width Written with DRc[4–0] Register Access Reset Value Section/Page (bits)
Page 44 ColdFire Core 3.2.1 Data Registers (D0–D7) Registers D0–D7 are used as data registers for bit (1-bit), byte (8-bit), word (16-bit) and longword (32-bit) operations; they can also be used as index registers. NOTE Registers D0 and D1 contain hardware configuration details after reset. See Section 3.6.14, “Reset Exception,”...
Page 45 ColdFire Core The BDM programming model supports direct reads and writes to A7 and OTHER_A7. It is the responsibility of the external development system to determine, based on the setting of SR[S], the mapping of A7 and OTHER_A7 to the two program-visible definitions (SSP and USP). To support dual stack pointers, the following two supervisor instructions are included in the ColdFire instruction set architecture to load/store the USP: move.l Ay, USP;...
Page 46 ColdFire Core DRc[4:0]: LSB of Status Register (SR) Access: User read-only Reset: — — — — — Figure 3-5. Condition Code Register (CCR) Table 3-2. CCR Field Descriptions Field Description 7–5 Reserved, should be cleared. Extend condition code bit. Set to the value of the C-bit for arithmetic operations; otherwise not affected or set to a specified result.
Page 47 ColdFire Core DRc[4:0]: 0x801 (VBR) Access: Supervisor read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Base Address Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 3-7.
Page 48: Instruction Set Architecture (Isa_A+)
ColdFire Core 3.2.9 Memory Base Address Registers (RAMBAR, FLASHBAR) The memory base address registers are used to specify the base address of the internal SRAM and Flash modules and indicate the types of references mapped to each. Each base address register includes a base address, write-protect bit, address space mask bits, and an enable bit.
Page 49 ColdFire Core All ColdFire processors use an instruction restart exception model. However, Version 2 ColdFire processors require more software support to recover from certain access errors. See Section 3.6.1, “Access Error Exception” for details. Exception processing includes all actions from the detection of the fault condition to the initiation of fetch for the first handler instruction.
Page 50: Exception Stack Frame Definition
ColdFire Core Table 3-5. Exception Vector Assignments (continued) Stacked Vector Vector Program Assignment Number(s) Offset (Hex) Counter 0x010 Fault Illegal instruction 0x014 Fault Divide by zero 6–7 0x018–0x01C — Reserved 0x020 Fault Privilege violation 0x024 Next Trace 0x028 Fault Unimplemented line-a opcode 0x02C Fault Unimplemented line-f opcode...
Page 51: Processor Exceptions
ColdFire Core The 16-bit format/vector word contains 3 unique fields: • A 4-bit format field at the top of the system stack is always written with a value of 4, 5, 6, or 7 by the processor indicating a two-longword frame format. See Table 3-6.
Page 52 ColdFire Core execute an instruction with a faulted opword and/or extension words, the access error is signaled and the instruction aborted. For this type of exception, the programming model has not been altered by the instruction generating the access error. If the access error occurs on an operand read, the processor immediately aborts the current instruction’s execution and initiates exception processing.
Page 53 ColdFire Core 3.6.6 Trace Exception To aid in program development, all ColdFire processors provide an instruction-by-instruction tracing capability. While in trace mode, indicated by setting of the T bit in the status register (SR[15] = 1), the completion of an instruction execution (for all but the STOP instruction) signals a trace exception. This functionality allows a debugger to monitor program execution.
Page 54 ColdFire Core 3.6.10 RTE and Format Error Exception When an RTE instruction is executed, the processor first examines the 4-bit format field to validate the frame type. For a ColdFire core, any attempted RTE execution where the format is not equal to {4,5,6,7} generates a format error.
Page 55 ColdFire Core NOTE Other implementation-specific registers are also affected. Refer to each of the modules in this user’s manual for details on these registers. Once the processor is granted the bus, it then performs two longword read bus cycles. The first longword at address 0 is loaded into the stack pointer and the second longword at address 4 is loaded into the program counter.
Page 56 ColdFire Core Table 3-8. D0 Hardware Configuration Info Field Description (continued) Field Description Divide present. This bit signals if the hardware divider (DIV) is present in the processor core. 0 Divide execute engine not present in core. 1 Divide execute engine is present in core. (This is the value used for this device.) EMAC present.
Page 57 ColdFire Core DRc[4:0]: Load: 0x081 (D1) Access: User read-only Store: 0x181 (D1) CLSZ CCAS CCSZ FLASHSZ Reset MBSZ UCAS SRAMSZ Reset Figure 3-11. D1 Hardware Configuration Info Table 3-9. D1 Hardware Configuration Information Field Description Field Description 31–30 Cache line size. This field is fixed to a hex value of 0x0 indicating a 16-byte cache line size. CLSZ 29–28 Configurable cache associativity.
Page 58: Instruction Execution Timing
ColdFire Core Table 3-9. D1 Hardware Configuration Information Field Description (continued) Field Description 13–12 Unified cache associativity. Defines the unified cache set-associativity. UCAS 00 Four-way 01 Direct mapped (This is the value used for this device) Else Reserved for future use 11–8 Reserved.
Page 59 ColdFire Core is stalled until the resource again becomes available. Thus, the maximum pipeline stall involving consecutive STORE operations is 2 cycles. The MOVEM instruction uses a different set of resources and this stall does not apply. 3. The OEP completes all memory accesses without any stall conditions caused by the memory itself. Thus, the timing details provided in this section assume that an infinite zero-wait state memory is attached to the processor core.
Page 60: Standard One Operand Instruction Execution Times
ColdFire Core Table 3-11. MOVE Byte and Word Execution Times (continued) Destination Source (Ax) (Ax)+ -(Ax) (d16,Ax) (d8,Ax,Xi*SF) xxx.wl (d8,PC,Xi*SF) 4(1/0) 4(1/1) 4(1/1) 4(1/1)) — — — #xxx 1(0/0) 3(0/1) 3(0/1) 3(0/1) — — — Table 3-12. MOVE Long Execution Times Destination Source (Ax)
Page 61: Standard Two Operand Instruction Execution Times
ColdFire Core Table 3-13. One Operand Instruction Execution Times (continued) Effective Address Opcode <EA> (An) (An)+ -(An) (d16,An) (d8,An,Xn*SF) xxx.wl #xxx neg.l 1(0/0) — — — — — — — negx.l 1(0/0) — — — — — — — not.l 1(0/0) —...
Page 62: Miscellaneous Instruction Execution Times
ColdFire Core Table 3-14. Two Operand Instruction Execution Times (continued) Effective Address Opcode <EA> (d16,An) (d8,An,Xn*SF) (An) (An)+ -(An) xxx.wl #xxx (d16,PC) (d8,PC,Xn*SF) divs.w <ea>,Dx 20(0/0) 23(1/0) 23(1/0) 23(1/0) 23(1/0) 24(1/0) 23(1/0) 20(0/0) divu.w <ea>,Dx 20(0/0) 23(1/0) 23(1/0) 23(1/0) 23(1/0) 24(1/0) 23(1/0) 20(0/0)
Page 63: Emac Instruction Execution Times
ColdFire Core Table 3-15. Miscellaneous Instruction Execution Times (continued) Effective Address Opcode <EA> (An) (An)+ -(An) (d16,An) (d8,An,Xn*SF) xxx.wl #xxx movem.l &list,<ea> — 1+n(0/n) — — 1+n(0/n) — — — 3(0/0) — — — — — — — <ea> — 2(0/1) —...
Page 64: Branch Instruction Execution Times
ColdFire Core Table 3-16. EMAC Instruction Execution Times (continued) Effective Address Opcode <EA> (d8,An, (An) (An)+ -(An) (d16,An) xxx.wl #xxx Xn*SF) msac.w Ry, Rx, <ea>, Rw — 2(1/0) 2(1/0) 2(1/0) 2(1/0) — — — msac.l Ry, Rx, <ea>, Rw, Raccx —...
Page 65 ColdFire Core Table 3-18. BRA, Bcc Instruction Execution Times Forward Forward Backward Backward Opcode Taken Not Taken Taken Not Taken 2(0/0) — 2(0/0) — 3(0/0) 1(0/0) 2(0/0) 3(0/0) MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 3-25 Preliminary...
Page 66 ColdFire Core MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 0 3-26 Freescale Semiconductor Preliminary...
Page 67: Enhanced Multiply-Accumulate Unit (Emac)
Chapter 4 Enhanced Multiply-Accumulate Unit (EMAC) This chapter describes the functionality, microarchitecture, and performance of the enhanced multiply-accumulate (EMAC) unit in the ColdFire family of processors. Multiply-Accumulate Unit The MAC design provides a set of DSP operations that can be used to improve the performance of embedded code while supporting the integer multiply instructions of the baseline ColdFire architecture.
Page 68: Introduction To The Mac
Enhanced Multiply-Accumulate Unit (EMAC) Operand Y Operand X Shift 0,1,-1 + / - Accumulator(s) Figure 4-1. Multiply-Accumulate Functionality Diagram Introduction to the MAC The MAC is an extension of the basic multiplier found in most microprocessors. It is typically implemented in hardware within an architecture and supports rapid execution of signal processing algorithms in fewer cycles than comparable non-MAC architectures.
Page 69 Enhanced Multiply-Accumulate Unit (EMAC) execution times are minimized and deterministic compared to the 2-bit/cycle algorithm with early termination that the OEP normally uses if no MAC hardware is present. The added MAC instructions to the ColdFire ISA provide for the multiplication of two numbers, followed by the addition or subtraction of the product to or from the value in an accumulator.
Page 70 Enhanced Multiply-Accumulate Unit (EMAC) OperandY OperandX Product Extended Product Accumulator Extension Byte Upper [7:0] Accumulator [31:0] Extension Byte Lower [7:0] Figure 4-3. Signed and Unsigned Integer Alignment Thus, the 48-bit accumulator definition is a function of the EMAC operating mode. Given that each 48-bit accumulator is the concatenation of 16-bit accumulator extension register (ACCextn) contents and 32-bit ACCn contents, the specific definitions are as follows: if MACSR[6:5] == 00...
Page 71: Memory Map/Register Definition
Enhanced Multiply-Accumulate Unit (EMAC) The need to move large amounts of data presents an obstacle to obtaining high throughput rates in DSP engines. New and existing ColdFire instructions can accommodate these requirements. A MOVEM instruction can move large blocks of data efficiently by generating line-sized burst references. The ability to simultaneously load an operand from memory into a register and execute a MAC instruction makes some DSP operations such as filtering and convolution more manageable.
Page 72 Enhanced Multiply-Accumulate Unit (EMAC) Table 4-2. MACSR Field Descriptions Field Description 31–12 Reserved, should be cleared. 11–8 Product/accumulation overflow flags. Contains four flags, one per accumulator, that indicate if past MAC or PAVn MSAC instructions generated an overflow during product calculation or the 48-bit accumulation. When a MAC or MSAC instruction is executed, the PAVn flag associated with the destination accumulator is used to form the general overflow flag, MACSR[V].
Page 73 Enhanced Multiply-Accumulate Unit (EMAC) Table 4-2. MACSR Field Descriptions (continued) Field Description Overflow. Set if an arithmetic overflow occurs on a MAC or MSAC instruction indicating that the result cannot be represented in the limited width of the EMAC. V is set only if a product overflow occurs or the accumulation overflows the 48-bit structure.
Page 74 Enhanced Multiply-Accumulate Unit (EMAC) To understand the round-to-nearest-even method, consider the following example involving the rounding of a 32-bit number, R0, to a 16-bit number. Using this method, the 32-bit number is rounded to the closest 16-bit number possible. Let the high-order 16 bits of R0 be named R0.U and the low-order 16 bits be R0.L. •...
Page 75 Enhanced Multiply-Accumulate Unit (EMAC) move.l accext01,d4 ; save the accumulator extensions move.l accext23,d5 move.l mask,d6 ; save the address mask movem.l #0x00ff,(a7) ; move the state to memory The following code performs the EMAC state restore: EMAC_state_restore: movem.l (a7),#0x00ff ; restore the state from memory move.l #0,macsr ;...
Page 76 Enhanced Multiply-Accumulate Unit (EMAC) if extension word, bit [5] = 1, the MASK bit, then if <ea> = (An) An & {0xFFFF, MASK} if <ea> = (An)+ An = (An + 4) & {0xFFFF, MASK} if <ea> =-(An) = (An - 4) & {0xFFFF, MASK} An = (An - 4) &...
Page 77: Emac Instruction Set Summary
Enhanced Multiply-Accumulate Unit (EMAC) Address: CPU @ 0x807 (ACCext01) Access: User read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Accumulator 0 Upper Accumulator 0 Lower Accumulator 1 Upper Accumulator 1 Lower Extension Byte...
Page 78 Enhanced Multiply-Accumulate Unit (EMAC) Table 4-4. EMAC Instruction Summary (continued) Command Mnemonic Description Store AccExtensions01 MOV.L ACCext01,Rx Writes the contents of accumulator 0,1 extension bytes into a CPU register Store AccExtensions23 MOV.L ACCext23,Rx Writes the contents of accumulator 2,3 extension bytes into a CPU register 4.5.1 EMAC Instruction Execution Times...
Page 79 Enhanced Multiply-Accumulate Unit (EMAC) As with change or use stalls between accumulators and general-purpose registers, introducing intervening instructions that do not reference the busy register can reduce or eliminate sequence-related store-MAC instruction stalls. In fact, a major benefit of the EMAC is the addition of three accumulators to minimize stalls caused by exchanges between the accumulator(s) and the general-purpose registers.
Page 80 Enhanced Multiply-Accumulate Unit (EMAC) • The optional 1-bit shift of the product is specified using the notation {<< | >>} SF, where <<1 indicates a left shift and >>1 indicates a right shift. The shift is performed before the product is added to or subtracted from the accumulator.
Page 81 Enhanced Multiply-Accumulate Unit (EMAC) /* sign-extend to 48 bits before performing any scaling */ product[47:40] = {8{product[39]}} /* sign-extend */ /* scale product before combining with accumulator */ switch (SF) /* 2-bit scale factor */ case 0: /* no scaling specified */ break;...
Page 82 Enhanced Multiply-Accumulate Unit (EMAC) then operandX[31:0] = {Rx[31:16], 0x0000} else operandX[31:0] = {Rx[15:0], 0x0000} else {operandY[31:0] = Ry[31:0] operandX[31:0] = Rx[31:0] /* perform the multiply */ product[63:0] = (operandY[31:0] * operandX[31:0]) << 1 /* check for product rounding */ if (MACSR.R/T == 1) then { /* perform convergent rounding */ if (product[23:0] >...
Page 83 Enhanced Multiply-Accumulate Unit (EMAC) then operandX[31:0] = {0x0000, Rx[31:16]} else operandX[31:0] = {0x0000, Rx[15:0]} else {operandY[31:0] = Ry[31:0] operandX[31:0] = Rx[31:0] /* perform the multiply */ product[63:0] = operandY[31:0] * operandX[31:0] /* check for product overflow */ if (product[63:40] != 0x0000_00) then { /* product overflow */ MACSR.PAVn = 1...
Page 84 Enhanced Multiply-Accumulate Unit (EMAC) result[47:0] = 0xffff_ffff_ffff /* transfer the result to the accumulator */ ACCx[47:0] = result[47:0] MACSR.V = MACSR.PAVn MACSR.N = ACCx[47] if (ACCx[47:0] == 0x0000_0000_0000) then MACSR.Z = 1 else MACSR.Z = 0 if (ACCx[47:32] == 0x0000) then MACSR.EV = 0 else MACSR.EV = 1 break;...
Page 85: Cau Registers
Chapter 5 Cryptographic Acceleration Unit This chapter describes the Cryptographic Acceleration Unit (CAU) programming model. The CAU is an instruction level coprocessor that is accessed with ColdFire coprocessor instructions (see section XX). The CAU supports acceleration of the following cryptographic algorithms: DES, 3DES, AES, MD5 and SHA-1.
Page 86: Cau Operation
Cryptographic Acceleration Unit RESET: RESET: = Read Only or Reserved Figure 5-1. Status Register (CASR) IC — Illegal Command 1 = Illegal coprocessor command issued 0 = No illegal commands issued DPE — DES Parity Error 1 = DES key parity error detected 0 = No error detected VER —...
Page 87 Cryptographic Acceleration Unit Table 5-2. CAU Commands Command Inst Type Description CMD[8:4] CMD[3:0] Operation Name cp0ld.l CNOP No Operation 0x00 cp0ld.l Load Reg 0x01 Op1 -> CAx cp0st.l Store Reg 0x02 CAx -> Destination cp0ld.l 0x03 CAx + Op1 -> CAx cp0ld.l RADR Reverse and Add...
Page 88 Cryptographic Acceleration Unit 5.3.4 ADR - add to register cp0ld.l <ea>,#ADR+CAx The ADR command adds the source operand specified by <ea> to CAx and stores the result in CAx. 5.3.5 RADR - reverse and add to register cp0ld.l <ea>,#RADR+CAx The RADR command does a byte reverse on the source operand specified by <ea>, adds that value to CAx and stores the result in CAx.
Page 89 Cryptographic Acceleration Unit 5.3.11 AESS - AES substitution cp0ld.l #AESS+CAx The AESS command performs the AES byte substitution operation on CAx and stores the result back to CAx. 5.3.12 AESIS - AES inverse substitution cp0ld.l #AESIS+CAx The AESIS command performs the AES inverse byte substitution operation on CAx and stores the result back to CAx.
Page 90 Cryptographic Acceleration Unit Table 5-5. AESIR Command Example Register Before After 01060B00 01020304 050A0F04 05060708 090E0308 090A0B0C 0D02070C 0D0E0F00 5.3.17 DESR - DES round cp0ld.l #DESR+{IP}+{FP}+{KSx} The DESR command performs a round of the DES algorithm and a key schedule update with the following source and destination designations: CA0=C, CA1=D, CA2=L, CA3=R.
Page 91: Cau Equate Values
Cryptographic Acceleration Unit Table 5-7. Hash Function Codes Hash Function Hash Logic Code Define MD5 F() CA1&CA2 | ~CA1&CA3 MD5 G() CA1&CA3 | CA2&~CA3 MD5 H(), SHA Parity() CA1^CA2^CA3 MD5 I() CA2^(CA1|~CA3) SHA Ch() CA1&CA2 ^ ~CA1&CA3 SHA Maj() CA1&CA2 ^ CA1&CA3 ^ CA2&CA3 5.3.20 SHS - secure hash shift cp0ld.l...
Page 92 Cryptographic Acceleration Unit .set RADR,0x040 .set ADRA,0x050 .set XOR,0x060 .set ROTL,0x070 .set MVRA,0x080 .set MVAR,0x090 .set AESS,0x0A0 .set AESIS,0x0B0 .set AESC,0x0C0 .set AESIC,0x0D0 .set AESR,0x0E0 .set AESIR,0x0F0 .set DESR,0x100 .set DESK,0x110 .set HASH,0x120 .set SHS,0x130 .set MDS,0x140 .set ILL,0x1F0 ; DESR Fields .set IP,0x08...
Page 93: Random Number Generator Accelerator (Rnga)
Chapter 6 Random Number Generator Accelerator (RNGA) A top level block diagram of the RNGA is shown in Figure 6-1. The module is connects to the IP Bus defined in SRS version 3.1.1 IP Interface Specification. Output Register Internal RNGA Core/Control Logic Figure 6-1.
Page 94: Features
Random Number Generator Accelerator (RNGA) Features The RNGA includes these distinctive features: • 32-bit interface • 32-bit Output Register • secure mode • power saving mode Modes of Operation Although the RNGA has several modes, only one is intended for use during normal operation. The other modes were created to aid in verification and testability of the module.
Page 95: Memory Map/Register Definition
Memory Map/Register Definition In this mode the RNGA’s oscillator clocks are shut off. The mode is entered by writing to the Sleep bit in the Control Register. When in this mode, the Output Register will not be loaded. • Scan Mode In this mode the RNGA reconfigures much of its untestable logic so it is testable by scan.
Page 96 Random Number Generator Accelerator (RNGA) no push will occur. In this way the Output Register will be kept as full as possible. The fields in the Control Register are defined in Figure 6-2. 31:5 0x0000000 Interrupt High Assur- Sleep Clear Inter- Mask ance rupt...
Page 97 Memory Map/Register Definition 0 = RNGA is not in Sleep Mode. 6.4.1.2 Status Register The Status Register shown in Figure 6-3 is a read only register which reflects the internal status of the RNGA. Only 32-bit reads of this register is supported. 30:24 23-16 15:8...
Page 98 Random Number Generator Accelerator (RNGA) This bit reflects whether the RNGA is in Sleep mode (i.e. either the Sleep bit in the Control Register is set or the ipg_doze input is asserted). When this bit is a one, the RNGA is in Sleep Mode and the oscillator clocks are inactive.
Page 99 Memory Map/Register Definition Each time the Entropy Register is written, the written value is used to update the internal state of the RNGA. The update is performed in such a way that the entropy in the RNGA’s internal state is preserved. Use of the Entropy Register can increase the entropy but never decrease it.
Page 100 Random Number Generator Accelerator (RNGA) 6.4.1.5 Mode Register This register cannot be accessed when the RNGA is in the Secure Mode. The Mode register is used to configure the RNGA’s mode of operation. Figure 6-6 shows the valid fields in the Mode Register. 31:2 Oscillator Frequency Verification...
Page 101 Memory Map/Register Definition Shift Clock Off The shift registers in the RNGA are clocked by two internally generated clocks. This bit turns these internal clocks on and off. 1 = The shift register clocks are off. 0 = The shift register clocks are on. Force System Clock While in Normal Mode, the shift register clocks are derived from free running oscillators with unknown frequency.
Page 102 Random Number Generator Accelerator (RNGA) asynchronously with respect to the ipg_clk clock domain. In order to avoid unknown values during simulation and meta stable states in silicon, this register should only be read when the Oscillator Counter Control Register is zero (i.e. when the register is not counting). 31:20 19:0 Number of clock pulses received from Oscillator #1...
Page 103: Functional Description
Functional Description Osc #2 Status Indicates that the clock derived from the second oscillator has toggled at least 0x400 times since the last write of the Oscillator Counter Control Register (the act of resetting the RNGA can be considered such a write since the Oscillator Counter Control Register resets to a non zero value). 1 = Oscillator #2 has toggled 0x400 times 0 = Oscillator #2 has not toggled 0x400 times.
Page 104: Initialization/Application Information
Random Number Generator Accelerator (RNGA) Core Engine (Random Number Engine) random control data Output Register Interface Interface Control Block RNGA Core/Control Logic Figure 6-11. RNGA Logic Block Diagram 6.5.3.1 Control The Control Block contains the address decoder, all addressable registers, and control state machines for the RNGA.
Page 105 Initialization/Application Information MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 0 Preliminary Freescale Semiconductor 6-13...
Page 106 Random Number Generator Accelerator (RNGA) MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 0 Preliminary 6-14 Freescale Semiconductor...
Page 107: Clock Module
Chapter 7 Clock Module Introduction The clock module allows the MCF52235 to be configured for one of several clocking methods. Clocking modes include internal phase-locked loop (PLL) clocking with either an external clock reference or an external crystal reference supported by an internal crystal amplifier. The PLL can also be disabled and an external oscillator can be used to clock the device directly.
Page 108: Low-Power Mode Operation
Clock Module 7.3.2 1:1 PLL Mode In 1:1 PLL mode, the PLL synthesizes a frequency equal to the external clock input reference frequency. The post divider is not active. 7.3.3 External Clock Mode In external clock mode, the PLL is bypassed, and the external clock is applied to EXTAL. The resulting operating frequency is equal to the external clock frequency.
Page 109 Clock Module RSTOUT CLKOUT LOCKS EXTAL XTAL PLLMODE LOCK EXTERNAL CLOCK REFERENCE CLOCK LOCS RFD[2:0] TO RESET MODULE PLLREF LOCEN LOLRE LOCRE PLL CLOCK OUT STPMD[1:0] SCALED PLL CLOCK OUT STOP MODE CLKGEN INTERNAL CLOCK CLKOUT PLLSEL DISCLK INTERNAL CLOCKS STOP MODE LOCK PLLMODE...
Page 110: Signal Descriptions
Clock Module RSTOUT STPMD LOCKS LOCK DETECT LOCK LOLRE TO RESET PLLMODE LOCEN MODULE LOCRE LOSS OF CLOCK LOCS DETECT REFERENCE PHASE AND CHARGE CLOCK FREQUENCY FILTER RFD[2:0] PUMP DETECT SCALED PLL CLOCK OUT PLLSEL MDF[2:0] DISCLK ÷ PLL CLOCK CLKOUT (4–18) Figure 7-2.
Page 111: Memory Map And Registers
Clock Module 7.6.2 XTAL This output is an internal oscillator connection to the external crystal. If CLKMOD0 is driven low during reset, XTAL is sampled to determine clocking mode. 7.6.3 CLKOUT This output reflects the internal system clock. 7.6.4 RSTO The RSTO pin is asserted by one of the following: •...
Page 112 Clock Module 7.7.1.1 Synthesizer Control Register (SYNCR) IPSBAR 0x0012_0000 (SYNCR) Access: Supervisor read/write Offset: LOLRE MFD2 MFD1 MFD0 LOCRE RFD2 RFD1 RFD0 Reset LOCEN DISCLK FWKUP — — CLKSRC PLLMODE PLLEN Reset Figure 7-3. Synthesizer Control Register (SYNCR) The reset values of PLLEN and CLKSRC are zero, as the PLL will not be enabled when the device emerges from reset).
Page 113 Clock Module Table 7-4. SYNCR Field Descriptions (continued) Field Description 14–12 Multiplication Factor Divider. Contain the binary value of the divider in the PLL feedback loop. The MFD[2:0] value is the multiplication factor applied to the reference frequency. When MFD[2:0] are changed or the PLL is disabled in stop mode, the PLL loses lock.
Page 114 Clock Module Table 7-4. SYNCR Field Descriptions (continued) Field Description Fast wakeup. Determines when the system clocks are enabled during wakeup from stop mode. FWKUP 0 System clocks enabled only when PLL is locked or operating normally 1 System clocks enabled on wakeup regardless of PLL lock status Note: When FWKUP = 0, if the PLL or oscillator is enabled and unintentionally lost in stop mode, the PLL wakes up in self-clocked mode or reference clock mode depending on the clock that was lost.
Page 115 Clock Module Table 7-5. SYNSR Field Descriptions (continued) Field Description Sticky indication of PLL lock status. LOCKS 0 PLL loss of lock since last system reset or MFD change or currently not locked due to exit from STOP with FWKUP set 1 No unintentional PLL loss of lock since last system reset or MFD change The lock detect function sets the LOCKS bit when the PLL achieves lock after: •...
Page 116 Clock Module IPSBAR 0x0012_0007 (LPDR) Access: Supervisor read/write Offset: — — — — LPD3 LPD2 LPD1 LPD0 Reset: Figure 7-5. Low Power Divider Register 7.7.1.4 Clock Control High Register (CCHR) The Pre-Divider Factor divides down the PLL input clock by 1 (PFD[2:0] = 000) to 8 (PFD[2:0] =111). This allows an external oscillator or crystal of more than 10 MHz to be used with the PLL.
Page 117: Functional Description
Clock Module IPSBAR 0x0011_000C (RTCDF) Access: Supervisor read/write Offset: RTCDF (31:24) Reset RTCDF (23:16) Reset RTCDF 15:8) Reset RTCDF (7:0) Reset Figure 7-7. Real Time Clock Divide Register Functional Description This section provides a functional description of the clock module. 7.8.1 Clock Operation During Reset The PLL is always disabled as the part emerges from Reset, with a default configuration of external crystal...
Page 118 Clock Module When programming the PLL, do not exceed the maximum system clock frequency listed in the electrical specifications. Use this procedure to accommodate the frequency overshoot that occurs when the MFD bits are changed: 1. Determine the appropriate value for the MFD and RFD fields in the SYNCR. The amount of jitter in the system clocks can be minimized by selecting the maximum MFD factor that can be paired with an RFD factor to provide the required frequency.
Page 119 Clock Module 7.8.3.1 Phase and Frequency Detector (PFD) The PFD is a dual-latch phase-frequency detector. It compares both the phase and frequency of the reference and feedback clocks. The reference clock comes from either the crystal oscillator or an external clock source.
Page 120 Clock Module In 1:1 PLL mode, the MFD is bypassed, and the effective multiplication factor is one. 7.8.3.5 PLL Lock Detection The lock detect logic monitors the reference frequency and the PLL feedback frequency to determine when frequency lock is achieved. Phase lock is inferred by the frequency relationship, but is not guaranteed. The LOCK flag in the SYNSR reflects the PLL lock status.
Page 121 Clock Module 7.8.3.6 PLL Loss of Lock Conditions Once the PLL acquires lock after reset, the LOCK and LOCKS flags are set. If the MFD is changed, or if an unexpected loss of lock condition occurs, the LOCK and LOCKS flags are negated. While the PLL is in the non-locked condition, the system clocks continue to be sourced from the PLL as the PLL attempts to relock.
Page 122 Clock Module Table 7-7 shows, if the reference fails, the PLL goes out of lock and into self-clocked mode (SCM). The PLL remains in SCM until the next reset. When the PLL is operating in SCM, the system frequency depends on the value in the RFD field. The SCM system frequency stated in electrical specifications assumes that the RFD has been programmed to binary 000.
Page 123 Clock Module Table 7-8. Stop Mode Operation (continued) Expected MODE PLL Action MODE Comments Action at During Stop Stop Off Off 1 Lose lock, Regain clocks, but SCM–> 0–>‘LK 0–>1 1–>‘LC Block LOCS and f.b. clock, don’t regain lock unstable LOCKS until reference clock and lock...
Page 124 Clock Module Table 7-8. Stop Mode Operation (continued) Expected MODE PLL Action MODE Comments Action at During Stop Stop On On 1 — — ‘LK ‘LC Lose lock Unstable 0–>1 ‘LC Lose lock, regain ‘LC Lose clock Stuck — — —...
Page 125 Clock Module Table 7-8. Stop Mode Operation (continued) Expected MODE PLL Action MODE Comments Action at During Stop Stop On On 0 — — ‘LK ‘LC Lose reference Wakeup without clock lock Lose f.b. clock Wakeup without lock Lose lock Stuck —...
Page 126 Clock Module Table 7-8. Stop Mode Operation (continued) Expected MODE PLL Action MODE Comments Action at During Stop Stop — — Lose reference Stuck — — — clock Off X Regain SCM Wakeup without disabled lock Off X Regain SCM disabled On On 0 —...
Page 127: Real Time Clock
Chapter 8 Real Time Clock Introduction This section discusses how to operate and program the real-time clock (RTC) module that maintains the system clock, provides stopwatch, alarm, and interrupt functions, and supports the following features. 8.1.1 Overview Figure 8-1 is a block diagram of the functional organization of the Real Time Clock (RTC) block, it consists of the following blocks: •...
Page 128: Memory Map/Register Definition
Real Time Clock 8.1.2 Features The RTC module includes the following features: • Full clock—days, hours, minutes, seconds • Minute countdown timer with interrupt • Programmable daily alarm with interrupt • Once-per-day, once-per-hour, once-per-minute, and once-per-second interrupts 8.1.3 Modes of Operation The incoming 1 Hz signal is used to increment the seconds, minutes, hours, and days TOD counters.
Page 129 Memory Map/Register Definition Table 8-1. RTC Module Register Memory Map (continued) $BASE+0x10 RTC Control Register(RCCTL) read/write $BASE+0x14 RTC Interrupt Status Register(RTCISR) read/write $BASE+0x18 RTC Interrupt Enable Register(RTCIENR) read/write $BASE+0x1C Stopwatch Minutes Register(STPWCH) read/write $BASE+0x20 RTC Days Counter Register(DAYS) read/write $BASE+0x24 RTC Seconds Counter Register(ALARM_DAY) read/write 8.2.1...
Page 130 Real Time Clock MINUTES — Minutes setting which indicates the current minutes, can be set to any value between 0 and Table 8-3. Meanings of MINUTES(HOURMIN Register) Values Meanings 000000 current minute is 0 000001 current minute is 1 ....
Page 131 Memory Map/Register Definition $BASE_ADDRESS+0x08 RESET: 0x0000 HOURS MINUTES RESET: 0x0000 = Unimplemented or Reserved Figure 8-4. RTC Hours and Minutes Alarm Register HOURS — Hour setting of the alarm hours, can be set to any value between 0 and 23. Table 8-5.
Page 132 Real Time Clock $BASE_ADDRESS+0x0C RESET: 0x0000 SECONDS RESET: 0x0000 = Unimplemented or Reserved Figure 8-5. RTC Seconds Alarm Register SECONDS—Seconds setting of the alarm seconds, can be set to any value between 0 and 59. Table 8-7. Meanings of SECONDS(ALRM_SEC Register) Values Meanings 000000...
Page 133 Memory Map/Register Definition EN — Enables/Disables the real-time clock. The software reset bit (SWR) has no effect on this bit. Bit description 1 = Enable the real-time clock 0 = Disable the real-time clock XTL — Crystal Selection, selects the proper input crystal frequency. It is important to set these bits correctly or the real-time clock will be inaccurate.
Page 134 Real Time Clock Bit description 1 = A 1-hour interrupt has occurred. 0 = No 1-hour interrupt occurred. 1HZ — 1 Hz Flag, indicates that the second counter has incremented. If enabled, this bit is set on every increment of the second counter of the time-of-day clock. Bit description 1 = A 1 Hz interrupt has occurred.
Page 135 Memory Map/Register Definition $BASE_ADDRESS+0x18 RESET: 0x0000 RESET: 0x0000 = Unimplemented or Reserved Figure 8-8. RTC Interrupt Enable Register HR — Hour Interrupt Enable, Enables/Disables an interrupt whenever the hour counter of the real-time clock increments. Bit description 1 = The 1-hour interrupt is enabled. 0 = The 1-hour interrupt id disabled.
Page 136 Real Time Clock SW — Stopwatch Interrupt Enable, Enables/Disables the stopwatch interrupt. Please note that the stopwatch counts down and remains at decimal -1 until it is reprogrammed. If this bit is enabled with -1 (decimal) in the STPWCH register, an interrupt will be posted on the next minute tick. Bit description 1 = Stopwatch interrupt is enabled.
Page 137 Memory Map/Register Definition $BASE_ADDRESS+0x20 RESET: 0x0000 DAYS RESET: 0x???? = Unimplemented or Reserved Figure 8-10. RTC Days Counter Register DAYS — Day Setting, indicates the current day count, can be set to any values between 0 and 65535. Table 8-10. Meanings of DAYS(DAYR Register) Values Meanings 0x0000...
Page 138: Functional Description
Real Time Clock Table 8-11. Meanings of DAYSAL(DAYALARM Register) Values Meanings 0x0000 current day setting of alarm is 0 0x0001 current day setting of alarm is 1 .... 0xFFFF current day setting of alarm is 65535 Functional Description A 1 Hz signal is supplied to the RTC, which used it to increment the seconds, minutes, hours, and days TOD counters.
Page 139: Initialization/Application Information
Initialization/Application Information register. At each minute, the value in the stopwatch is decremented. When the stopwatch value reaches -1, the interrupt occurs. The value of the register does not change until it is reprogrammed. Note that the actual delay includes the seconds from setting the stopwatch to the next minute tick. Initialization/Application Information 8.4.1 Flow Chart of RTC Operation...
Page 140 Real Time Clock r2,[r1,#0x10] r2,r2,#0x21 r2,[r1,#0x10] ; Software reset and 32k crystal r3,=0x0000 r3,[r1,#0x20] ;DAY r3,=0x00038 r3,[r1,#0x04] ;SECOND r3,=0x173B r3,[r1] ;HR, MIN r3,=0x0001 r3,[r1,#0x24] ;Alarm Day r3,=0x0000 r3,[r1,#0x08] ;Alarm hour, minute r3,=0x01 r3,[r1,#0x0C] ;Alarm seconds r2,[r1,#0x18] ;set ALARM interrupt r2,r2,#0x4 r2,[r1,#0x18] ALARM_STATUS_3 r2,[r1,#0x18]...
Page 141 Chapter 9 Power Management Introduction This chapter explains the low-power operation of the MCF5235. 9.1.1 Features The following features support low-power operation. • Four modes of operation: run, wait, doze, and stop • Ability to shut down most peripherals independently •...
Page 142 Power Management The CRSR, CWCR, and CWSR are described in the System Control Module. They are shown here only to warn against accidental writes to these registers when accessing the LPICR. Table 9-2. IPSBAR Offset [31:24] [23:16] [15:8] [7:0] 0x00_000C PPMRH[63:32] 0x00_0010 Core Reset Status...
Page 143 Power Management IPSBAR 0x00_000C (PPMRH) Access: read/write Offset: Reset Reset CDRNGA CDEPHY CDCFM CDFCAN CDPWM CDGPT Reset CDADC CDPIT1 CDPIT0 CDEPORT CDPORTS Reset Figure 9-1. Peripheral Power Management Register High (PPMRH) Table 9-3. PPMRH Field Descriptions Field Description 31–14 Reserved, should be cleared. Disable clock to the EPHY (Ethernet PHY Module)) CDEPHY 0 EPHY module clock is enabled...
Page 144 Power Management Table 9-3. PPMRH Field Descriptions (continued) Field Description Disable clock to the ADC module. CDADC 0 ADC module clock is enabled 1 ADC module clock is disabled 6–5 Reserved, should be cleared. Disable clock to the PIT1 module. CDPIT1 0 PIT0 module clock is enabled 1 PIT1 module clock is disabled...
Page 145 Power Management Table 9-4. PPMRL Field Descriptions Field Description 31–22 Reserved, should be cleared. Disable clock to the FEC (Fast Ethernet Controller) module. CDFEC0 FEC module clock is enabled FEC module clock is disabled 20–19 Reserved, should be cleared. Disable clock to the INTC1 module. CDINTC0 INTC1 module clock is enabled INTC1 module clock is disabled...
Page 146 Power Management Table 9-4. PPMRL Field Descriptions (continued) Field Description Disable clock to the UART0 module. CDUART0 UART0 module clock is enabled UART0 module clock is disabled Disable clock to the DMA module. CDDMA DMA module clock is enabled DMA module clock is disabled 3–2 Reserved, should be cleared.
Page 147 Power Management NOTE Only a fixed (external) interrupt can bring a device out of stop mode. To exit from other low-power modes, such as doze or wait, either fixed or programmable interrupts may be used; however, the module generating the interrupt must be enabled in that particular low-power mode.
Page 148 Power Management 9.2.3 Peripheral Power Management Set Register (PPMRS) The PPMRS register provides a simple memory-mapped mechanism to set a given bit in the PPMRx registers to disable the clock for a given IPS module without the need to perform a read-modify-write on the PPMR.
Page 149 Power Management Table 9-8. PPMRC Field Descriptions Field Description Reserved, should be cleared. 6–0 Clear Module Clock Disable PPMRC 0–63 Clear corresponding bit in PPMRx, enabling the module clock 64–127 Clear all bits in PPMRx, enabling all the module clocks 9.2.4.1 Low-Power Control Register (LPCR) The LPCR controls chip operation and module operation during low-power modes.
Page 150: Power Management
Power Management IPS Bus Timeout Monitor The IPS controller implements a bus timeout monitor to insure that every IPS bus cycle is properly terminated within a programmed period of time. The monitor continually checks for termination of each IPS bus cycle and completes the cycle if there is no response when the programmed monitor cycle count is reached.
Page 151: Functional Description
Power Management Functional Description The functions and characteristics of the low-power modes, and how each module is affected by, or affects these modes are discussed in this section. 9.4.1 Low-Power Modes The system enters a low-power mode by executing a STOP instruction. Which mode the device actually enters (either stop, wait, or doze) depends on what is programmed in LPCR[LPMD].
Page 152 Power Management 9.4.1.4 Stop Mode Stop mode affects the CPU in the same manner as the wait and doze modes, except that all clocks to the system are stopped and the peripherals cease operation. Stop mode must be entered in a controlled manner to ensure that any current operation is properly terminated.
Page 153 Power Management generated when the DCR[INT] bit is set, and an interrupt is generated when either the CE, BES or BED bit in the DSR becomes set. The DMA controller is stopped in stop mode and thus cannot cause an exit from this low-power mode. 9.4.2.6 UART Modules (UART0, UART1, and UART2) In wait and doze modes, the UART may generate an interrupt to exit the low-power modes.
Page 154 Power Management reference request interrupt enable (ORRI) bit of DTMR is set and the DTXMR[DMAEN] bit is cleared, an interrupt is issued when the timer counter reaches the reference value. DMA timer operation is disabled in stop mode, but the DMA timer is unaffected by either the wait or doze modes and may generate an interrupt to exit these modes.
Page 155 Power Management 9.4.2.14 Clock Module In wait and doze modes, the clocks to the CPU, Flash, and SRAM will be stopped and the system clocks to the peripherals are enabled. Each module may disable the module clocks locally at the module level. In stop mode, all clocks to the system will be stopped.
Page 156 Power Management Exiting stop mode is done in one of the following ways: • Reset the FlexCAN (either by hard reset or by asserting the SOFT_RST bit in MCR). • Clearing the STOP bit in the MCR. • Self-wake mechanism. If the SELF-WAKE bit in the MCR is set at the time the FlexCAN enters stop mode, then upon detection of recessive to dominant transition on the CAN bus, the FlexCAN resets the STOP bit in the MCR and resumes its clocks.
Page 157 Power Management The auto-power save mode in the FlexCAN is intended to enable NORMAL operation with optimized power saving. Upon setting the AUTO POWER SAVE bit in the MCR register, the FlexCAN looks for a set of conditions in which there is no need for clocks to run. If all these conditions are met, then the FlexCAN stops its clocks, thus saving power.
Page 158 Power Management Table 9-11. CPU and Peripherals in Low-Power Modes Peripheral Status / Wakeup Capability Module Wait Mode Doze Mode Stop Mode Stopped Stopped Stopped SRAM Stopped Stopped Stopped Flash Stopped Stopped Stopped System Control Module Enabled Enabled Stopped Random Number Generator Accelerator Enabled Stopped Stopped...
Page 159 Power Management MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor Preliminary 9-19...
Page 160 Power Management MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 0 9-20 Preliminary Freescale Semiconductor...
Page 161: Reset Controller Module
Chapter 10 Reset Controller Module 10.1 Introduction The reset controller is provided to determine the cause of reset, assert the appropriate reset signals to the system, and keep a history of what caused the reset. The low voltage detection module, which generates low-voltage detect (LVD) interrupts and resets, is implemented within the reset controller module.
Page 162: Signals
Reset Controller Module RSTI Power-On Reset RSTO Reset Loss of Clock Controller Loss of Lock To Internal Resets Software Reset Detect Figure 10-1. Reset Controller Block Diagram 10.4 Signals Table 10-1 provides a summary of the reset controller signal properties. The signals are described in the following sections.
Page 163 Reset Controller Module Table 10-2 for the memory map and the following paragraphs for a description of the registers. Table 10-2. Reset Controller Memory Map IPSBAR Width Register Access Reset Value Section/Page Offset (bits) 0x11_0000 Reset Control Register (RCR) 0x05 10.5.1/10-3 0x11_0001 Reset Status Register (RSR)
Page 164 Reset Controller Module Table 10-3. RCR Field Descriptions (continued) Field Description LVD interrupt enable. Controls the LVD interrupt if LVDE is set. This bit has no effect if the LVDE bit is a logic 0. LVDIE 1 LVD interrupt enabled 0 LVD interrupt disabled LVD reset enable.
Page 165: Functional Description
Reset Controller Module Table 10-4. RSR Field Descriptions (continued) Field Description Reserved, should be cleared. — Power-on reset flag. Indicates that the last reset was caused by a power-on reset. 1 Last reset caused by power-on reset 0 Last reset not caused by power-on reset External reset flag.
Page 166 Reset Controller Module Asynchronous reset sources usually indicate a catastrophic failure. Therefore, the reset control logic does not wait for the current bus cycle to complete. Reset is asserted immediately to the system. 10.6.1.1 Power-On Reset At power up, the reset controller asserts RSTO. RSTO continues to be asserted until V has reached a minimum acceptable level and, if PLL clock mode is selected, until the PLL achieves phase lock.
Page 167 Reset Controller Module POR OR LVD LOSS OF CLOCK? LOSS OF LOCK? ENABLE BUS MONITOR RSTI PIN OR WD TIMEOUT OR SW RESET? BUS CYCLE COMPLETE? ASSERT RSTO AND LATCH RESET STATUS ASSERT RSTO AND LATCH RESET STATUS RSTI NEGATED? PLL MODE? PLL LOCKED? WAIT 512 CLKOUT CYCLES...
Page 168 Reset Controller Module 10.6.2.1 Synchronous Reset Requests In this discussion, the references in parentheses refer to the state numbers in Figure 10-4. All cycle counts given are approximate. If the external RSTI signal is asserted by an external device for at least four rising CLKOUT edges (3) and if software requests a reset, the reset control logic latches the reset request internally and enables the bus monitor (5).
Page 169 Reset Controller Module If a loss-of-clock or loss-of-lock condition is detected during the 512 cycle wait, the reset sequence continues after a PLL lock (9, 9A). 10.6.3.2 Reset Status Flags For a POR reset, the POR and LVD bits in the RSR are set, and the SOFT, WDR, EXT, LOC, and LOL bits are cleared even if another type of reset condition is detected during the reset sequence for the POR.
Page 170 Reset Controller Module MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 0 10-10 Freescale Semiconductor Preliminary...
Page 171: Static Ram (Sram)
Chapter 11 Static RAM (SRAM) 11.1 Introduction This chapter describes the on-chip static RAM (SRAM) implementation, including general operations, configuration, and initialization. It also provides information and examples showing how to minimize power consumption when using the SRAM. 11.1.1 Features The major features include the following: •...
Page 172 Static RAM (SRAM) Table 11-1. SRAM Programming Model CPU Space Width Written Register Access Reset Value Section/Page (Rc) (bits) w/ MOVEC Supervisor Access Only Registers 0xC05 RAM Base Address Register (RAMBAR) 0x0000_0000 11.2.1/11-2 11.2.1 SRAM Base Address Register (RAMBAR) The configuration information in the SRAM base address register (RAMBAR) controls the operation of the SRAM module.
Page 173: Initialization/Application Information
Static RAM (SRAM) Table 11-2. RAMBAR Field Descriptions (continued) Field Description 11–10 Priority bit. PRIU determines if or CPU has priority in the upper K bank of memory. PRIL determines if or PRIU CPU has priority in the lower K bank of memory. If a bit is set, the CPU has priority. If a bit is cleared, has PRIL priority.
Page 174 Static RAM (SRAM) 3. After the data has been loaded into the SRAM, it may be appropriate to load a revised value into the RAMBAR with a new set of attributes. These attributes consist of the write-protect and address space mask fields. The ColdFire processor or an external debugger using the debug module can perform these initialization functions.
Page 175: Chip Configuration Module (Ccm)
Chapter 12 Chip Configuration Module (CCM) 12.1 Introduction This chapter describes the various operating configurations of the device. It provides a description of signals used by the CCM and a programming model. 12.1.1 Block Diagram The chip configuration module (CCM) controls the chip configuration and mode of operation for the MCF52235.
Page 176: External Signal Descriptions
Chip Configuration Module (CCM) 12.2 External Signal Descriptions Table 12-1 provides an overview of the CCM signals. Table 12-1. Signal Properties Name Function Reset State RCON Reset configuration select Internal weak pull-up device 12.2.1 RCON If the external RCON pin is asserted during reset, then various chip functions, including the reset configuration pin functions after reset, are configured according to the levels driven onto the external data pins (see Section 12.4, “Functional...
Page 177: Memory Map/Register Definition
Chip Configuration Module (CCM) 12.3.2 Memory Map Table 12-3. Chip Configuration Module Memory Map IPSBAR Width Register Access Reset Value Section/Page Offset (bits) Supervisor Mode Access Only 0x11_0004 Chip Configuration Register (CCR) 0x0001 8.3.3.1/8-3 0x11_0007 Low-Power Control Register (LPCR) 0x00 7.2.4.1/7-12 0x11_0008 Reset Configuration Register (RCON)
Page 178 Chip Configuration Module (CCM) Table 12-4. CCR Field Descriptions Field Description 1– Reserved, should be cleared. — TSIZ[1:0] enable. This read/write bit enables the TSIZ[1:0] function of the external pins. SZEN 0 TSIZ[1:0] function disabled. 1 TSIZ[1:0] function enabled. PST[3:0]/DDATA[3:0] enable. This read/write bit enables the Processor Status (PST) and Debug Data (DDATA) PSTEN functions of the external pins.
Page 179: Functional Description
Chip Configuration Module (CCM) Table 12-5. RCON Field Descriptions Field Description 15–6 Reserved, should be cleared. — Pad driver load. Reflects the default pad driver strength configuration. RLOAD 0 artial drive strength (This is the default value.) 1 ull drive strength 4–1 Reserved, should be cleared.
Page 180: Reset
Chip Configuration Module (CCM) 12.4.1 Reset Configuration During reset, the pins for the reset override functions are immediately configured to known states. Table 12-7 shows the states of the external pins while in reset. Table 12-7. Reset Configuration Pin States During Reset Output Input Function...
Page 181: System Control Module (Scm)
Chapter 13 System Control Module (SCM) 13.1 Introduction This section details the functionality of the system control module (SCM) that provides the programming model for the system access control unit (SACU), system bus arbiter, 32-bit core watchdog timer (CWT), and system control registers and logic. Specifically, the system control includes the internal peripheral system (IPS) base address register (IPSBAR), the processor’s dual-port RAM base address register (RAMBAR), and system control registers that include the core watchdog timer control.
Page 182: Memory Map And Register Definition
System Control Module (SCM) • System access control unit (SACU) programming model — Master privilege register (MPR) — Peripheral access control registers (PACRs) — Grouped peripheral access control registers (GPACR0, GPACR1) 13.4 Memory Map and Register Definition The memory map for the SCM registers is shown in Table 13-1.
Page 183: Register Descriptions
System Control Module (SCM) Table 13-1. SCM Register Map (continued) IPSBAR Width Register Access Reset Value Section/Page Offset (bits) 0x00_002E Peripheral Access Control Register (PACR8) 0x00 13.7.3.2/13-17 0x00_0030 GPACR0 Register 0x00 13.7.3.3/13-18 0x00_0031 GPACR1 Register 0x00 13.7.3.3/13-18 Addresses not assigned to a register and undefined register bits are reserved for expansion. The PPMRH, LPICR, PMRL, PPMRS, PPMRC, and IPSBMT are described in Chapter 7, “Power Management.”...
Page 184 System Control Module (SCM) NOTE Accessing reserved IPSBAR memory space could result in an unterminated bus cycle that causes the core to hang. Only a hard reset will allow the core to recover from this state. Therefore, all bus accesses to IPSBAR space should fall within a module’s memory map space.
Page 185 System Control Module (SCM) system-level performance. For example, a DMA channel in a typical double-buffer application (also known as a ping-pong scheme) may load data into one portion of the dual-ported SRAM while the processor is manipulating data in another portion of the SRAM. Once the processor completes the data calculations, it begins processing the just-loaded buffer while the DMA moves out the just-calculated data from the other buffer, and reloads the next data block into the just-freed memory region.
Page 186 System Control Module (SCM) Table 13-4. RAMBAR Field Description Field Description 31–16 Base address. Defines the memory module's base address on a 64-Kbyte boundary corresponding to the physical array location within the 4 Gbyte address space supported by ColdFire. 15–10 Reserved, should be cleared. Back door enable.
Page 187 System Control Module (SCM) The SRAM modules are configured through the RAMBAR shown in Figure 13-2. • RAMBAR specifies the base address of the SRAM. • All undefined bits are reserved. These bits are ignored during writes to the RAMBAR and return zeros when read.
Page 188 System Control Module (SCM) Table 13-5. CRSR Field Descriptions Field Description External reset. 1 An external device driving RSTI caused the last reset. Assertion of reset by an external device causes the processor core to initiate reset exception processing. All registers are forced to their initial state. 6–0 Reserved, should read as 0.
Page 189 System Control Module (SCM) IPSBAR 0x011 (CWCR) Access: read/write Offset: CWRI CWT[2:0] CWTA CWTAVAL CWTIC Reset: Figure 13-5. Core Watchdog Control Register (CWCR) Table 13-6. CWCR Field Description Field Description Core watchdog enable. 0 SWT disabled. 1 SWT enabled. Core watchdog interrupt select. CWRI 0 If a time-out occurs, the CWT generates an interrupt to the processor core.
Page 190 System Control Module (SCM) Table 13-6. CWCR Field Description (continued) Core watchdog transfer acknowledge valid. CWTAVA 0 CWTA Transfer Acknowledge has not occurred. 1 CWTA Transfer Acknowledge has occurred. Write a 1 to clear this flag bit. Core watchdog timer interrupt flag. CWTIF 0 CWT interrupt has not occurred 1 CWT interrupt has occurred.
Page 191: Internal Bus Arbitration
System Control Module (SCM) 13.6 Internal Bus Arbitration The internal bus arbitration is performed by the on-chip bus arbiter, which containing the arbitration logic that controls which of up to four MBus masters (M0–M3 in Figure 13-7) has access to the external buses. The function of the arbitration logic is described in this section.
Page 192 System Control Module (SCM) • The anti-lock-out logic for the fixed priority scheme forces the arbitration algorithm to round-robin if any requester has been held for longer than a specified cycle count. 13.6.2 Arbitration Algorithms There are two modes of arbitration: fixed and round-robin. This section discusses the differences between them.
Page 193 System Control Module (SCM) IPSBAR 0x01C (MPARK) Access: read/write Offset: M2_P BCR2 M2_PRTY M0_PRTY M1_PRTY 4BIT Reset TIME PRKL FIXED LCKOUT_TIME Reset Figure 13-8. Default Bus Master Park Register (MPARK) Table 13-7. MPARK Field Description Field Description 31–26 Reserved, should be cleared. DMA bandwidth control enable M2_P_EN 0 disable the use of the DMA's bandwidth control to elevate the priority of its bus requests.
Page 194: System Access Control Unit (Sacu)
System Control Module (SCM) Table 13-7. MPARK Field Description (continued) Field Description Timeout Enable TIMEOUT 0 disable count for when a master is locked out by other masters. 1 enable count for when a master is locked out by other masters and allow access when LCKOUT_TIME is reached.
Page 195: Features
System Control Module (SCM) 13.7.2 Features Each bus transfer can be classified by its privilege level and the reference type. The complete set of access types includes the following: • Supervisor instruction fetch • Supervisor operand read • Supervisor operand write •...
Page 196 System Control Module (SCM) Table 13-8. SACU Register Memory Map IPSBAR [31:28] [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] Offset 0x020 PPMRS PPMRC IPSBMT 0x024 PACR0 PACR1 PACR2 PACR3 0x028 PACR4 PACR5 PACR6 PACR7 0x02c PACR8 — — — 0x030 GPACR0 GPACR1 —...
Page 197 System Control Module (SCM) 13.7.3.2 Peripheral Access Control Registers (PACR0–PACR8) Access to several on-chip peripherals is controlled by shared peripheral access control registers. A single PACR defines the access level for each of the two modules. These modules only support operand reads and writes.
Page 198 System Control Module (SCM) Table 13-12. Peripheral Access Control Registers (PACRs) Modules Controlled IPSBAR Offset Name ACCESS_CTRL1 ACCESS_CTRL0 0x024 PACR0 — 0x025 PACR1 — 0x026 PACR2 UART0 UART1 0x027 PACR3 UART2 — 0x028 PACR4 QSPI 0x029 — — — 0x02a PACR6 DTIM0 DTIM1...
Page 199 System Control Module (SCM) Table 13-13. Grouped Peripheral Access Control Register (GPACR) Field Descriptions Field Description This bit, once set, prevents subsequent writes to the GPACR. Any attempted write to the GPACR generates LOCK an error termination and the contents of the register are not affected. Only a system reset clears this flag. 6–4 Reserved, should be cleared.
Page 200 System Control Module (SCM) Table 13-15. GPACR Address Space Space Protected Register Modules Protected (IPSBAR Offset) GPACR0 0x0000_0000– Ports, CCM, PMM, Reset controller, Clock, 0x03FF_FFFF EPORT, WDOG, PIT0–PIT3, QADC, GPTA, GPTB, FlexCAN, CFM (Control) GPACR1 0x0400_0000– CFM (Flash module’s backdoor access for 0x07FF_FFFF programming or access by a bus master other than the core)
Page 201 Chapter 14 General Purpose I/O Module 14.1 Introduction Many of the pins associated with the external interface may be used for several different functions. When not used for their primary function, many of the pins may be used as general-purpose digital I/O pins. In some cases, the pin function is set by the operating mode, and the alternate pin functions are not supported.
Page 202 General Purpose I/O Module CTS2 / PUC[3] DDATA[3:0] / PDD[7:4] RTS2 / PUC[2] PORT UC PORT DD RXD2 / PUC[1] TXD2 / PUC[0] PST[3:0] / PDD[3:0] CANTX / PAS[3] / SYNCB CTS1 / PUB[3] / SYNCA / RXD2 RTS1 / PUB[2] / SYNCB / TXD2 CANRX / PAS[2] / SYNCA RXD1 / PUB[1] PORT UB...
Page 203 General Purpose I/O Module 14.3 Features The MCF52235 ports includes these distinctive features: • Control of primary function use on all ports • Digital I/O support for all ports; registers for: — Storing output pin data — Controlling pin data direction —...
Page 204 General Purpose I/O Module 14.5 Memory Map/Register Definition 14.5.1 Ports Memory Map MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 0 14-4 Freescale Semiconductor Preliminary...
Page 205 General Purpose I/O Module Table 14-1. Ports Module Memory Map 31–24 23–16 15–8 7–0 Offset Access Port Output Data Registers $0000 Reserved $0004 Reserved $0008 PORTNQ Reserved PORTAN PORTAS $000C PORTQS Reserved PORTTA PORTTC $0010 PORTTD PORTUA PORTUB PORTUC $0014 PORTDD PORTLD PORTGP...
Page 206: Register Descriptions
General Purpose I/O Module 14.6 Register Descriptions 14.6.1 Port Output Data Registers (PORTn) The PORTn registers store the data to be driven on the corresponding port n pins when the pins are configured for digital output. The PORTn registers with a full 8-bit implementation are shown in Figure 11-2.
Page 207 General Purpose I/O Module IPSBAR Base + $000C (PORTQS) Access: User read/write Offset: Base + $0015 (PORTLD) PORTn6 PORTn5 PORTn4 PORTn3 PORTn2 PORTn1 PORTn0 Reset: Figure 14-4. — Port Output Data Registers [6:0] IPSBAR Base + $0008 (PORTNQ) Access: User read/write Offset: PORTn7 PORTn6...
Page 208 General Purpose I/O Module IPSBAR Base + $0023 (DDRAS) Access: User read/write Offset: Base + $0026 (DDRTA) Base + $0027 (DDRTC) Base + $0028 (DDRTD) Base + $0029 (DDRUA) Base + $002A (DDRUB) Base + $002B (DDRUC) DDRn3 DDRn2 DDRn1 DDRn0 Reset: Figure 14-7.
Page 209 General Purpose I/O Module Writing 1s to a PORTnP/SETn register sets the corresponding bits in the PORTn register. Writing 0s has no effect. IPSBAR Base + $003A (PORTAN/SETAN) Access: User read/write Offset: Base + $0044 (PORTDD/SETDD) Base + $0046 (PORTGPP/SETGP) PORTnP7 PORTnP6 PORTnP5...
Page 210 General Purpose I/O Module PORTnP/SETn Port n pin data/set data bits. 1 = Port n pin state is 1 (read); set corresponding PORTn bit (write). 0 = Port n pin state is 0 (read). 14.6.4 Port Clear Output Data Registers (CLRn) Writing 0s to a CLRn register clears the corresponding bits in the PORTn register.
Page 211 General Purpose I/O Module IPSBAR Base + $0050 (CLRNQ) Access: User read/write Offset: CLRn7 CLRn6 CLRn5 CLRn4 CLRn3 CLRn2 CLRn1 Reset: Figure 14-17. — Port Clear Output Data Registers [7:1] CLRn Port n clear output data register bits. 1 = Never returned for reads; no effect for writes. 0 = Always returned for reads;...
Page 212 General Purpose I/O Module IPSBAR Base + $0070 (PTDPAR) Access: User read/write Offset: Base + $0073 (PUCPAR) PnPAR3 PnPAR2 PnPAR1 PnPAR0 Reset: Figure 14-20. PnPAR — Port n Pin Assignment Registers Dual [3:0] PnPAR Port n pin assignment register bits. 1 = Pin assumes the primary function for that pin.
Page 213 General Purpose I/O Module IPSBAR Base + $006B (PASPAR) Access: User read/write Offset: Base + $006E (PTAPAR) Base + $006F (PTCPAR) Base + $0071 (PUAPAR) Base + $0072 (PUBPAR) PnPAR3 PnPAR2 PnPAR1 PnPAR0 Reset: Figure 14-23. PnPAR — Port n Pin Assignment Registers Quad [7:0] PnPAR Port n pin assignment register bits.
Page 214 General Purpose I/O Module 14.6.5.4 Pin Drive Strength Register The pin drive strength register is read/write, and each bit resets to logic 0 in single chip mode (MCF52235 default) and logic 1 in EzPort and FAST mode. IPSBAR 0x00_007A (PDSR) Access: User read/write Offset: PDSR47...
Page 215: Ports Interrupts
General Purpose I/O Module Base + $007A (PDSR) Upper 16bits Field PDSR47 PDSR46 PDSR45 PDSR44 PDSR43 PDSR42 PDSR41 PDSR40 Reset Field PDSR39 PDSR38 PDSR37 PDSR36 PDSR35 PDSR34 PDSR33 PDSR32 Reset Each bit resets to logic 0 in Single Chip mode and logic 1 in EzPort/FAST mode. Figure 14-26.
Page 216 General Purpose I/O Module MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 0 14-16 Freescale Semiconductor Preliminary...
Page 217: Interrupt Controller Module
Chapter 15 Interrupt Controller Module This section details the functionality for the MCF52235 interrupt controllers (INTC0, INTC1). The general features of each of the interrupt controller include the following: • 63 interrupt sources per controller — fully-programmable interrupt sources — 7 fixed-level interrupt sources •...
Page 218 Interrupt Controller Module to the beginning of a specific exception service routine. In particular, vectors 64–255 of the exception vector table are reserved for user interrupt service routines. The first 64 exception vectors are reserved for the processor to handle reset, error conditions (access, address), arithmetic faults, system calls, etc. Once the interrupt vector number has been retrieved, the processor continues by creating a stack frame in memory.
Page 219 Interrupt Controller Module Table 15-1. Interrupt Priority Within a Level (continued) Interrupt ICR[2:0] Priority Sources 8–63 8–63 8–63 0 (Lowest) 8–63 The level and priority is fully programmable for all sources except interrupt sources 1–7. Interrupt source 1–7 (from the edgeport module) are fixed at the corresponding level’s midpoint priority. Thus, a maximum of 8 fully-programmable interrupt sources are mapped into a single interrupt level.
Page 220: Memory Map
Interrupt Controller Module if interrupt source 8 is active and acknowledged, then vector_number = if interrupt source 9 is active and acknowledged, then vector_number = if interrupt source 62 is active and acknowledged, then vector_number = 126 The net effect is a fixed mapping between the bit position within the source to the actual interrupt vector number.
Page 221: Register Descriptions
Interrupt Controller Module Table 15-3. Interrupt Controller Memory Map (continued) Module Offset Bits[31:24] Bits[23:16] Bits[15:8] Bits[7:0] IPSBAR + 0x0C40 Reserved ICR01 ICR02 ICR03 IPSBAR + 0x0C44 ICR04 ICR05 ICR06 ICR07 IPSBAR + 0x0C48 ICR08 ICR09 ICR10 ICR11 IPSBAR + 0x0Cx4C ICR12 ICR13 ICR14...
Page 222 Interrupt Controller Module IPRn is a read-only register, so any attempted write to this register is ignored. Bit 0 is not implemented and reads as a zero. IPSBAR 0xC00( (IPRHn) Access: read-only Offset: INT[63:48] Reset INT[47:32] Reset Figure 15-1. Interrupt Pending Register High (IPRHn) Table 15-4.
Page 223 Interrupt Controller Module Table 15-5. IPRLn Field Descriptions Field Description 31–1 Interrupt Pending. Each bit corresponds to an interrupt source. The corresponding IMRLn bit determines whether an interrupt condition can generate an interrupt. At every system clock, the IPRLn samples the signal generated by the interrupting source.
Page 224 Interrupt Controller Module IPSBAR 0xC0C( (IMRLn) Access: read/write Offset: INT_MASK[31:16] Reset INT_MASK[16:1] KALL Reset Figure 15-4. Interrupt Mask Register Low (IMRLn) Table 15-7. IMRLn Field Descriptions Field Description 31–1 Interrupt mask. Each bit corresponds to an interrupt source. The corresponding IMRLn bit determines whether an INT_MASK interrupt condition can generate an interrupt.
Page 225 Interrupt Controller Module or more sources to allow software to self-schedule interrupts by forcing one or more of these bits (1 = force request, 0 = negate request) in the appropriate INTFRCn register. The assertion of an interrupt request via the INTFRCn register is not affected by the interrupt mask register.
Page 226 Interrupt Controller Module Field INTFRCL[31:16] Reset 0000_0000_0000_0000 Field INTFRCL[16:1] — Reset 0000_0000_0000_0000 IPSBAR + 0xC14 Figure 15-7. Interrupt Force Register Low (INTFRCLn) Table 15-9. INTFRCLn Field Descriptions Field Description 31–1 Interrupt force. Allows software generation of interrupts for each possible source for functional or debug purposes. INTFRCL 0 No interrupt forced on corresponding interrupt source 1 Force an interrupt on the corresponding source...
Page 227 Interrupt Controller Module Table 15-10. IRLRn Field Descriptions Field Description 7–1 Interrupt requests. Represents the prioritized active interrupts for each level. 0 There are no active interrupts at this level 1 There is an active interrupt at this level Reserved 15.3.5 Interrupt Acknowledge Level and Priority Register (IACKLPRn) Each time an IACK is performed, the interrupt controller responds with the vector number of the highest...
Page 228 Interrupt Controller Module 15.3.6 Interrupt Control Register (ICRnx) Each ICRnx, where x = 1, 2,..., 63, specifies the interrupt level (1–7) and the priority within the level (0–7). All ICRnx registers can be read, but only ICRn8 to ICRn63 can be written. It is software’s responsibility to program the ICRnx registers with unique and non-overlapping level and priority definitions.
Page 229 Interrupt Controller Module 15.3.6.1 Interrupt Sources Table 15-13 shows the interrupt sources for each interrupt request line on Interrupt Controller 0. Table 15-13. Interrupt Source Assignment For Interrupt Controller 0 Source Module Flag Source Description Flag Clearing Mechanism EPF1 Edge port flag 1 Write EPF1 = 1 EPF2 Edge port flag 2...
Page 230 Interrupt Controller Module Table 15-13. Interrupt Source Assignment For Interrupt Controller 0 (continued) Source Module Flag Source Description Flag Clearing Mechanism X_INTF Transmit frame interrupt Write X_INTF = 1 X_INTB Transmit buffer interrupt Write X_INTB = 1 Transmit FIFO underrun Write UN = 1 Collision retry limit Write RL = 1...
Page 231 Interrupt Controller Module Table 15-13. Interrupt Source Assignment For Interrupt Controller 0 (continued) Source Module Flag Source Description Flag Clearing Mechanism Not used (Reserved) PIT0 PIT interrupt flag Write PIF = 1 or write PMR PIT1 PIT interrupt flag Write PIF = 1 or write PMR Not Used (Reserved) Not Used (Reserved) CBEIF...
Page 232 Interrupt Controller Module Source Module Flag Source Description Flag Clearing Mechanism BUF0I Message Buffer 2 Interrupt Write 1 to BUF2I after reading as 1 BUF1I Message Buffer 3 Interrupt Write 1 to BUF3I after reading as 1 BUF2I Message Buffer 4 Interrupt Write 1 to BUF4I after reading as 1 BUF3I Message Buffer 5 Interrupt...
Page 233 Interrupt Controller Module Source Module Flag Source Description Flag Clearing Mechanism Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used...
Page 234: Low-Power Wakeup Operation
Interrupt Controller Module also loads the level and priority number for the level into the IACKLPR register, where it may be retrieved later. This interrupt controller design also supports the concept of a software IACK. A software IACK allows an interrupt service routine to determine if there are other pending interrupts so that the overhead associated with interrupt exception processing (including machine state save/restore functions) can be minimized.
Page 235 Interrupt Controller Module The interrupt controller provides a special combinatorial logic path to provide a special wake-up signal to exit from the low-power stop mode. This special mode of operation works as follows: 1. LPICR[6:4] is loaded with the mask level that will be specified while the core is in stop mode. LPICR[7] must be set to enable this mode of operation.
Page 236 Interrupt Controller Module MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 0 15-20 Freescale Semiconductor Preliminary...
Page 237: Edge Port Module (Eport)
Chapter 16 Edge Port Module (EPORT) 16.1 Introduction Although this device has two edge port modules, the description included herein treats each module as a single entity. Pay particular attention to the note below, as the two modules are not completely identical. Specifically, edge port module 0 has seven interrupt inputs while module 1 contains eight.
Page 238: Low-Power Mode Operation
Edge Port Module (EPORT) NOTE The GPIO module must be configured to enable the peripheral function of the appropriate pins (refer to Chapter 13, “General Purpose I/O Module”) prior to configuring the edge port module. 16.2 Low-Power Mode Operation This section describes the operation of the EPORT module in low-power modes. For more information on low-power modes, see Chapter 8, “Power Management.”...
Page 239: Memory Map/Register Definition
Edge Port Module (EPORT) 16.4 Memory Map/Register Definition This subsection describes the memory map and register structure. Refer to Table 16-2 for a description of the EPORT memory map.EPORT0 has an IPSBAR offset base address of 0x0013_0000 while EPORT1 has an IPSBAR offset of 0x0014_0000. Table 16-2.
Page 240 Edge Port Module (EPORT) Table 16-3. EPPAR Field Descriptions Field Description 15–2 EPORT pin assignment select fields. The read/write EPPAn fields configure EPORT pins for level detection and rising EPPAn and/or falling edge detection. Pins configured as level-sensitive are active-low (logic 0 on the external pin represents a valid interrupt request). Level-sensitive interrupt inputs are not latched.
Page 241 Edge Port Module (EPORT) Offset 0x13_0003 (EPIER0) Access: User read/write Address: 0x14_0003 (EPIER1) EPIE7 EPIE6 EPIE5 EPIE4 EPIE3 EPIE2 EPIE1 Reset: Figure 16-4. EPORT Port Interrupt Enable Register (EPIER) Table 16-5. EPIER Field Descriptions Field Description 7–1 Edge port interrupt enable bits enable EPORT interrupt requests. If a bit in EPIER is set, EPORT generates an EPIEn interrupt request when: •...
Page 242 Edge Port Module (EPORT) Offset 0x13_0005 (EPPDR0) Access: User read-only Address: 0x14_0005 (EPPDR1) EPPD7 EPPD6 EPPD5 EPPD4 EPPD3 EPPD2 EPPD1 Reset: [IRQ7] [IRQ6] [IRQ5] [IRQ4] [IRQ3] [IRQ2] [IRQ1] Figure 16-6. EPORT Port Pin Data Register (EPPDR) Table 16-7. EPPDR Field Descriptions Field Description 7–1...
Page 243: Coldfire Flash Module (Cfm)
Chapter 17 ColdFire Flash Module (CFM) 17.1 Introduction 17.1.1 Overview The ColdFire Flash Module (CFM) is a non-volatile memory (NVM) module for integration with a CPU. The CFM provides 256 Kbytes of 32-bit Flash memory serving as electrically erasable and programmable, non-volatile memory.
Page 244 ColdFire Flash Module (CFM) COMMON FLASH BUS EVEN COMMON FLASH BUS INTERFACE EVEN BLOCK ODD BLOCK ARRAY 0 ARRAY 1 ARRAY 2 ARRAY 3 FLASH MEMORY CONTROLLER FLASH COMMAND CONTROLLER INTERNAL FLASH BUS INTERFACE INTERNAL FLASH BUS Figure 17-1. CFM Block Diagram 17.1.2 Features •...
Page 245: External Signal Description
ColdFire Flash Module (CFM) • Protection scheme to prevent accidental program or erase of Flash memory • Access restriction control for supervisor/user and data/instruction operations • Security feature to prevent unauthorized access to the Flash memory 17.2 External Signal Description The CFM contains no signals that connect off-chip for the end customer.
Page 246 ColdFire Flash Module (CFM) Table 17-1. CFM Configuration Field Address Offset Size Factory Description (from PROGRAM_ARRAY_BASE) (bytes) Default $0400 - $0407 Backdoor Comparison Key $FFFF_FFFF_FFFF_FFFF $0408 - $040B Flash Protection Bytes $FFFF_FFFF (see Section 17.3.2.4, “CFMPROT — CFM Protection Register”) $040C - $040F Flash SUPV Access Bytes $FFFF_FFFF...
Page 247 ColdFire Flash Module (CFM) 17.3.2 Register Descriptions 17.3.2.1 CFMMCR — CFM Module Configuration Register The CFMMCR register is used to configure and control the operation of the internal bus interface. IPSBAR 0x0000 (CFMMCR) Access: User read/write Offset: LOCK PVIE AEIE CBEI CCIE KEYA Reset Figure 17-3.
Page 248 ColdFire Flash Module (CFM) Table 17-3. CFMMCR Field Descriptions (continued) Field Description Enable security key writing KEYACC The KEYACC bit is readable and only writable if the KEYEN bits in the CFMSEC register are set to enable backdoor key access. 1 = Writes to CFM Flash memory are interpreted as keys to release security.
Page 249 ColdFire Flash Module (CFM) IPSBAR 0x0008 (CFMSEC) Access: User read/write Offset: R KEYEN SECSTAT Reset Reset Figure 17-5. CFM Security Register (CFMSEC) Reset state loaded from Flash configuration field during reset. Reset state determined by security state of CFM. CFMSEC register bits [31:30,15:0] are readable, while remaining bits read 0 and all bits are not writable. Table 17-5.
Page 250 ColdFire Flash Module (CFM) The CFM Flash security operation is described in Section 17.4.3, “Flash Security Operation. 17.3.2.4 CFMPROT — CFM Protection Register The CFMPROT register defines which Flash logical sectors are protected against program and erase operations. IPSBAR 0x0010 (CFMPROT) Access: User read/write Offset: PROTECT...
Page 251 ColdFire Flash Module (CFM) PROTECT[31:0] — (PROGRAM_ARRAY_BASE + $0003_FFFF) SECTOR 31 PROTECT[31] 8kBytes (PROGRAM_ARRAY_BASE + $0003_E000) • • • Flash Logical Sectors - (PROGRAM_ARRAY_BASE + $0002_2000) protection defined by CFMPROT SECTOR 16 8kBytes (PROGRAM_ARRAY_BASE + $0002_0000) SECTOR 15 8kBytes (PROGRAM_ARRAY_BASE + $0001_E000) •...
Page 252 ColdFire Flash Module (CFM) with the desired value. Each Flash logical sector may be mapped into supervisor or unrestricted address space (see Figure 17-7 for details on Flash sector mapping). Table 17-8. Field Description 31 - 0 Flash address space assignment for supervisor/user access SUPV SUPV[M] = 1: Flash logical sector M is placed in supervisor address space.
Page 253 ColdFire Flash Module (CFM) 17.3.2.7 CFMUSTAT — CFM User Status Register The CFMUSTAT register defines the Flash command controller status and Flash memory access, protection and verify status. 0x0020 (CFMUSTAT) IPSBAR Access: User read/write Offset: CCIF CBEIF PVIOL ACCERR BLANK Reset: Figure 17-10.
Page 254 ColdFire Flash Module (CFM) Table 17-10. Field Description Access error ACCERR The ACCERR flag, set by the Flash command controller, indicates an illegal access was made to the Flash memory or registers caused by an illegal command write sequence. The ACCERR flag is cleared by writing a 1 to the ACCERR flag.
Page 255 ColdFire Flash Module (CFM) Table 17-12. CFM Flash Memory Commands CMD[6:0] Description Blank Check Page Erase Verify Word Program Page Erase Mass Erase 17.3.2.9 CFMCLKSEL — CFM Clock Select Register The CFMCLKSEL register reflects the factory setting for read access latency from the system bus to the Flash block.
Page 256: Functional Description
ColdFire Flash Module (CFM) 17.4 Functional Description 17.4.1 General The following modes and operations are described in the following sections: 1. Flash normal mode (Section 17.4.2, “Flash Normal Mode”) a) Read operation (Section 17.4.2.1, “Read Operation”) b) Write operation (Section 17.4.2.2, “Write Operation”) c) Program, erase, and verify operations (Section 17.4.2.3, “Program, Erase, and Verify...
Page 257 ColdFire Flash Module (CFM) • How to write the CFMCLKD register • Command write sequences used to program, erase, and verify the Flash memory • Valid Flash commands • Errors resulting from illegal command write sequences to the Flash memory 17.4.2.3.1 Writing the CFMCLKD Register Prior to issuing any command, it is first necessary to write the CFMCLKD register to divide the input clock...
Page 258 ColdFire Flash Module (CFM) Before starting a command write sequence, the ACCERR and PVIOL flags in the CFMUSTAT register must be clear and the CBEIF flag should be tested to determine the state of the address, data, and command buffers. If the CBEIF flag is set, indicating the buffers are empty, a new command write sequence can be executed.
Page 259 ColdFire Flash Module (CFM) Blank Check The blank check operation will verify that all Flash memory addresses in the CFM are erased. An example flow to execute the blank check command is shown in Figure 17-13. The blank check command write sequence is as follows: 1.
Page 260 ColdFire Flash Module (CFM) START Read: Register CFMCLKD Clock Register Written DIVLD Check Set? Write: Register CFMCLKD Read: Register CFMUSTAT Address, Data, CBEIF Command Set? Buffer Empty Check Access Error and Write: Register CFMUSTAT ACCERR/PVIOL Protection Violation Clear bit ACCERR/PVIOL $30 Set? Check Write: Array Address...
Page 261 ColdFire Flash Module (CFM) Page Erase Verify The page erase verify operation will verify that all memory addresses in a Flash logical page are erased. An example flow to execute the page erase verify operation is shown in Figure 17-14. The page erase verify command write sequence is as follows: 1.
Page 262 ColdFire Flash Module (CFM) START Read: Register CFMCLKD Clock Register Written DIVLD Check Set? Write: Register CFMCLKD Read: Register CFMUSTAT Address, Data, Command CBEIF Set? Buffer Empty Check Access Error and Write: Register CFMUSTAT ACCERR/PVIOL Protection Violation Clear bit ACCERR/PVIOL $30 Set? Check Write: Logical Page Address...
Page 263 ColdFire Flash Module (CFM) Program The program operation will program a previously erased address in the Flash memory using an embedded algorithm. An example flow to execute the program operation is shown in Figure 17-15. The program command write sequence is as follows: 1.
Page 264 ColdFire Flash Module (CFM) START Read: Register CFMCLKD Clock Register Written DIVLD Check Set? Write: Register CFMCLKD Read: Register CFMUSTAT CBEIF Set? Access Error and Write: Register CFMUSTAT ACCERR/PVIOL Protection Violation Clear bit ACCERR/PVIOL $30 Set? Check Write: Array Address and Data NOTE: command write sequence Write: Register CFMCMD...
Page 265 ColdFire Flash Module (CFM) An example flow to execute the page erase operation is shown in Figure 17-16. The page erase command write sequence is as follows: 1. Write to any word address in a Flash logical page to start the command write sequence for the page erase command.
Page 266 ColdFire Flash Module (CFM) START Read: Register CFMCLKD Clock Register Written DIVLD Check Set? Write: Register CFMCLKD Read: Register CFMUSTAT CBEIF Set? Access Error and Write: Register CFMUSTAT ACCERR/PVIOL Protection Violation Clear bit ACCERR/PVIOL $30 Set? Check Write: Logical Page Address and Dummy Data NOTE: command write sequence Write: Register CFMCMD...
Page 267 ColdFire Flash Module (CFM) An example flow to execute the mass erase command is shown in Figure 17-17. The mass erase command write sequence is as follows: 1. Write to any Flash memory address to start the command write sequence for the mass erase command.
Page 268 ColdFire Flash Module (CFM) START Read: Register CFMCLKD Clock Register Written DIVLD Check Set? Write: Register CFMCLKD Read: Register CFMUSTAT CBEIF Set? Access Error and Write: Register CFMUSTAT ACCERR/PVIOL Protection Violation Clear bit ACCERR/PVIOL $30 Set? Check Write: Array Address and Dummy Data NOTE: command write sequence Write: Register CFMCMD...
Page 269 ColdFire Flash Module (CFM) 17.4.2.3.5 Flash Normal Mode Illegal Operations The ACCERR flag will be set during the command write sequence if any of the following illegal operations are performed, causing the command write sequence to immediately abort: 1. Writing to the Flash memory before initializing CFMCLKD. 2.
Page 270 ColdFire Flash Module (CFM) If a command is not active (CCIF=1) when the MCU enters stop mode, the ACCERR flag will not set. 17.4.3 Flash Security Operation The CFM provides security information to the Integration module and the rest of the MCU. This security information is stored within a word in the Flash configuration field.
Page 271 ColdFire Flash Module (CFM) 17.4.3.2 Blank Check A secured CFM can be unsecured by verifying that the entire Flash memory is erased. If required, the mass erase command can be executed on the Flash memory. The blank check command must then be executed on the Flash memory.
Page 272 ColdFire Flash Module (CFM) MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 0 17-30 Freescale Semiconductor Preliminary...
Page 273: Fast Ethernet Controller (Fec)
Chapter 18 Fast Ethernet Controller (FEC) This chapter provides a feature-set overview and a functional block diagram. Additionally, detailed descriptions of operation and the programming model are included. 18.1 Overview The Ethernet Media Access Controller (MAC) is designed to support both 10 and 100 Mbps Ethernet/IEEE 802.3 networks.
Page 274 Fast Ethernet Controller (FEC) 18.2.2 Interface Options The following interface options are supported. A detailed discussion of the interface configurations is provided in Section 18.4.5, “Network Interface Options”. 18.2.2.1 10 Mbps and 100 Mbps MII Interface MII is the Media Independent Interface defined by the IEEE 802.3 standard for 10/100 Mbps operation. The MAC-PHY interface may be configured to operate in MII mode by asserting RCR[MII_MODE].
Page 275: Fec Top-Level Functional Diagram
FEC Top-Level Functional Diagram 18.3 FEC Top-Level Functional Diagram The block diagram of the FEC is shown below. The FEC is implemented with a combination of hardware and microcode. The off-chip (Ethernet) interfaces are compliant with industry and IEEE 802.3 standards. Controller FIFO Controller...
Page 276: Functional Description
Fast Ethernet Controller (FEC) NOTE DMA references in this section refer to the FEC’s DMA engine. This DMA engine is for the transfer of FEC data only, and is not related to the DMA controller described in Chapter 16, “DMA Controller Module,”...
Page 277 Functional Description Table 18-1. ECR[ETHER_EN] De-Assertion Effect on FEC Register/Machine Reset Value XMIT block Transmission is aborted (bad CRC appended) RECV block Receive activity is aborted DMA block All DMA activity is terminated RDAR Cleared TDAR Cleared Descriptor Controller block Halt operation 18.4.2 User Initialization (Prior to Asserting ECR[ETHER_EN])
Page 278 Fast Ethernet Controller (FEC) 18.4.3 Microcontroller Initialization In the FEC, the descriptor control RISC initializes some registers after ECR[ETHER_EN] is asserted. After the microcontroller initialization sequence is complete, the hardware is ready for operation. Table 18-4 shows microcontroller initialization operations. Table 18-4.
Page 279 Functional Description Table 18-5. MII Mode (continued) Signal Description EMAC pin Management Data Clock EMDC Management Data EMDIO Input/Output The 7-wire serial mode interface (RCR[MII_MODE] = 0) operates in what is generally referred to as the “AMD” mode. 7-wire mode connections to the external transceiver are shown in Table 18-6.
Page 280 Fast Ethernet Controller (FEC) Both buffer (TXB) and frame (TFINT) interrupts may be generated as determined by the settings in the EIMR. The transmit error interrupts are HBERR, BABT, LATE_COL, COL_RETRY_LIM, and XFIFO_UN. If the transmit frame length exceeds MAX_FL bytes the BABT interrupt will be asserted, however the entire frame will be transmitted (no truncation).
Page 281 Functional Description The Ethernet controller receives serial data LSB first. 18.4.8 Ethernet Address Recognition The FEC filters the received frames based on destination address (DA) type — individual (unicast), group (multicast), or broadcast (all-ones group address). The difference between an individual address and a group address is determined by the I/G bit in the destination address field.
Page 282 Fast Ethernet Controller (FEC) Accept/Reject Frame True False Broadcast Addr Receive Address Recognition True False Hash Match BC_REJ = 1 False True Receive Frame Receive Frame Set MC bit in RCV BD if multicast Set BC bit in RCV BD True Exact Match False...
Page 283 Functional Description Receive Address Recognition Group Individual I/G Address True False True Exact Match False True False Pause Address Hash Search Individual Table Receive Frame Receive Frame Hash Search Group Table True Match True Match Receive Frame False False Reject Frame Receive Frame Flush from FIFO Reject Frame...
Page 284 Fast Ethernet Controller (FEC) A table of example Destination Addresses and corresponding hash values is included below for reference. Table 18-7. Destination Address to 6-Bit Hash 6-bit Hash (in Hash Decimal 48-bit DA hex) Value 65:ff:ff:ff:ff:ff 55:ff:ff:ff:ff:ff 15:ff:ff:ff:ff:ff 35:ff:ff:ff:ff:ff b5:ff:ff:ff:ff:ff 95:ff:ff:ff:ff:ff d5:ff:ff:ff:ff:ff f5:ff:ff:ff:ff:ff...
Page 285 Functional Description Table 18-7. Destination Address to 6-Bit Hash (continued) 6-bit Hash (in Hash Decimal 48-bit DA hex) Value 59:ff:ff:ff:ff:ff 0x1c 79:ff:ff:ff:ff:ff 0x1d 29:ff:ff:ff:ff:ff 0x1e 19:ff:ff:ff:ff:ff 0x1f d1:ff:ff:ff:ff:ff 0x20 f1:ff:ff:ff:ff:ff 0x21 b1:ff:ff:ff:ff:ff 0x22 91:ff:ff:ff:ff:ff 0x23 11:ff:ff:ff:ff:ff 0x24 31:ff:ff:ff:ff:ff 0x25 71:ff:ff:ff:ff:ff 0x26 51:ff:ff:ff:ff:ff 0x27...
Page 286 Fast Ethernet Controller (FEC) Table 18-7. Destination Address to 6-Bit Hash (continued) 6-bit Hash (in Hash Decimal 48-bit DA hex) Value fd:ff:ff:ff:ff:ff 0x3c dd:ff:ff:ff:ff:ff 0x3d 9d:ff:ff:ff:ff:ff 0x3e bd:ff:ff:ff:ff:ff 0x3f 18.4.10 Full Duplex Flow Control Full-duplex flow control allows the user to transmit pause frames and to detect received pause frames. Upon detection of a pause frame, MAC data frame transmission stops for a given pause duration.
Page 287 Functional Description 18.4.11 Inter-Packet Gap (IPG) Time The minimum inter-packet gap time for back-to-back transmission is 96 bit times. After completing a transmission or after the backoff algorithm completes, the transmitter waits for carrier sense to be negated before starting its 96 bit time IPG counter. Frame transmission may begin 96 bit times after carrier sense is negated if it stays negated for at least 60 bit times.
Page 288 Fast Ethernet Controller (FEC) 18.4.14.1 Transmission Errors 18.4.14.1.1 Transmitter Underrun If this error occurs, the FEC sends 32 bits that ensure a CRC error and stops transmitting. All remaining buffers for that frame are then flushed and closed. The UN bit is set in the EIR. The FEC will then continue to the next transmit buffer descriptor and begin transmitting the next frame.
Page 289: Programming Model
Programming Model then the frame non-octet aligned (NO) error is reported in the RxBD. If there is no CRC error, then no error is reported. 18.4.14.2.3 CRC Error When a CRC error occurs with no dribble bits, the FEC closes the buffer and sets the CR bit in the RxBD. CRC checking cannot be disabled, but the CRC error can be ignored if checking is not required.
Page 290 Fast Ethernet Controller (FEC) Table 18-10. FEC Register Memory Map (continued) IPSBAR Name Width Description Offset 0x1024 Ethernet Control Register 0x1040 MDATA MII Data Register 0x1044 MSCR MII Speed Control Register 0x1064 MIBC MIB Control/Status Register 0x1084 Receive Control Register 0x10C4 Transmit Control Register 0x10E4...
Page 291 Programming Model Table 18-11. MIB Counters Memory Map IPSBAR Mnemonic Description Offset 0x1200 RMON_T_DROP Count of frames not counted correctly 0x1204 RMON_T_PACKETS RMON Tx packet count 0x1208 RMON_T_BC_PKT RMON Tx Broadcast Packets 0x120C RMON_T_MC_PKT RMON Tx Multicast Packets 0x1210 RMON_T_CRC_ALIGN RMON Tx Packets w CRC/Align error 0x1214 RMON_T_UNDERSIZE...
Page 292 Fast Ethernet Controller (FEC) Table 18-11. MIB Counters Memory Map (continued) IPSBAR Mnemonic Description Offset 0x128C RMON_R_MC_PKT RMON Rx Multicast Packets 0x1290 RMON_R_CRC_ALIGN RMON Rx Packets w CRC/Align error 0x1294 RMON_R_UNDERSIZE RMON Rx Packets < 64 bytes, good crc 0x1298 RMON_R_OVERSIZE RMON Rx Packets >...
Page 293 Programming Model Some of the error interrupts are independently counted in the MIB block counters. Software may choose to mask off these interrupts since these errors will be visible to network management via the MIB counters. • HBERR - IEEE_T_SQE •...
Page 294 Fast Ethernet Controller (FEC) Table 18-12. EIR Field Descriptions (continued) Bits Name Description Transmit frame interrupt. This bit indicates that a frame has been transmitted and that the last corresponding buffer descriptor has been updated. Transmit buffer interrupt. This bit indicates that a transmit buffer descriptor has been updated.
Page 295 Programming Model 18.5.4.2 Interrupt Mask Register (EIMR) The EIMR register controls which interrupt events are allowed to generate actual interrupts. All implemented bits in this CSR are read/write. This register is cleared upon a hardware reset. If the corresponding bits in both the EIR and EIMR registers are set, the interrupt will be signalled to the CPU. The interrupt signal will remain asserted until a 1 is written to the EIR bit (write 1 to clear) or a 0 is written to the EIMR bit.
Page 296 Fast Ethernet Controller (FEC) Field — R_DES_ACTIVE — Reset 0000_0000_0000_0000 Field — Reset 0000_0000_0000_0000 Address IPSBAR + 0x1010 Figure 18-6. Receive Descriptor Active Register (RDAR) Table 18-14. RDAR Field Descriptions Bits Name Description 31–25 — Reserved, should be cleared. R_DES_ACTIVE Set to one when this register is written, regardless of the value written. Cleared by the FEC device whenever no additional “empty”...
Page 297 Programming Model Field — X_DES_ACTIVE — Reset 0000_0000_0000_0000 Field — Reset 0000_0000_0000_0000 Address IPSBAR + 0x1014 Figure 18-7. Transmit Descriptor Active Register (TDAR) Table 18-15. TDAR Field Descriptions Bits Name Description 31–25 — Reserved, should be cleared. X_DES_ACTIVE Set to one when this register is written, regardless of the value written. Cleared by the FEC device whenever no additional “ready”...
Page 298 Fast Ethernet Controller (FEC) Table 18-16. ECR Field Descriptions Bits Name Description 31-2 — Reserved. ETHER_EN When this bit is set, the FEC is enabled, and reception and transmission are possible. When this bit is cleared, reception is immediately stopped and transmission is stopped after a bad CRC is appended to any currently transmitted frame.
Page 299 Programming Model Table 18-17. MMFR Field Descriptions Name Description 31–30 Start of frame delimiter. These bits must be programmed to 01 for a valid MII management frame. 29–28 Operation code. This field must be programmed to 10 (read) or 01 (write) to generate a valid MII management frame. A value of 11 will produce “read”...
Page 300 Fast Ethernet Controller (FEC) Field — Reset 0000_0000_0000_0000 Field — DIS_PREAMBLE MII_SPEED — Reset 0000_0000_0000_0000 Address IPSBAR + 0x1044 Figure 18-10. MII Speed Control Register (MSCR) Table 18-18. MSCR Field Descriptions Bits Name Description 31–8 — Reserved, should be cleared. DIS_PREAMBLE Asserting this bit will cause preamble (32 1’s) not to be prepended to the MII management frame.
Page 301 Programming Model Table 18-19. Programming Examples for MSCR (continued) System Clock Frequency MII_SPEED (field in reg) EMDC frequency 50 MHz 2.5 MHz 66 MHz 2.5 MHz 18.5.4.8 MIB Control Register (MIBC) The MIBC is a read/write register used to provide control of and to observe the state of the MIB block. This register is accessed by user software if there is a need to disable the MIB block operation.
Page 302 Fast Ethernet Controller (FEC) 18.5.4.9 Receive Control Register (RCR) The RCR is programmed by the user. The RCR controls the operational mode of the receive block and should be written only when ECR[ETHER_EN] = 0 (initialization time). 27 26 Field —...
Page 303 Programming Model Table 18-21. RCR Field Descriptions (continued) Bits Name Description Disable receive on transmit. 0 Receive path operates independently of transmit (use for full duplex or to monitor transmit activity in half duplex mode). 1 Disable reception of frames while transmitting (normally used for half duplex mode).
Page 304 Fast Ethernet Controller (FEC) Table 18-22. TCR Field Descriptions Bits Name Description 31–5 — Reserved, should be cleared. RFC_PAUSE Receive frame control pause. This read-only status bit will be asserted when a full duplex flow control pause frame has been received and the transmitter is paused for the duration defined in this pause frame.
Page 305 Programming Model Field PADDR1 Reset Uninitialized Field PADDR1 Reset Uninitialized Address IPSBAR + 0x10E4 Figure 18-14. Physical Address Low Register (PALR) Table 18-23. PALR Field Descriptions Bits Name Description 31–0 PADDR1 Bytes 0 (bits 31:24), 1 (bits 23:16), 2 (bits 15:8) and 3 (bits 7:0) of the 6-byte individual address to be used for exact match, and the Source Address field in PAUSE frames.
Page 306 Fast Ethernet Controller (FEC) Table 18-24. PAUR Field Descriptions BIts Name Description 31–16 PADDR2 Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address to be used for exact match, and the Source Address field in PAUSE frames. 15–0 TYPE Type field in PAUSE frames.
Page 307 Programming Model Field IADDR1 Reset Uninitialized Field IADDR1 Reset Uninitialized Address IPSBAR + 0x1118 Figure 18-17. Descriptor Individual Upper Address Register (IAUR) Table 18-26. IAUR Field Descriptions Bits Name Descriptions 31–0 IADDR1 The upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast address.
Page 308 Fast Ethernet Controller (FEC) Table 18-27. IALR Field Descriptions Bits Name Description 31–0 IADDR2 The lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast address. Bit 31 of IADDR2 contains hash index bit 31.
Page 309 Programming Model Field GADDR2 Reset Uninitialized Field GADDR2 Reset Uninitialized Address IPSBAR + 0x1124 Figure 18-20. Descriptor Group Lower Address Register (GALR) Table 18-29. GALR Field Descriptions Bits Name Description 31–0 GADDR2 The GADDR2 register contains the lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address.
Page 310 Fast Ethernet Controller (FEC) Table 18-30. TFWR Field Descriptions Bits Name Descriptions 31–2 — Reserved, should be cleared. 1–0 X_WMRK Number of bytes written to transmit FIFO before transmission of a frame begins 0x 64 bytes written 10 128 bytes written 11 192 bytes written 18.5.4.19 FIFO Receive Bound Register (FRBR) The FRBR is an 8-bit register that the user can read to determine the upper address bound of the FIFO...
Page 311 Programming Model 18.5.4.20 FIFO Receive Start Register (FRSR) The FRSR is an 8-bit register programmed by the user to indicate the starting address of the receive FIFO. FRSR marks the boundary between the transmit and receive FIFOs. The transmit FIFO uses addresses from the start of the FIFO to the location four bytes before the address programmed into the FRSR.
Page 312 Fast Ethernet Controller (FEC) Field R_DES_START Reset Uninitialized Field R_DES_START — Reset Uninitialized Address IPSBAR + 0x1180 Figure 18-24. Receive Descriptor Ring Start Register (ERDSR) Table 18-33. ERDSR Field Descriptions Bits Name Descriptions 31–2 R_DES_START Pointer to start of receive buffer descriptor queue. 1–0 —...
Page 313 Programming Model Table 18-34. ETDSR Field Descriptions Bits Name Descriptions 31–2 X_DES_START Pointer to start of transmit buffer descriptor queue. 1–0 — Reserved, should be cleared. 18.5.4.23 Receive Buffer Size Register (EMRBR) The EMRBR is a 9-bit register programmed by the user. The EMRBR register dictates the maximum size of all receive buffers.
Page 314: Buffer Descriptors
Fast Ethernet Controller (FEC) 18.6 Buffer Descriptors This section provides a description of the operation of the driver/DMA via the buffer descriptors. It is followed by a detailed description of the receive and transmit descriptor fields. 18.6.1 Driver/DMA Operation with Buffer Descriptors The data for the FEC frames must reside in memory external to the FEC.
Page 315 Buffer Descriptors the RISC will stop the transmit descriptor read process until software sets up another transmit frame and writes to TDAR. When the DMA of each transmit buffer is complete, the DMA writes back to the BD to clear the R bit, indicating that the hardware consumer is finished with the buffer.
Page 316 Fast Ethernet Controller (FEC) Offset + 0 — — — Offset + 2 Data Length Offset + 4 Rx Data Buffer Pointer - A[31:16] Offset + 6 Rx Data Buffer Pointer - A[15:0] Table 18-36. Receive Buffer Descriptor Field Definitions Word Location Field Name...
Page 317 Buffer Descriptors Table 18-36. Receive Buffer Descriptor Field Definitions (continued) Word Location Field Name Description Offset + 0 Bit 5 Rx frame length violation. Written by the FEC. A frame length greater than RCR[MAX_FL] was recognized. This bit is valid only if the L-bit is set.
Page 318 Fast Ethernet Controller (FEC) indicated via individual interrupt bits (error conditions) and in statistic counters in the MIB block. See Section 18.5.3, “MIB Block Counters Memory Map” for more details. Offset + 0 Offset + 2 Data Length Offset + 4 Tx Data Buffer Pointer - A[31:16] Offset + 6 Tx Data Buffer Pointer - A[15:0]...
Page 319 Buffer Descriptors Table 18-37. Transmit Buffer Descriptor Field Definitions (continued) Word Location Field Name Description Offset + 2 Bits [15:0] Data Length Data Length, written by user. Data length is the number of octets the FEC should transmit from this BD’s data buffer. It is never modified by the FEC. Bits [15:5] are used by the DMA engine, bits[4:0] are ignored.
Page 320 Fast Ethernet Controller (FEC) MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 0 18-48 Preliminary Freescale Semiconductor...
Page 321: Ethernet Physical Transceiver (Ephy) Block Description
Chapter 19 Ethernet Physical Transceiver (EPHY) Block Description 19.1 Introduction The Ethernet physical transceiver (Ethernet physical interface) is an IEEE 802.3 compliant 10BASE-T/100BASE-TX Ethernet PHY transceiver. The Ethernet physical interface module supports both the medium-independent interface (MII) and the MII management interface. The EPHY requires a 25-MHz crystal for its basic operation.
Page 322 Ethernet Physical Transceiver (EPHY) Block Description 19.1.2 Block Diagram PHY_TXP MII_RXCLK PHY_TXN MII_RXDV MII_RXD[3:0] MII_RXER PHY_RXP PHY_RXN MII_TXCLK PHY_RBIAS MII_TXEN PHY SUB BLOCK MII_TXD[3:0] MII_TXER MII_CRS MII_COL MII_MDC MII_MDIO MII INTERFACE IP BUS IP BUS REGISTERS SIGNALS REF CLOCK Figure 19-1. Ethernet Physical Transceiver (EPHY) Block Diagram MCF52235 ColdFire®...
Page 323: External Signal Descriptions
External Signal Descriptions POLARITY CORRECTION 10BASE-T CLOCK RECOVERY SQUELCH RECEIVER MANCHESTER DECODE LINK DETECT VGA CONTROL 4B/5B 100BASE-TX MLT-3 DECODE (COARSE EQUALIZER) DECODE DESCRAMBLER RECEIVER DIGITAL EQUALIZER SLICER TIMING CONTROL BLW CONTROL 100BASE-TX AUTO COLLISION LOOPBACK NEGOTIATE CARRIER SENSE 10BASE-T DIG LOOP B 10BASE-T MANCHESTER ENCODER...
Page 324 Ethernet Physical Transceiver (EPHY) Block Description 19.2.4 PHY_RXN — EPHY Twisted Pair Input – Ethernet twisted-pair input pin. This pin is high-impedance out of reset. 19.2.5 PHY_RBIAS — EPHY Bias Control Resistor Connect a 1.0% external resistor, RBIAS (see Electrical Characteristics chapter), between the PHY_RBIAS pin and analog ground.
Page 325: Memory Map And Register Descriptions
Memory Map and Register Descriptions 19.2.13 ACTLEC — Activity LED Flashes when data is received by the device if EPHYCTL0 LEDEN bit is set. 19.3 Memory Map and Register Descriptions This section provides a detailed description of all registers accessible in the Ethernet physical interface. 19.3.1 Module Memory Map Table 19-1...
Page 326 Ethernet Physical Transceiver (EPHY) Block Description ANDIS — Auto Negotiation Disable This bit can be written anytime, but the value is latched in the ANE bit of the MII PHY control register (MII address 0.12) only when the EPHYEN bit transitions from 0 to 1. 1 = Auto negotiation is disabled after start-up.
Page 327 Memory Map and Register Descriptions Read: Anytime Write: See each bit description PHYADD[4:0] — EPHY Address for MII Requests These bits can be written anytime, but the EPHY address is latched to the MII PHY address register (MII address 21.4:0) only when the EPHYEN bit transitions from 0 to 1. PHYADD4 is the MSB of the of the EPHY address.
Page 328 Ethernet Physical Transceiver (EPHY) Block Description 19.3.3 MII Registers Table 19-2 gives an overview of all registers in the Ethernet physical interface that are accessible via the MII management interface. These registers are not part of the MCU memory map. Table 19-2.
Page 329 Memory Map and Register Descriptions RESET — EPHY Reset Resetting a port is accomplished by setting this bit to 1. 1 = The PHY will reset the port’s status and registers to the default values. The PHY will also reset the PHY to its initial state.
Page 330 Ethernet Physical Transceiver (EPHY) Block Description RAN — Restart Auto-Negotiation The RAN bit determines when the A/N process can start processing. 1 = When auto-negotiation is enabled (ANE=1), the auto-negotiation process will be restarted. After auto-negotiation indicates that it has been initialized, this bit is cleared. When bit ANE is cleared to indicate auto-negotiation is disabled, RAN must also be 0.
Page 331 Memory Map and Register Descriptions 100XHD —100BASE-TX Half-Duplex 1 = Indicates the PHY supports 100BASE-TX half-duplex mode 0 = Indicates the PHY does not support 100BASE-TX half-duplex mode 10TFD —10BASE-T Full-Duplex 1 = Indicates the PHY supports 10BASE-T full-duplex mode 0 = Indicates the PHY does not support 10BASE-T full-duplex mode 10THD —10BASE-T Half-Duplex 1 = Indicates the PHY supports 10BASE-T half-duplex mode...
Page 332 Ethernet Physical Transceiver (EPHY) Block Description JABDT —Jabber Detect After it is set, JABDT is cleared each time register 1 is read via the management interface. JABDT is also cleared by a PHY reset. For 100BASE-TX operation, this signal will always be cleared. 1 = Indicates that a jabber condition has been detected 0 = Indicates that no jabber condition has been detected EXCAP —...
Page 333 Memory Map and Register Descriptions 19.3.3.5 Auto-Negotiate (A/N) Advertisement Register The auto-negotiation (A/N) process requires four registers to communicate link information with its link partner: A/N advertisement register (MII register 4), A/N link partner ability register (MII register 5), A/N expansion register (MII register 6), and the A/N next page transmit register (MII register 7).
Page 334 Ethernet Physical Transceiver (EPHY) Block Description TAF10HD — 10BASE-T Half-Duplex 1 = 10BASE-T half-duplex capable 0 = Not 10BASE-T half-duplex capable 19.3.3.6 Auto Negotiation Link Partner Ability (Base Page) Figure 19-11 shows the contents of the A/N link partner ability register. The register can only be read by the MI and will be written by the auto-negotiation process when it receives a link code word advertising the capabilities of the link partner.
Page 335 Memory Map and Register Descriptions TAF100HD — 100BASE-TX Half-Duplex 1 = Link partner is 100BASE-TX half-duplex capable 0 = Link partner is not 100BASE-TX half-duplex capable TAF10FD — 10BASE-T Full-Duplex 1 = Link partner is10BASE-T full-duplex capable 0 = Link partner is not 10BASE-T full-duplex capable TAF10HD —...
Page 336 Ethernet Physical Transceiver (EPHY) Block Description Message/Unformatted Code Field Message code field — Predefined code fields defined in IEEE 802.3u-1995 Annex 28C Unformatted code filed — 11-bit field containing an arbitrary value 19.3.3.8 Auto-Negotiation Expansion Register Figure 19-13 shows the contents of the A/N expansion register. The MI process can only read this register. This register contains information about the A/N capabilities of the port’s link partner and information on the status of the parallel detection mechanism.
Page 337 Memory Map and Register Descriptions LPANA — Link Partner A/N Able Indicates whether the link partner has A/N capabilities. 1 = Link partner is A/N able 0 = Link partner is not A/N able 19.3.3.9 Auto Negotiation Next Page Transmit Figure 19-14 shows the contents of the A/N next page transmit register.
Page 338 Ethernet Physical Transceiver (EPHY) Block Description 19.3.4 PHY-Specific Registers PHY also contains a number of registers to set its internal mode of operation. These registers can be set through the external management interface to determine capabilities such as speed, test-mode, circuit bypass mode, interrupt setting, etc.
Page 339 Memory Map and Register Descriptions ACKR — Acknowledge Bit Received 1 = Acknowledge bit has been received from the link partner 0 = Acknowledge bit has not been received since the last access of this register. (ACK bit 14 of the auto-negotiation link partner ability register was set by receipt of link code word) PGR —...
Page 340 Ethernet Physical Transceiver (EPHY) Block Description LNK — Link Status This is a duplicate of LNKSTAT bit 2 of the status register (1.2). 1 = Link is down 0 = Link is up DPMD — Duplex Mode 1 = Full-duplex 0 = Half-duplex SPD —...
Page 341: Functional Description
Functional Description FEFLTD — Far End Fault Disable 1 = Far end fault detect is disabled 0 = Far end fault detect on receive and transmit is enabled. This applies only while auto-negotiation is disabled MIILBO — MII Loopback Disable 1 = Disable MII loopback 0 = MII transmit data is looped back to the MII receive pins JBDE —...
Page 342 Ethernet Physical Transceiver (EPHY) Block Description • 10BASE-T • 100BASE-TX • Low-power 19.4.1 Power Down/Initialization Upon reset, the EPHYEN bit, in the Ethernet physical transceiver control register 0 (EPHYCTL0), is cleared and EPHY is in its lowest power consumption state. All analog circuits are powered down. The twisted-pair transmitter and receiver pins (PHY_TXP, PHY_TXN, PHY_RXP, and PHY_RXN) are high-impedance.
Page 343 Functional Description RESET or EPHYEN=0 Set PHYADD[4:0], and ANDIS, DIS100, DIS10 Set EPHYEN=1 PHYADD[4:0] and ANDIS become latched in MII registers Delay for t Start-up Configure MII registers via MDIO Initialization Complete Figure 19-18. EPHY Start-Up / Initialization Sequence EPHYEN MDIO Start-up Figure 19-19.
Page 344 Ethernet Physical Transceiver (EPHY) Block Description If the auto-negotiation mode of operation is desired, the ANDIS bit in the EPHYCTL0 must be set to 0 and the DIS100 and DIS10 bits must be cleared prior to setting EPHYEN to 1. Refer to Section 19.4.2, “Auto-Negotiation,”...
Page 345 Functional Description Figure 19-20 shows the main blocks used in the auto-negotiation function. The transmit block allows transmission of fast link pulses to establish communications with partners that are auto-negotiation able. The receive block determines the capabilities of the link partner and writes to the link partner ability register (register 5).
Page 346 Ethernet Physical Transceiver (EPHY) Block Description A 2.5 MHz internal clock is used for nibble wide transactions. A 10 MHz internal clock is used for serial transactions. PARALLEL PHY_TXN MANCHESTER DIGITAL PHY_TXP ENCODER FILTER SERIAL DIGITAL CARRIER LINE TRANSMITTER/ LOOPBACK JABBER SENSE (bit 0.14)
Page 347 Functional Description Link Integrity Test: Used to determine whether the 10BASE-T link is operational. If neither data nor a link pulse is received for 64 ms, then the link is considered down. While the link is down, the transmit, loopback, collision detect, and SQE functions are disabled. The link down state is exited after receiving data or four link pulses.
Page 348 Ethernet Physical Transceiver (EPHY) Block Description PARALLEL MLT3 4B5B SLOPE LINE SCRAMBLER ENCODER ENCODER CONTROL DRIVER SERIAL DIGITAL ANALOG CARRIER LINK LOOPBACK LOOPBACK SENSE MONITOR (bit 0.14) (bit 18.4) SERIAL TO EQUALIZER PARALLEL 4B5B MLT3 BASELINE DESCRAMBLER TIMING AND SYMBOL DECODER DECODER WANDER...
Page 349 Functional Description 4B/5B Encoder/Decoder: The 4B/5B encoder converts the 4-bit nibbles from the reconciliation sublayer to a 5-bit code group. 19.4.4.1.2 PMA Sublayer The PMA provides medium-independent means for the PCS and other bit-oriented clients (e.g., repeaters) to support the use of a range of physical media. For 100BASE-TX the PMA performs these functions: •...
Page 350 Ethernet Physical Transceiver (EPHY) Block Description restoration to restore the lost DC component of the recovered digital data to correct the baseline wander problem. Timing Recovery: The timing recovery block locks onto the incoming data stream, extracts the embedded clock, and presents the data synchronized to the recovered clock. In the event that the receive path is unable to converge to the receive signal, it resets the MSE-good (bit 25.15) signal.
Page 351 Functional Description 19.4.5.2 Wait Mode If the MCU executes a WAIT instruction with the EPHYWAI bit set, the EPHY will be powered down and all internal MII registers reset to their default state. Upon exiting STOP mode the EPHY will exit the power-down state and latch the values previously written to the EPHYCTL0 and EPHYCTL1 registers.
Page 352 Ethernet Physical Transceiver (EPHY) Block Description MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 0 19-32 Freescale Semiconductor Preliminary...
Page 353: Dma Controller Module
Chapter 20 DMA Controller Module 20.1 Introduction This chapter describes the direct memory access (DMA) controller module. It provides an overview of the module and describes in detail its signals and registers. The latter sections of this chapter describe operations, features, and supported data transfer modes in detail. NOTE The designation ‘n’...
Page 354 DMA Controller Module MADDR[31:0] SADDR[4:2] SDATA[31:0] MWDATA[31:0] MRDATA[31:0] MRSTH SSRSTH SMEN[3:0] SBE[3:0] MSIZ[1:0] MTT[1:0] MTM[2:0] SIVOE SINT[3:0] MTEA EXT_REQ[3:0] # - Version 3 Mbus signal * - Version 2 Mbus signal MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 0 20-2 Preliminary Freescale Semiconductor...
Page 355 DMA Controller Module DREQ0 DREQ1 DREQ2 DREQ3 Channel 0 Channel 1 Channel 2 Channel 3 Internal SAR0 SAR1 SAR2 SAR3 DAR0 DAR1 DAR2 DAR3 Interrupts BCR0 BCR1 BCR2 BCR3 DCR0 DCR1 DCR2 DCR3 DSR0 DSR1 DSR2 DSR3 Channel Channel Requests Attributes Channel System Bus Address...
Page 356: M-Bus Priority Level (Mpl)
DMA Controller Module • Automatic channel linking 20.2 M-bus Priority Level (MPL) This output signal indicates to the bus arbiter that the DMA has been programmed to have priority on the transfer. This signal is a decode of the BWC bits. Depending on the M-bus arbiter architecture, this signal may be ignored.
Page 357: Memory Map/Register Definition
DMA Controller Module 3. Channel termination—Occurs after the operation is finished, either successfully or due to an error. The channel indicates the operation status in the channel’s DSR, described in Section 20.4.4.1, “DMA Status Registers (DSRn).” 20.4 Memory Map/Register Definition This section describes each internal register and its bit assignment.
Page 358 DMA Controller Module IPSBAR 0x00_0014 (DMAREQC) Access: read/write Offset: Off-Platform DMAREQ Control DMAREQC_EXT Reset DMAC3 DMAC2 DMAC1 DMAC0 Reset Figure 20-3. DMA Request Control Register (DMAREQC) IPSBAR 0x00_0014 Offset Off-Platform DMAREQ Control DMAREQC_EXT — Reset DMAC3 DMAC2 DMAC1 DMAC0 Reset Figure 20-4.
Page 359 DMA Controller Module Table 20-2. DMAREQC Field Description (continued) Field Description 15–0 DMA channel n. Each four bit field defines the logical connection between the DMA requesters and that DMA DMACn channel.There are ten possible requesters (4 DMA Timers and 6 UARTs). Any request can be routed to any of the DMA channels.
Page 360 DMA Controller Module IPSBAR 0x00_0100 (DMA0) Offset 0x00_0110 (DMA1) 0x00_0120 (DMA2) 0x00_0130 (DMA3) Reset Reset Figure 20-6. NOTE The backdoor enable bit must be set in the SCM RAMBAR as well as the secondary port valid bit in the core RAMBAR in order to enable backdoor accesses from the DMA to SRAM.
Page 361 DMA Controller Module IPSBAR 0x00_0104 (DMA0) Offset 0x00_0114 (DMA1) 0x00_0124 (DMA2) 0x00_0134 (DMA3) Reset Reset Figure 20-8. 20.4.4 Byte Count Registers (BCRn) and DMA Status Registers (DSRn) BCRn, shown in Figure 20-9, contains the number of bytes yet to be transferred for a given block. BCRn decrements on the successful completion of the address transfer of a write transfer.
Page 362 DMA Controller Module IPSBAR 0x00_0108 (DMA0) Offset 0x00_0118 (DMA1) 0x00_0128 (DMA2) 0x00_0138 (DMA3) Reset Reset Figure 20-10. DSRn[DONE], shown in Figure 20-11, is set when the block transfer is complete. When a transfer sequence is initiated and BCRn[BCR] is not a multiple of 16, 4, or 2 when the DMA is configured for line, longword, or word transfers, respectively, DSRn[CE] is set and no transfer occurs.
Page 363 DMA Controller Module IPSBAR Figure 20-9 Offset DONE Reset Figure 20-12. Table 20-3. DSRn Field Descriptions Field Description Reserved, should be cleared. Configuration error. Occurs when BCR, SAR, or DAR does not match the requested transfer size, or if BCR = 0 when the DMA receives a start condition.
Page 364 DMA Controller Module IPSBAR 0x00_010C (DMA0) Access: read/write Offset: 0x00_011C (DMA1) 0x00_012C (DMA2) 0x00_013C (DMA3) EEXT SINC SSIZE DINC DSIZE START Reset SMOD DMOD D_REQ LINKCC LCH1 LCH2 Reset Figure 20-13. DMA Control Registers (DCRn) IPSBAR 0x00_010C (DMA0) Offset 0x00_011C (DMA1) 0x00_012C (DMA2) 0x00_013C (DMA3) R INT EEXT...
Page 365 DMA Controller Module Table 20-4. DCRn Field Descriptions (continued) Field Description Auto-align. AA and SIZE determine whether the source or destination is auto-aligned, that is, transfers are optimized based on the address and size. See Section 20.5.4.1, “Auto-Alignment.” 0 Auto-align disabled 1 If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned;...
Page 366 DMA Controller Module Table 20-4. DCRn Field Descriptions (continued) Field Description 15–12 Source address modulo. Defines the size of the source data circular buffer used by the DMA controller. If enabled SMOD (SMOD is non-zero), the buffer base address will be located on a boundary of the buffer size. The value of this boundary is based upon the initial source address (SAR).
Page 367 DMA Controller Module Table 20-4. DCRn Field Descriptions (continued) Field Description Disable request. D_REQ If this flag is set, the DMA hardware automatically clears the corresponding DCRn[EEXT] bit when the byte count register reaches zero. 0 The channel’s EEXT bit is not affected. 1 The channel’s EEXT bit is cleared when the BCR is exhausted.
Page 368: Functional Description
DMA Controller Module 20.5 Functional Description In the following discussion, the term ‘DMA request’ implies that DCRn[START] or DCRn[EEXT] is set, followed by assertion of an internal or external DMA request. The START bit is cleared when the channel begins an internal access. Before initiating a dual-address access, the DMA module verifies that DCRn[SSIZE,DSIZE] are consistent with the source and destination addresses.
Page 369 DMA Controller Module 20.5.2 Dual-Address Data Transfer Mode Each channel supports dual-address transfers. Dual-address transfers consist of a source data read and a destination data write. The DMA controller module begins a dual-address transfer sequence during a DMA request. If no error condition exists, DSRn[REQ] is set. •...
Page 370 DMA Controller Module The DMAREQC register is configured to assign peripheral DMA requests to the individual DMA channels. The SARn is loaded with the source (read) address. If the transfer is from a peripheral device to memory, the source address is the location of the peripheral data register. If the transfer is from memory to either a peripheral device or memory, the source address is the starting address of the data block.
Page 371 DMA Controller Module Because SSIZE > DSIZE, the source is auto-aligned. Error checking is performed on destination registers. The access sequence is as follows: 1. Read byte from 0x0001—write 1 byte, increment SARn. 2. Read word from 0x0002—write 2 bytes, increment SARn. 3.
Page 372 DMA Controller Module MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 0 20-20 Preliminary Freescale Semiconductor...
Page 373: Ezport
Chapter 21 EzPort EzPort is a serial Flash programming interface that allows the Flash memory contents on a 32-bit general purpose microcontroller to be read, erased, and programmed from off-chip in a compatible format to many standalone Flash memory chips. 21.1 Features The EzPort includes the following features:...
Page 374: External Signal Description
EzPort Figure 21-1 is a block diagram of the EzPort. EzPort Enabled EZPCS EZPCK Flash EzPort Controller EZPD EZPQ Reset Flash Memory Reset Out Reset Controller Microcontroller Core Figure 21-1. EzPort Block Diagram 21.3 External Signal Description 21.3.1 Overview Table 21-1 contains a list of EzPort external signals.
Page 375: Command Definition
EzPort EZPCK.The maximum frequency of the EzPort clock is half the system clock frequency for all commands except when executing the read data command. When executing the Read Data command, the EzPort clock has a maximum frequency of one eighth the system clock frequency. 21.3.2.2 EZPCS —...
Page 376 EzPort 21.4.1 Command Descriptions 21.4.1.1 Write Enable The Write Enable command sets the write enable register bit in the status register. The write enable bit must be set for a Write Configuration Register (WRCR), Page Program (PP), Sector Erase (SE), or Bulk Erase (BE) command to be accepted.
Page 377 EzPort Table 21-3. EzPort Status Register Field Description (continued) Field Descriptions Configuration Register Loaded. Status flag that indicates if the configuration register has been loaded. The configuration register initializes the Flash controllers clock configuration register to generate a divided down clock from the system clock that runs at a frequency of 150 kHz to 200 kHz.
Page 378 EzPort Table 21-4. EzPort Configuration Register Field Description Field Descriptions Reserved, should be cleared. — Enables prescaler divide by 8. PRDIV 0 The system clock is fed directly into the divider. 1 Enables a prescaler that divides the system clock by 8 before it enters the divider. 5–0 Clock divider field.
Page 379: Functional Description
EzPort 21.4.1.8 Sector Erase The Sector Erase command erases the contents of a 2-Kbyte space of Flash memory. The 3-byte address sent after the command byte can be any address within the space to erase. This command should not be used if the write error flag is set, a write is in progress, the write enable bit is not set, or the configuration register has not been written.
Page 380: Initialization/Application Information
EzPort 21.6 Initialization/Application Information Prior to issuing any program or erase commands, the clock configuration register must be written to set the Flash state machine clock (FCLK). The Flash controller module runs at the system clock frequency divide by 2, but FCLK must be divided down from this frequency to a frequency between 150 kHz and 200 kHz.
Page 381: Programmable Interrupt Timer Modules (Pit0-Pit1)
Chapter 22 Programmable Interrupt Timer Modules (PIT0–PIT1) 22.1 Introduction This chapter describes the operation of the two programmable interrupt timer modules: PIT0–PIT1. 22.1.1 Overview Each PIT is a 16-bit timer that provides precise interrupts at regular intervals with minimal processor intervention.
Page 382: Memory Map/Register Definition
Programmable Interrupt Timer Modules (PIT0–PIT1) NOTE The low-power interrupt control register (LPICR) in the system control module specifies the interrupt level at or above which the device can be brought out of a low-power mode. Table 22-1. PIT Module Operation in Low-power Modes Low-power Mode PIT Operation Mode Exit...
Page 383 Programmable Interrupt Timer Modules (PIT0–PIT1) Accesses to reserved address locations have no effect and result in a cycle termination transfer error. User mode accesses to supervisor only addresses have no effect and result in a cycle termination transfer error. 22.2.1 PIT Control and Status Register (PCSRn) The PCSRn registers configure the corresponding timer’s operation.
Page 384 Programmable Interrupt Timer Modules (PIT0–PIT1) Table 22-3. PCSRn Field Descriptions (continued) Field Description Debug mode bit. Controls the function of the PIT in halted/debug mode. Reset clears DBG. During debug mode, register read and write accesses function normally. When debug mode is exited, timer operation continues from the state it was in before entering debug mode, but any updates made in debug mode remain.
Page 385: Functional Description
Programmable Interrupt Timer Modules (PIT0–PIT1) 22.2.3 PIT Count Register (PCNTRn) The 16-bit, read-only PCNTRn contains the counter value. Reading the 16-bit counter with two 8-bit reads is not guaranteed to be coherent. Writing to PCNTRn has no effect, and write cycles are terminated normally.
Page 386 Programmable Interrupt Timer Modules (PIT0–PIT1) When the PCSRn[OVW] bit is set, the counter can be directly initialized by writing to PMRn without having to wait for the count to reach 0x0000. PIT CLOCK COUNTER 0x0002 0x0001 0x0000 0xFFFF MODULUS 0x0005 Figure 22-6.
Page 387: General Purpose Timer Module (Gpt)
Chapter 23 General Purpose Timer Module (GPT) 23.1 Introduction This device has one 4-channel general purpose timer module (GPT). It consists of a 16-bit counter driven by a 7-stage programmable prescaler. A timer overflow function allows software to extend the timing capability of the system beyond the 16-bit range of the counter.
Page 388: Block Diagram
General Purpose Timer Module (GPT) 23.3 Block Diagram CLK[1:0] SYNCx System PR[2:0] Clock PACLK PACLK/256 Channel 3 Output Compare PACLK/65536 Divide Prescaler TCRE by 2 GPTCNTH:GPTCNTL Clear Counter 16-Bit Counter Interrupt Interrupt Request Logic Channel 0 Edge 16-Bit Comparator IOS0 CH.
Page 389: Low-Power Mode Operation
General Purpose Timer Module (GPT) 23.4 Low-Power Mode Operation This subsection describes the operation of the general purpose time module in low-power modes and halted mode of operation. Low-power modes are described in Chapter 7, “Power Management.” Table 23-1 shows the general purpose timer module operation in the low-power modes, and shows how this module may facilitate exit from each mode.
Page 390: Memory Map And Registers
General Purpose Timer Module (GPT) 23.5.3 SYNCn The SYNCn pin is for synchronization of the timer counter. It can be used to synchronize the counter with externally-timed or clocked events. A high signal on this pin clears the counter. 23.6 Memory Map and Registers Table 18-4 shows the memory map of the GPT module.
Page 391 General Purpose Timer Module (GPT) Table 23-3. QSPI Memory Map (continued) IPSBAR Width Register Access Reset Value Section/Page Offset (bits) 0x1A_0017 GPT Channel 3 Register Low (GPTC3L) 23.6.14/23-13 0x1A_0018 Pulse Accumulator Control Register (GPTPACTL) 0x00 18.6.15/18-19 0x1A_0019 Pulse Accumulator Flag Register (GPTPAFLG) 0x00 23.6.16/23-14 0x1A_001A...
Page 392 General Purpose Timer Module (GPT) 23.6.2 GPT Compare Force Register (GPCFORC) IPSBAR 0x1A_0001 (GPCFORC) Access: Supervisor read/write Offset: Reset: Figure 23-3. GPT Input Compare Force Register (GPCFORC) Table 23-5. GPTCFORC Field Descriptions Field Description 7–4 Reserved, should be cleared. 3–0 Force output compare.Setting an FOC bit causes an immediate output compare on the corresponding channel.
Page 393 General Purpose Timer Module (GPT) Table 23-6. GPTOC3M Field Descriptions Field Description 7–4 Reserved, should be cleared. 3–0 Output compare 3 mask. Setting an OC3M bit configures the corresponding PORTTn pin to be an output. OC3Mn OC3M makes the GPT port pin an output regardless of the data direction bit when the pin is configured for output compare (IOSx = 1).
Page 394 General Purpose Timer Module (GPT) Table 23-8. GPTCNT Field Descriptions Field Description 15–0 Read-only field that provides the current count of the timer counter. To ensure coherent reading of the timer counter, CNTR such that a timer rollover does not occur between two back-to-back 8-bit reads, it is recommended that only word (16-bit) accesses be used.
Page 395 General Purpose Timer Module (GPT) Write GPTFLG1 Register Data Bit n Clear CnF Flag TFFCA Read GPTCn Registers Write GPTCn Registers Figure 23-8. Fast Clear Flag Logic 23.6.7 GPT Toggle-On-Overflow Register (GPTTOV) IPSBAR 0x1A_0008 (GPTTOV) Access: Supervisor read/write Offset: Reset: Figure 23-9.
Page 396 General Purpose Timer Module (GPT) Table 23-11. GPTCL1 Field Descriptions Field Description 7–0 Output mode/output level. Selects the output action to be taken as a result of a successful output compare on each OMx/OLx channel. When either OMn or OLn is set and the IOSn bit is set, the pin is an output regardless of the state of the corresponding DDR bit.
Page 397 General Purpose Timer Module (GPT) Table 23-13. GPTIE Field Descriptions Field Description 7–4 Reserved, should be cleared. 3–0 Channel interrupt enable. Enables the C[3:0]F flags in GPT flag register 1 to generate interrupt requests for each channel. These bits are read anytime, write anytime. 1 Corresponding channel interrupt requests enabled 0 Corresponding channel interrupt requests disabled 23.6.11 GPT System Control Register 2 (GPTSCR2)
Page 398 General Purpose Timer Module (GPT) Table 23-14. GPTSCR2 Field Descriptions (continued) Field Description 2–0 Prescaler bits. Select the prescaler divisor for the GPT counter. 000 Prescaler divisor 1 001 Prescaler divisor 2 010 Prescaler divisor 4 011 Prescaler divisor 8 100 Prescaler divisor 16 101 Prescaler divisor 32 110 Prescaler divisor 64...
Page 399 General Purpose Timer Module (GPT) Table 23-16. GPTFLG2 Field Descriptions Field Description Timer overflow flag. Set when the GPT counter rolls over from 0xFFFF to 0x0000. If the TOI bit in GPTSCR2 is also set, TOF generates an interrupt request. This bit is read anytime, write anytime (writing 1 clears the flag, and writing 0 has no effect).
Page 400 General Purpose Timer Module (GPT) Table 23-18. GPTPACTL Field Descriptions Field Description Reserved, should be cleared. Enables the pulse accumulator. 1 Pulse accumulator enabled 0 Pulse accumulator disabled Note: The pulse accumulator can operate in event mode even when the GPT enable bit, GPTEN, is clear. Pulse accumulator mode.
Page 401 General Purpose Timer Module (GPT) Table 23-19. GPTPAFLG Field Descriptions Field Description 7–2 Reserved, should be cleared. Pulse accumulator overflow flag. Set when the 16-bit pulse accumulator rolls over from 0xFFFF to 0x0000. If the PAOVF GPTPACTL[PAOVI] bit is also set, PAOVF generates an interrupt request. Clear PAOVF by writing a 1 to it. This bit is read anytime, write anytime.
Page 402 General Purpose Timer Module (GPT) 23.6.18 GPT Port Data Register (GPTPORT) IPSBAR 0x1A_001D (GPTPORT) Access: Supervisor read/write Offset: PORTT Reset: Figure 23-20. GPT Port Data Register (GPTPORT) Table 23-21. GPTPORT Field Descriptions Field Description 7–4 Reserved, should be cleared. 3–0 GPT port input capture/output compare data.
Page 403: Functional Description
General Purpose Timer Module (GPT) 23.7 Functional Description The general purpose timer (GPT) module is a 16-bit, 4-channel timer with input capture and output compare functions and a pulse accumulator. 23.7.1 Prescaler The prescaler divides the module clock by 1 or 16. The PR[2:0] bits in GPTSCR2 select the prescaler divisor.
Page 404 General Purpose Timer Module (GPT) Writing to the PORTTn bit of an output compare pin does not affect the pin state. The value written is stored in an internal latch. When the pin becomes available for general-purpose output, the last value written to the bit appears at the pin.
Page 405 General Purpose Timer Module (GPT) NOTE The PAI input and GPT channel 3 use the same pin. To use the PAI input, disconnect it from the output logic by clearing the channel 3 output mode (OM3) and output level (OL3) bits. Also clear the channel 3 output compare mask bit (OC3M3).
Page 406 General Purpose Timer Module (GPT) 3. Clear the pin’s DDR bit in PORTTnDDR. 4. Write to the OMn/OLn bits in GPTCTL1 to select the output action. Table 23-23 shows how various timer settings affect pin functionality. Table 23-23. GPT Settings and Pin Functions EDGx OMx/ GPTEN DDR...
Page 407: Reset
General Purpose Timer Module (GPT) Setting an OC3M bit configures the corresponding PORTTn pin to be output. OC3Mn makes the PORTTn pin an output regardless of the data direction bit when the pin is configured for output compare (IOSn = 1). The OC3Mn bits do not change the state of the PORTTnDDR bits.
Page 408 General Purpose Timer Module (GPT) NOTE When the fast flag clear all enable bit (GPTSCR1[TFFCA]) is set, any access to the pulse accumulator counter registers clears all the flags in GPTPAFLG. 23.9.3 Pulse Accumulator Input (PAIF) PAIF is set when the selected edge is detected at the PAI pin. In event counter mode, the event edge sets PAIF.
Page 409: Dma Timers (Dtim0-Dtim3)
Chapter 24 DMA Timers (DTIM0–DTIM3) 24.1 Introduction This chapter describes the configuration and operation of the four direct memory access (DMA) timer modules (DTIM0, DTIM1, DTIM2, and DTIM3). These 32-bit timers provide input capture and reference compare capabilities with optional signaling of events using interrupts or DMA triggers. Additionally, programming examples are included.
Page 410: Memory Map/Register Definition
DMA Timers (DTIM0–DTIM3) Figure 24-1 is a block diagram of one of the four identical timer modules. Internal Bus Clock DMA Timer Mode Register (DTMRn) DMA Timer Extended Mode (÷1 or ÷16 DMA Timer Prescaler Mode Bits Register (DTXMRn) Clock Generator DTnIN Divider...
Page 411 DMA Timers (DTIM0–DTIM3) Table 24-1. DMA Timer Module Memory Map IPSBAR Offset DMA Timer 0 Width Register Access Reset Value Section/Page DMA Timer 1 (bits) DMA Timer 2 DMA Timer 3 0x00_0400 DMA Timer n Mode Register (DTMRn) 0x0000 24.2.1/24-3 0x00_0440 0x00_0480 0x00_04C0...
Page 412 DMA Timers (DTIM0–DTIM3) Table 24-2. DTMRn Field Descriptions Field Description 15–8 Prescaler value. The prescaler is programmed to divide the clock input (internal bus clock/(16 or 1) or clock on DTnIN) by values from 1 (PS = 0x00) to 256 (PS = 0xFF). 7–6 Capture edge.
Page 413 DMA Timers (DTIM0–DTIM3) 0x00_0402 (DTXMR0) IPSBAR Access: User read/write 0x00_0442 (DTXMR1) Offset: 0x00_0482 (DTXMR2) 0x00_04C2 (DTXMR3) DMAEN MODE16 DMAEN HALTED MODE16 Reset: Figure 24-3. DMA Timer Extended Mode Registers (DTXMRn) Table 24-3. DTXMRn Field Descriptions Field Description DMA request. Enables DMA request output on counter reference match or capture edge event. DMAEN 0 DMA request disabled 1 DMA request enabled...
Page 414 DMA Timers (DTIM0–DTIM3) IPSBAR 0x00_0403 (DTER0) Access: User read/write Offset: 0x00_0443 (DTER1) 0x00_0483 (DTER2) 0x00_04C3 (DTER3) Reset: Figure 24-4. DMA Timer Event Registers (DTERn) Table 24-4. DTERn Field Descriptions Field Description 7–2 Reserved, should be cleared. Output reference event. The counter value, DTCNn, equals the reference value, DTRRn. Writing a one to REF clears the event condition.
Page 415 DMA Timers (DTIM0–DTIM3) 24.2.4 DMA Timer Reference Registers (DTRRn) Each DTRRn, shown in Figure 24-5, contains the reference value compared with the respective free-running timer counter (DTCNn) as part of the output-compare function. The reference value is not matched until DTCNn equals DTRRn, and the prescaler indicates that DTCNn should be incremented again.
Page 416: Functional Description
DMA Timers (DTIM0–DTIM3) 0x00_040C (DTCN0) IPSBAR Access: User read/write 0x00_044C (DTCN1) Offset: 0x00_048C (DTCN2) 0x00_04CC (DTCN3) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 CNT (32-bit timer counter value count) Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 24-7.
Page 417 DMA Timers (DTIM0–DTIM3) — Capture the timer value on an edge detected on DTnIN — Configure DTnOUT output mode — Increment counter by 1 or by 65,537 (16-bit mode) — Enable/disable interrupt or DMA request on counter reference match or capture edge •...
Page 418 DMA Timers (DTIM0–DTIM3) timer0_ex clr.l DO clr.l D1 clr.l D2 move.l #0x0000,D0 move.l D0,TCN0 ;reset the counter to 0x0000 move.b #0x03,D0 ;writing ones to TER0[REF,CAP] move.b D0,TER0 ;clears the event flags move.w TMR0,D0 ;save the contents of TMR0 while setting bset #0,D0 ;the 0 bit.
Page 419: Queued Serial Peripheral Interface (Qspi)
Chapter 25 Queued Serial Peripheral Interface (QSPI) 25.1 Introduction This chapter describes the queued serial peripheral interface (QSPI) module. Following a feature set overview is a description of operation including details of the QSPI’s internal RAM organization. The chapter concludes with the programming model and a timing diagram. 25.1.1 Block Diagram Figure 25-1...
Page 420 Queued Serial Peripheral Interface (QSPI) 25.1.2 Overview The queued serial peripheral interface module provides a serial peripheral interface with queued transfer capability. It allows users to queue up to 16 transfers at once, eliminating CPU intervention between transfers. Transfer RAM in the QSPI is indirectly accessible using address and data registers. NOTE The GPIO module must be configured to enable the peripheral function of the appropriate pins (refer to...
Page 421 Queued Serial Peripheral Interface (QSPI) Table 25-1. QSPI Input and Output Signals and Functions Signal Name Hi-Z or Actively Driven Function QSPI Data Output (QSPI_DOUT) Configurable Serial data output from QSPI QSPI Data Input (QSPI_DIN) Serial data input to QSPI Serial Clock (QSPI_CLK) Actively driven Clock output from QSPI...
Page 422 Queued Serial Peripheral Interface (QSPI) Table 25-3. QMR Field Descriptions Field Description Master mode enable. MSTR 0 Reserved, do not use. 1 The QSPI is in master mode. Must be set for the QSPI module to operate correctly. Data output high impedance enable. Selects QSPI_DOUT mode of operation. DOHIE 0 Default value after reset.
Page 423 Queued Serial Peripheral Interface (QSPI) Figure 25-3 shows an example of a QSPI clocking and data transfer. QSPI_CLK QSPI_DOUT QSPI_DIN QSPI_CS QMR[CPOL] = 0 Chip selects are active low QMR[CPHA] = 1 A = QDLYR[QCD] QCR[CONT] = 0 B = QDLYR[DTL] Figure 25-3.
Page 424 Queued Serial Peripheral Interface (QSPI) 25.3.3 QSPI Wrap Register (QWR) IPSBAR 0x00_0348 Access: User read/write Offset: CPTQP HALT WREN WRTO CSIV ENDQP NEWQP Reset Figure 25-5. QSPI Wrap Register (QWR) Table 25-5. QWR Field Descriptions Field Description Halt transfers. Assertion of this bit causes the QSPI to stop execution of commands once it has completed execution HALT of the current command.
Page 425 Queued Serial Peripheral Interface (QSPI) Table 25-6. QIR Field Descriptions Field Description Write collision access error enable. A write collision occurs during a data transfer when the RAM entry containing WCEFB the current command is written to by the CPU with the QDR. When this bit is asserted, the write access to QDR results in an access error.
Page 426 Queued Serial Peripheral Interface (QSPI) 25.3.5 QSPI Address Register (QAR) The QAR is used to specify the location in the QSPI RAM that read and write operations affect. As shown Section 25.4.1, “QSPI RAM”, the transmit RAM is located at addresses 0x0 to 0xF, the receive RAM is located at 0x10 to 0x1F, and the command RAM is located at 0x20 to 0x2F.
Page 427 Queued Serial Peripheral Interface (QSPI) Table 25-7. QCR0–QCR15 Field Descriptions Field Description Continuous. CONT 0 Chip selects return to inactive level defined by QWR[CSIV] when a single word transfer is complete. 1 Chip selects return to inactive level defined by QWR[CSIV] only after the transfer of the queue entries (max of 16 words).
Page 428 Queued Serial Peripheral Interface (QSPI) QSPI_CSn (active-low) QSPI_CLK QSPI_DOUT QSPI_DIN QS1: QSPI_CS to QSPI_CLK QS2: QSPI_CLK to QSPI_DOUT VALID 20 ns QS3: QSPI_CLK to QSPI_DOUT HOLD 0 ns 10 ns QS4: QSPI_DIN to QSPI_CLK SETUP QS5: QSPI_DIN to QSPI_CLK HOLD 10 ns 1T1 is defined as the clock period in ns.
Page 429 Queued Serial Peripheral Interface (QSPI) The user initiates QSPI operation by loading a queue of commands in command RAM, writing transmit data into transmit RAM, and then enabling the QSPI data transfer. The QSPI executes the queued commands and sets the completion flag in the QSPI interrupt register (QIR[SPIF]) to signal their completion.
Page 430 Queued Serial Peripheral Interface (QSPI) The transmit and command RAM are user write-only. The receive RAM is user read-only. Figure 25-11 shows the RAM configuration. The RAM contents are undefined immediately after a reset. The command and data RAM in the QSPI is indirectly accessible with QDR and QAR as 48 separate locations that comprise 16 words of transmit data, 16 words of receive data, and 16 bytes of commands.
Page 431 Queued Serial Peripheral Interface (QSPI) Outbound data must be written to transmit RAM in a right-justified format. The unused bits are ignored. The QSPI copies the data to its data serializer (shift register) for transmission. The data is transmitted most significant bit first and remains in transmit RAM until overwritten by the user.
Page 432 Queued Serial Peripheral Interface (QSPI) Table 25-8. QSPI_CLK Frequency as Function of Internal Bus Clock and Baud Rate Internal Bus Clock = 66 MHz QMR [BAUD] QSPI_CLK 16.5 MHz 8.25 MHz 4.1 MHz 2.06 MHz 1.0 MHz 12.9 kHz 25.4.3 Transfer Delays The QSPI supports programmable delays for the QSPI_CS signals before and after a transfer.
Page 433 Queued Serial Peripheral Interface (QSPI) between successive transfers. If the internal bus clock is operating at a slower rate, the delay between transfers must be increased proportionately. 25.4.4 Transfer Length There are two transfer length options. The user can choose a default value of 8 bits or a programmed value of 8 to 16 bits.
Page 434 Queued Serial Peripheral Interface (QSPI) 25.5 Initialization/Application Information The following steps are necessary to set up the QSPI 12-bit data transfers and a QSPI_CLK of 4.125 MHz. The QSPI RAM is set up for a queue of 16 transfers. All four QSPI_CS signals are used in this example. 1.
Page 435: Introduction
Chapter 26 UART Modules 26.1 Introduction This chapter describes the use of the three universal asynchronous receiver/transmitters (UARTs) and includes programming examples. NOTE The designation ‘n’ is used throughout this section to refer to registers or signals associated with one of the three identical UART modules: UART0, UART1, or UART2.
Page 436 UART Modules The serial communication channel provides a full-duplex asynchronous/synchronous receiver and transmitter deriving an operating frequency from the internal bus clock or an external clock using the timer pin. The transmitter converts parallel data from the CPU to a serial bit stream, inserting appropriate start, stop, and parity bits.
Page 437 UART Modules 26.2 External Signal Description Figure 26-1 shows both the external and internal signal groups. An internal interrupt request signal is provided to notify the interrupt controller of an interrupt condition. The output is the logical NOR of unmasked UISRn bits. The interrupt level and priority are programmed in the interrupt controller.
Page 438: Memory Map/Register Definition
UART Modules 26.3 Memory Map/Register Definition This section contains a detailed description of each register and its specific function. Flowcharts in Section 26.4.6, “Programming,” describe basic UART module programming. The operation of the UART module is controlled by writing control bytes into the appropriate registers. Table 26-2 is a memory map for UART module registers.
Page 439 UART Modules Table 26-2. UART Module Memory Map (continued) ISPBAR Offset Width Register Access Reset Value Section/Page UART0 (bit) UART1 UART2 0x00_0234 UART Input Port Register (UIPn) 0xFF 26.3.12/26-16 0x00_0274 0x00_02B4 0x00_0238 UART Output Port Bit Set Command Register (UOP1n) 0x00 26.3.13/26-17 0x00_0278...
Page 440 UART Modules Table 26-3. UMR1n Field Descriptions Field Description Receiver request-to-send. Allows the UnRTS output to control the UnCTS input of the transmitting device to prevent RXRTS receiver overrun. If both the receiver and transmitter are incorrectly programmed for UnRTS control, UnRTS control is disabled for both.
Page 441 UART Modules Address: 0x00_0200 (UMR20) Access: User read/write 0x00_0240 (UMR21) 0x00_0280 (UMR22) TXRTS TXCTS Reset: After UMR1n is read or written, the pointer points to UMR2n Figure 26-5. UART Mode Register 2 (UMR2n) Table 26-4. UMR2n Field Descriptions Field Description 7–6 Channel mode.
Page 442 UART Modules Table 26-4. UMR2n Field Descriptions (continued) Field Description Transmitter clear-to-send. If both TXCTS and TXRTS are set, TXCTS controls the operation of the transmitter. TXCTS 0 UnCTS has no effect on the transmitter. 1 Enables clear-to-send operation. The transmitter checks the state of UnCTS each time it is ready to send a character.
Page 443 UART Modules Table 26-5. USRn Field Descriptions Field Description Received break. The received break circuit detects breaks that originate in the middle of a received character. However, a break in the middle of a character must persist until the end of the next detected character time. 0 No break was received.
Page 444 UART Modules Address: 0x00_0204 (UCSR0) Access: User write-only 0x00_0244 (UCSR1) 0x00_0284 (UCSR2) Reset: Figure 26-7. UART Clock Select Register (UCSRn) Table 26-6. UCSRn Field Descriptions Field Description 7–4 Receiver clock select. Selects the clock source for the receiver. 1101 Prescaled internal bus clock (f sys/2 1110 DTIN divided by 16 1111 DTIN...
Page 445 UART Modules Table 26-7 describes UCRn fields and commands. Examples in Section 26.4.2, “Transmitter and Receiver Operating Modes,” show how these commands are used. Table 26-7. UCRn Field Descriptions Field Description Reserved, should be cleared. 6–4 MISC Field (this field selects a single command) MISC Command Description...
Page 446 UART Modules Table 26-7. UCRn Field Descriptions (continued) Field Description 3–2 TC Field (This field selects a single command) Command Description Causes the transmitter to stay in its current mode: if the transmitter is enabled, it NO ACTION TAKEN remains enabled; if the transmitter is disabled, it remains disabled. Enables operation of the UART’s transmitter.
Page 447 UART Modules Address: 0x00_020C (URB0) Access: User read-only 0x00_024C (URB1) 0x00_028C (URB2) Reset: Figure 26-9. UART Receive Buffer (URBn) 26.3.7 UART Transmit Buffers (UTBn) The transmit buffers consist of the transmitter holding register and the transmitter shift register. The holding register accepts characters from the bus master if UART’s USRn[TXRDY] is set. A write to the transmit buffer clears USRn[TXRDY], inhibiting any more characters until the shift register can accept more data.
Page 448 UART Modules Table 26-8. UIPCRn Field Descriptions Field Description 7–5 Reserved Change of state (high-to-low or low-to-high transition). 0 No change-of-state since the CPU last read UIPCRn. Reading UIPCRn clears UISRn[COS]. 1 A change-of-state longer than 25–50 µs occurred on the UnCTS input. UACRn can be programmed to generate an interrupt to the CPU when a change of state is detected.
Page 449 UART Modules NOTE True status is provided in the UISRn regardless of UIMRn settings. UISRn is cleared when the UART module is reset. Address: 0x00_0214 (UISR0) Access: User read/write 0x00_0254 (UISR1) 0x00_0294 (UISR2) FFULL/ TXRDY (UISRn) RXRDY FFULL/ TXRDY (UIMRn) RXRDY Reset: Figure 26-13.
Page 450 UART Modules 26.3.11 UART Baud Rate Generator Registers (UBG1n/UBG2n) The UBG1n registers hold the MSB, and the UBG2n registers hold the LSB of the preload value. UBG1n and UBG2n concatenate to provide a divider to the internal bus clock for transmitter/receiver operation, as described in Section 26.4.1.2.1, “Internal Bus Clock Baud Rates.”...
Page 451 UART Modules Address: 0x00_0234 (UIP0) Access: User read-only 0x00_0274 (UIP1) 0x00_02B4 (UIP2) Reset: Figure 26-17. UART Input Port Register (UIPn) Table 26-12. UIPn Field Descriptions Field Description 7–1 Reserved Current state of clear-to-send. The UnCTS value is latched and reflects the state of the input pin when UIPn is read. Note: This bit has the same function and value as UIPCRn[RTS].
Page 452 UART Modules 26.4 Functional Description This section describes operation of the clock source generator, transmitter, and receiver. 26.4.1 Transmitter/Receiver Clock Source The internal bus clock serves as the basic timing reference for the clock source generator logic, which consists of a clock generator and a programmable 16-bit divider dedicated to each UART. The clock generator might not produce standard baud rates if the internal bus clock is used, so the user must enable the 16-bit divider.
Page 453 UART Modules 26.4.1.2 Calculating Baud Rates The following sections describe how to calculate baud rates. 26.4.1.2.1 Internal Bus Clock Baud Rates When the internal bus clock is the UART clocking source, it goes through a divide-by-32 prescaler and then passes through the 16-bit divider of the concatenated UBG1n and UBG2n registers. The baud-rate calculation is as follows: sys 2 ⁄...
Page 454 UART Modules UARTn UART Command Register (UCRn) UART Mode Register 1 (UMR1n) UART Mode Register 2 (UMR2n) UART Status Register (USRn) UART Transmitter Holding Register Transmit Buffer (UTBn) UnTXD Transmitter Shift Register (2 Registers) FIFO Receiver Holding Register 1 External Interface Receiver Holding Register 2 Receiver Holding Register 3...
Page 455 UART Modules If the transmitter is programmed to automatically negate UnRTS when a message transmission completes, UnRTS must be asserted manually before a message is sent. In applications in which the transmitter is disabled after transmission is complete and UnRTS is appropriately programmed, UnRTS is negated one bit time after the character in the shift register is completely transmitted.
Page 456 UART Modules programmed clock source. The lsb is received first. The data is then transferred to a receiver holding register and USRn[RXRDY] is set. If the character is less than 8 bits, the most significant unused bits in the receiver holding register are cleared. After the stop bit is detected, the receiver immediately looks for the next start bit.
Page 457 UART Modules 26.4.2.3 FIFO The FIFO is used in the UART’s receive buffer logic. The FIFO consists of three receiver holding registers. The receive buffer consists of the FIFO and a receiver shift register connected to the UnRXD (see Figure 26-20).
Page 458 UART Modules 26.4.3 Looping Modes The UART can be configured to operate in various looping modes, as shown in Figure 26-22. These modes are useful for local and remote system diagnostic functions. The modes are described in the following paragraphs and in Section 26.3, “Memory Map/Register Definition.”...
Page 459 UART Modules 26.4.3.3 Remote Loop-back Mode In remote loop-back mode, shown in Figure 26-25, the UART automatically transmits received data bit by bit on the UnTXD output. The local CPU-to-transmitter link is disabled. This mode is useful in testing receiver and transmitter operation of a remote UART. For this mode, the transmitter uses the receiver clock.
Page 460 UART Modules Master Station UnTXD ADD1 ADD2 Transmitter Enabled USRn[TXRDY] internal module select UMR1n[PM] = 11 ADD 1 ADD 2 UMR1n[PT] = 1 UMR1n[PT] = 0 UMR1n[PT] = 2 Peripheral Station UnRXD ADD1 ADD2 Receiver Enabled USRn[RXRDY] internal module select UMR1n [PM] = 11 ADD 1...
Page 461 UART Modules 26.4.5 Bus Operation This section describes bus operation during read, write, and interrupt acknowledge cycles to the UART module. 26.4.5.1 Read Cycles The UART module responds to reads with byte data. Reserved registers return zeros. 26.4.5.2 Write Cycles The UART module accepts write data as bytes only.
Page 462 UART Modules 3. Unmask appropriate bits in the core’s status register (SR) to enable interrupts. 4. If TXRDY or RXRDY are being used to generate interrupt requests, then verify that DMAREQC (in the SCM) does not also assign the UART’s TXRDY and RXRDY into DMA channels. 5.
Page 463 UART Modules To configure the UART for DMA requests: 1. Initialize the DMAREQC in the SCM to map the desired UART DMA requests to the desired DMA channels. For example; setting DMAREQC[7:4] to 1000 maps UART0 receive DMA requests to DMA channel 1;...
Page 464 UART Modules Table 26-16. UART Module Initialization Sequence (continued) Register Setting UMR2n Select the mode of operation (CMx bits). If preferred, program operation of transmitter ready-to-send (TXRTS). If preferred, program operation of clear-to-send (TXCTS bit). Select stop-bit length (SBx bits). UCRn Enable transmitter and/or receiver.
Page 465 UART Modules CHCHK CHCHK Place Channel In Local Loopback Mode Enable Transmitter Clear Status Word TxCHK Set Transmitter- Waited Transmitter Never-ready Flag Too Long? Ready? SNDCHR Send Character To Transmitter RxCHK Waited Set Receiver- Character Been Too Long? Never-ready Flag Received? Figure 26-27.
Page 466 UART Modules FRCHK RSTCHN Have Disable Framing Error? Transmitter Set Framing Restore Error Flag To Original Mode PRCHK Have Return Parity Error? Set Parity Error Flag CHRCHK Get Character From Receiver Same As Transmitted Character? Set Incorrect Character Flag Figure 26-27. UART Mode Programming Flowchart (Sheet 3 of 5) MCF52235 ColdFire®...
Page 467 UART Modules SIRQ INCH ABRKI Does Channel A IRQ Caused Receiver Have A By Beginning Character? Of A Break? Clear Change-in- Place Character Break Status Bit In D0 ABRKI1 End-of-break Return IRQ Arrived Yet? Clear Change-in- Break Status Bit Remove Break Character From Receiver FIFO Replace Return...
Page 468 UART Modules OUTCH Transmitter Ready? Send Character To Transmitter Return Figure 26-27. UART Mode Programming Flowchart (Sheet 5 of 5) MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 0 26-34 Freescale Semiconductor Preliminary...
Page 469 Chapter 27 C Interface 27.1 Introduction This chapter describes the I C module, clock synchronization, and I C programming model registers. It also provides extensive programming examples. 27.2 Overview C is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange, minimizing the interconnection between devices.
Page 470 C Interface • Software-programmable for one of 50 different serial clock frequencies • Software-selectable acknowledge bit • Interrupt-driven, byte-by-byte data transfer • Arbitration-lost interrupt with automatic mode switching from master to slave • Calling address identification interrupt • START and STOP signal generation/detection •...
Page 471 C Interface • C control register (I2CR) • C status register (I2SR) • C data I/O register (I2DR) 27.4 C System Configuration The I C module uses a serial data line (I2C_SDA) and a serial clock line (I2C_SCL) for data transfer. For C compliance, all devices connected to these two signals must have open drain or open collector outputs.
Page 472 C Interface The slave whose address matches that sent by the master pulls I2C_SDA low at the ninth serial clock (D) to return an acknowledge bit. 27.4.3 Data Transfer When successful slave addressing is achieved, the data transfer can proceed (see E in Figure 27-2) on a byte-by-byte basis in the direction specified by the R/W bit sent by the calling master.
Page 473 C Interface I2C_SCL Bit0 I2C_SDA by Transmitter Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 I2C_SDA by Receiver START Signal Figure 27-4. Acknowledgement by Receiver If the master receiver does not acknowledge the slave transmitter after a byte transmission, it means end-of-data to the slave.
Page 474 C Interface • The second example in Figure 27-6 is the master reading the slave immediately after the first byte. At the moment of the first acknowledge, the master-transmitter becomes a master-receiver and the slave-receiver becomes slave-transmitter. • In the third example in Figure 27-6, the START condition and slave address are both repeated using the repeated START signal.
Page 475 C Interface The relative priority of the contending masters is determined by a data arbitration procedure. A bus master loses arbitration if it transmits logic 1 while another master transmits logic 0. The losing masters immediately switch over to slave receive mode and stop driving I2C_SDA output (see Figure 27-7).
Page 476 C Interface Table 27-1. I C Module Memory Map IPSBAR Register Access Reset Value Section/Page Offset 0x00_0300 C Address Register (I2ADR) 0x00 27.5.1/27-8 0x00_0304 C Frequency Divider Register (I2FDR) 0x00 27.5.2/27-8 0x00_0308 C Control Register (I2CR) 0x00 27.5.3/27-9 0x00_030C C Status Register (I2SR) 0x81 27.5.4/27-10 0x00_0310...
Page 477 C Interface Table 27-3. I2FDR Field Descriptions Field Description 7–6 Reserved, should be cleared. 5–0 C clock rate. Prescales the clock for bit-rate selection. The serial bit clock frequency is equal to the internal bus clock divided by the divider shown below. Due to potentially slow I2C_SCL and I2C_SDA rise and fall times, bus signals are sampled at the prescaler frequency.
Page 478 C Interface Table 27-4. I2CR Field Descriptions Field Description C enable. Controls the software reset of the entire I C module. If the module is enabled in the middle of a byte transfer, slave mode ignores the current bus transfer and starts operating when the next START condition is detected. Master mode is not aware that the bus is busy;...
Page 479 C Interface Table 27-5. I2SR Field Descriptions Field Description C Data transferring bit. While one byte of data is transferred, ICF is cleared. 0 Transfer in progress 1 Transfer complete. Set by the falling edge of the ninth clock of a byte transfer. C addressed as a slave bit.
Page 480: I 2 C Programming Examples
C Interface Address: 0x00_0310 (I2DR) Access: User read/write DATA Reset: Figure 27-13. I C Data I/O Register (I2DR) Table 27-6. I2DR Field Description Field Description 7–0 C data. In master transmit mode, when data is written to this register, a data transfer is initiated. The most DATA significant bit is sent first.
Page 481 C Interface I2SR = 0x0 I2CR = 0x0 27.6.2 Generation of START After completion of the initialization procedure, serial data can be transmitted by selecting the master transmitter mode. On a multiple-master bus system, I2SR[IBB] must be tested to determine whether the serial bus is free.
Page 482 C Interface The following is an example of a software response by a master transmitter in the interrupt routine (see Figure 27-14). I2SR LEA.L I2SR,-(A7) ;Load effective address BCLR.B #1,(A7)+ ;Clear the IIF flag MOVE.B I2CR,-(A7) ;Push the address on stack, BTST.B #5,(A7)+ ;check the MSTA flag BEQ.S SLAVE...
Page 483 C Interface 27.6.5 Generation of Repeated START After the data transfer, if the master still wants the bus, it can signal another START followed by another slave address without signaling a STOP, as in the following example. RESTART MOVE.B I2CR,-(A7) ;Repeat START (RESTART) BSET.B #2, (A7) MOVE.B (A7)+, I2CR...
Page 484 C Interface Clear Master Mode? TX/Rx Arbitration Lost? Last Byte Clear IAL Transmitted Last RXAK= 0 IAAS=1 IAAS=1 Byte to be Read Address Data Cycle Cycle End of 2nd Last (Read) SRW=1 Tx/Rx ADDR Cycle Byte to be Read? (Master RX) (WRITE) ACK from Generate...
Page 485: Analog-To-Digital Converter (Adc)
Chapter 28 Analog-to-Digital Converter (ADC) 28.1 Introduction The analog-to-digital converter (ADC) consists of two separate and complete ADCs, each with their own sample and hold circuits. The converters share a common voltage reference and common digital control module. 28.2 Features The ADC’s characteristics include the following: •...
Page 486: Functional Description
Analog-to-Digital Converter (ADC) Voltage REFH Reference Circuit REFL Digital Output Storage Registers Scaling & Cyclic Converter A • Sample/Hold • • Scaling & Cyclic Converter B SYNCx Controller Bus Interface Data Figure 28-1. Dual ADC Block Diagram 28.4 Functional Description The ADC’s conversion process is either initiated by a sync signal from one of two input pins (SYNCx) or by writing 1 to a STARTn bit.
Page 487 Analog-to-Digital Converter (ADC) HILIM[0:3] ADC0 > ADC1 ADC2 LOLIM[0:3] Test Data (From CPU) < End of Scan A Interrupt Zero Crossing Logic ADCA RSLT[0:3] V– – Zero Crossing REFL OFFST[0:3] or Error Limit Channel Select Interrupt Single-Ended vs Differential HILIM[4:7] Crossbars allow AN0-3 to be stored in samples 4-7, >...
Page 488 Analog-to-Digital Converter (ADC) HILIM[0:3] ADC0 > ADC1 ADC2 LOLIM[0:3] Test Data (From CPU) < End of Scan A Interrupt Zero Crossing Logic ADCA RSLT[0:3] V– – Zero Crossing REFL OFFST[0:3] or Error Limit Channel Select Interrupt Single-Ended vs Differential HILIM[4:7] Crossbars do >...
Page 489 Analog-to-Digital Converter (ADC) 28.4.1 Input MUX Function The input MUX function is shown in Figure 28-4. The channel select and single ended vs. differential switches are indirectly controlled based on settings within the LIST1, LIST2, and SDIS registers, and the CHNCFG field of the CTRL1 register.
Page 490 Analog-to-Digital Converter (ADC) MUX Configuration for Single-Ended MUX Configuration for Differential Channel Channel Select Select Converter A Converter A Interface Interface Function Function V– V– REFL REFL Single-Ended Differential Channel Select Channel Select Single-Ended vs Single-Ended vs Differential Differential Channel Channel Select Select...
Page 491 Analog-to-Digital Converter (ADC) ADCA Cyclic ADC Core Interface RSD#1 RSD#2 V– V– θ θ Function REFL Channel Select Single-Ended vs Differential ADCB Cyclic ADC Core Interface RSD#1 RSD#2 V– V– θ θ Function REFL Channel Select Single-Ended vs Differential Figure 28-5. Cyclic ADC — Top Level Block Diagram The input mode for a given sample is determined by the CHNCFG field of the CTRL1 register.
Page 492 Analog-to-Digital Converter (ADC) – REFLO × × 4095 -------------------------------------------- - SingleEndedValue round – REFH REFLO VIN = Applied voltage at the input pin VREFH and VREFL = Voltage at the external reference pins on the device (typically VREFH = VSSA and VREFL = VDDA) Note: The 12-bit result is rounded to the nearest LSB.
Page 493 Analog-to-Digital Converter (ADC) Potential REFH – AN– Differential buffer will center about mid-point NOTE: Normally, V REFL set to V = 0V AN– Center tap held at (V ) /2 REFH REFL Figure 28-6. Typical Connections for Differential Measurements 28.4.3 ADC Data Processing As shown in Figure...
Page 494 Analog-to-Digital Converter (ADC) HILIM[0:3] > End of LOLIM[0:3] Scan A Test Data Interrupt (From CPU) < Zero Crossing Logic ADC0 ADCA RSLT[0:3] ADC1 V– ADC2 – OFFST[0:3] Zero Crossing or Error Limit Interrupt HILIM[4:7] > End of LOLIM[4:7] Scan B Interrupt <...
Page 495 Analog-to-Digital Converter (ADC) more than one SAMPLE slot. Scanning is initiated when the START0 bit is written as 1 or, if the SYNC0 bit is 1, when the SYNC0 input goes high. A scan ends when the first disabled sample slot is encountered in the SDIS register.
Page 496 Analog-to-Digital Converter (ADC) Loop scan modes automatically restart a scan as soon as the previous scan completes. In the loop sequential mode, up to 8 samples are captured in each loop, and the next scan starts immediately after the completion of the previous scan. In loop parallel scan modes, both converters restart together if SIMULT=1 and restart independently if SIMULT=0.
Page 497 Analog-to-Digital Converter (ADC) — The ADC’s clock is enabled (ADC=1 in the SIM module’s SIM_PCE register); — Either the relaxation oscillator must be enabled for 8-MHz operation or the external oscillator clock must be running at 8 MHz in this mode. In auto standby mode, the ADC uses the conversion clock when active and the100 kHz Standby clock when idle.
Page 498 Analog-to-Digital Converter (ADC) mode will automatically reduce current levels until active and then impose a PUDELAY wait to allow current levels to rise from standby to normal levels. When starting up using auto power-down mode, first use the normal mode startup procedure. Before starting scan operations, set PUDELAY to the large power-up value.
Page 499 Analog-to-Digital Converter (ADC) 28.4.7.2 Description of Clock Operation As shown in Figure 28-8, the conversion clock is the primary source for the ADC clock and is always selected as the ADC clock when conversions are in process. The DIV value in the CTRL2 register should be configured so the conversion clock frequency falls between 100 kHz and 5.0 MHz.
Page 500 Analog-to-Digital Converter (ADC) In a parallel scan mode when SIMULT=0, both ADCs operate using independent STARTn bits and SYNCn signals. As shown in Figure 28-10, the first scan started will be re-synchronized to the system clock, but the second scan may wait up to 5 additional system clocks before starting. Also, note that which converter is synchronized to the system clock depends on which convert first starts to use the ADC.
Page 501 Analog-to-Digital Converter (ADC) ADC Conversion Clock Resynchronized ADCA Scan Start START1 Asserted ADCB Scan Should Start Here START0 ADCB Scan Start Asserted System Clock Wait for next rising edge of ADC Old ADC Clock Conversion Clock ADC Clock After Resynchronization ADCA Scan ADCB Scan Delay in start because ADC Clock cannot...
Page 502: Register Definitions
Analog-to-Digital Converter (ADC) is as noise-free as possible. Any noise residing on the V voltage is directly transferred to the REFH REFH digital result. Figure 28-11 illustrates the internal workings of the ADC voltage reference circuit. V must be noise REFH filtered;...
Page 503 Analog-to-Digital Converter (ADC) Table 28-5. ADC Register Summary IPSBAR Offset Acronym Register Name Access Type Location 0x0019_0000 CTRL1 Control Register 1 Read/Write Section 28.5.1 0x0019_0002 CTRL2 Control Register 2 Read/Write Section 28.5.2 Section 28.5.3 0x0019_0004 ADZCC Zero Crossing Control Register Read/Write Section 28.5.4 0x0019_0006...
Page 504 Analog-to-Digital Converter (ADC) Register Add. Offset Acronym SYNC LLMTI EOSIE HLMTI CTRL $0019_0000 ZCIE CHNCFG SMODE STOP0 START CTRL Simultaneous Mode $0019_0002 CTRL SYNC EOSIE STOP1 SIMULT START Parallel Mode $0019_0004 ADZCC ZCE7 ZCE6 ZCE5 ZCE4 ZCE3 ZCE2 ZCE1 ZCE0 ADLST1 $0019_0006 SAMPLE3...
Page 505 Analog-to-Digital Converter (ADC) EOSI EOSI CIP0 CIP1 LLMTI HLMT RDY7 RDY6 RDY5 RDY4 RDY3 RDY2 RDY1 RDY0 $0019_0006 ADSTAT $0019_0007 ADLSTAT HLS7 HLS6 HLS5 HLS4 HLS3 HLS2 HLS1 HLS0 LLS7 LLS6 LLS5 LLS4 LLS3 LLS2 LLS1 LLS0 $0019_0008 ADZCSTAT ZCS7 ZCS6 ZCS5 ZCS4...
Page 506 Analog-to-Digital Converter (ADC) 28.5.1.2 STOP 0 (STOP0)—Bit 14 When STOP0 is asserted, the current scan is stopped and no further scans can start. Any further SYNC0 input pulses (see SYNC0 bit 12) or writes to the START0 bit are ignored until the STOP0 bit is cleared. After the ADC is in stop mode, the result registers can be modified by the processor.
Page 507 Analog-to-Digital Converter (ADC) 28.5.1.6 Zero Crossing Interrupt Enable (ZCIE)—Bit 10 This bit enables the zero crossing interrupt if the current result value has a sign change from the previous result as configured by the ADZCC register. • 0 = Interrupt disabled •...
Page 508 Analog-to-Digital Converter (ADC) 28.5.1.10 Scan Mode Control (SMODE)—Bits 2-0 SMODE controls the scan mode of the ADC module. All scan modes make use of the 8 sample slots defined by the ADLST1 and ADLST2 registers. A scan is the process of stepping through these sample slots, converting the analog input indicated by that slot, and storing the result.
Page 509 Analog-to-Digital Converter (ADC) • 011= Loop parallel Upon an initial start or enabled sync pulse, converter A will capture Samples 0-3, and converter B will capture Samples 4-7. Each time a converter completes its current scan, it immediately restarts its scan sequence. This continues until a STOPn bit is asserted. While a loop is running, any additional start commands or sync pulses are ignored.
Page 510 Analog-to-Digital Converter (ADC) 28.5.2.2 Clock Divisor Select (DIV)—Bits 4–0 The divider circuit generates the ADC clock by dividing the system clock by 2 × (DIV[4:0]+1). A DIV value must be chosen so the ADC clock does not exceed 5.0 MHz. The following table shows ADC clock frequency based on the value of DIV for several configurations.
Page 511 Analog-to-Digital Converter (ADC) 28.5.3.2 Stop (STOP1)—Bit 14 During parallel scan modes when SIMULT=0, setting STOP1 stops parallel scans in the B converter and prevents new ones from starting. Any further SYNC1 input pulses (please see SYNC1 bit) or writes to the START1 bit are ignored until the STOP1 bit is cleared.
Page 512 Analog-to-Digital Converter (ADC) • 0 = Interrupt disabled • 1 = Interrupt enabled 28.5.3.7 Simultaneous Mode (SIMULT)—Bit 5 This bit only affects parallel scan modes. When SIMULT=1 (default value) parallel scans operate in simultaneous mode. The scans in the A and B converter operate simultaneously and always result in pairs of simultaneous conversions in the A and B converter.
Page 513 Analog-to-Digital Converter (ADC) 28.5.4 Zero Crossing Control Register (ADZCC) The ADC zero crossing control (ADZCC) register provides the ability to monitor the selected channels and determine the direction of zero crossing triggering the optional interrupt. Zero crossing logic monitors only the sign change between current and previous sample. The ZCE0 bit monitors the sample stored in ADRSLT0, ZCE1 bit monitors ADRSLT1, and ZCE7 bit monitors ADRSLT7.
Page 514 Analog-to-Digital Converter (ADC) IPSBAR 0x19_0004 (ADLST2) Access: read/write Offset: SAMPLE7 SAMPLE6 SAMPLE5 SAMPLE4 Reset Figure 28-18. Channel List 2 (ADLST2) Register 28.5.5.1 Reserved—Bits 15, 11, 7 and 3 These bits are reserved or are not implemented. They are read as 0 and cannot be modified by writing. 28.5.5.2 SAMPLE n (SAMPLE4)—Bits 2, 1, and 0 The value of the SAMPLEn field is used to select the input channel to be sampled.
Page 515 Analog-to-Digital Converter (ADC) When inputs are configured as differential pairs, a reference to either analog input in a differential pair by a sample slot implies a differential measurement on the pair. The details of single ended and differential measurement are described under the CHNCFG field. Sample slots are disabled using the SDIS register. 28.5.6 Sample Disable Register (SDIS) This register is an extension to the ADLST1and ADLST2, providing the ability to enable only the desired...
Page 516 Analog-to-Digital Converter (ADC) 28.5.6.2 Disable Sample (DSn)—Bits 7–0 The respective SAMPLEn field can be enabled or disabled where n = 0–7. • 0 = Enable SAMPLEn • 1 = Disable SAMPLEn and all subsequent samples. Which samples are actually disabled will depend on the conversion mode, sequential/parallel, and the value of SIMULT.
Page 517 Analog-to-Digital Converter (ADC) 28.5.7.3 Reserved—Bit 13 This bit is reserved or not implemented. It is read as 0 and cannot be modified by writing. 28.5.7.4 End of Scan Interrupt 1 (EOSI1)—Bit 12 This bit indicates whether a scan of analog inputs have been completed since the last read of the STAT register or a reset.
Page 518 Analog-to-Digital Converter (ADC) The LLMTI bit is cleared by writing 1 to all active LLS[7:0] bits in the ADLSTAT register. • 0 = No low limit interrupt request • 1 = Low limit exceeded, IRQ pending if LLMTIE is set 28.5.7.8 High Limit Interrupt (HLMTI)—Bit 8 If any high limit (HILIMn) register is enabled by having a value other than 0x7FF8, high limit checking...
Page 519 Analog-to-Digital Converter (ADC) 28.5.8 Limit Status Register (ADLSTAT) The ADC limit status (ADLSTAT) register latches in the result of the comparison between the result of the sample in the ADRSLTn register and the respective limit register, HILIMn or LOLIMn. For example, if the result for ADRSLT0 is greater than the value programmed into the HILIM0, then set the HLS0 bit to 1.
Page 520 Analog-to-Digital Converter (ADC) 28.5.9.2 Zero Crossing Status (ZCS[7:0])—Bits 7–0 The zero crossing condition is determined by examining the ADC value after it has been adjusted by the offset for the result register. Please see Figure 28-7. Each bit of the register is cleared by writing 1 to that register bit.
Page 521 Analog-to-Digital Converter (ADC) 28.5.10.1 Sign Extend (SEXT)—Bit 15 SEXT is the sign-extend bit of the result. When the SEXT bit is set to 1, it implies a negative result. When the SEXT bit is set to 0, it implies a positive result. If only positive results are required, then the respective ADC Offset (ADOFSn) register must be set to a value of 0.
Page 522 Analog-to-Digital Converter (ADC) IPSBAR 0x19_0011 - 0x19_0018 (LOLIM0–7) Access: read/write Offset: LLMT Reset Figure 28-25. ADC High Limit Register 0—Address: ADC_BASE + $32 ADC High Limit Register 1—Address: ADC_BASE + $34 ADC High Limit Register 2—Address: ADC_BASE + $36 ADC High Limit Register 3—Address: ADC_BASE + $38 ADC High Limit Register 4—Address: ADC_BASE + $3A...
Page 523 Analog-to-Digital Converter (ADC) IPSBAR 0x19_0021 - 0x19_0028 (ADOFS0–7) Access: read/write Offset: OFFSET Reset Figure 28-27. Offset 0-7 (ADOFS0-7) Registers The offset value is subtracted from the ADC result. In order to obtain unsigned results, the respective offset register should be programmed with a value of $0000, thus giving a result range of $0000 to $7FF8. 28.5.13 Power Control Register (POWER) This register controls the power management features of the ADC module.
Page 524 Analog-to-Digital Converter (ADC) IPSBAR 0x19_0029 (POWER) Access: read/write Offset: PSTS2 PSTS1 PSTS0 PUDELAY Reset Figure 28-28. Power Control (POWER) Register 28.5.13.1 Auto Standby (ASB)—Bit 15 The ASB bit selects auto standby mode. ASB is ignored if APD is 1. When the ADC is idle, auto standby mode selects the standby clock as the ADC clock source and puts the converters into standby current mode.
Page 525 Analog-to-Digital Converter (ADC) • 0 = ADC converter A is currently powered up • 1 = ADC converter A is currently powered down 28.5.13.6 Power-Up Delay (PUDELAY)—Bits 9–4 This 6-bit field determines the number of ADC clocks provided to power-up an ADC converter (after setting PD0 or PD1 to 0) before allowing a scan to start.
Page 526 Analog-to-Digital Converter (ADC) 28.5.13.9 Manual Power-Down for Converter B (PD1)—Bit 1 This bit forces ADC converter B to power-down. • 0 = Power-up ADC converter B • 1 = Power-down ADC converter B Asserting PD1 powers down converter B immediately. The results of a scan using converter B will be invalid while PD1 is asserted.
Page 527 Analog-to-Digital Converter (ADC) 28.5.14.1 Select V Source (SEL_VREFH)—Bit 15 REFH This bit selects the source of the V reference for conversions. REFH • 0 = Internal VR • 1 = AN2 28.5.14.2 Select V Source (SEL_VREFL)—Bit 14 REFL This bit selects the source of the V reference for conversions.
Page 528 Analog-to-Digital Converter (ADC) MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 0 28-44 Freescale Semiconductor Preliminary...
Page 529: Pulse Width Modulation (Pwm) Module
Chapter 29 Pulse Width Modulation (PWM) Module 29.1 Introduction This chapter describes the configuration and operation of the pulse width modulation (PWM) module. It includes a block diagram, programming model, and functional description. 29.1.1 Overview The PWM module shown in Figure 29-1, generates a synchronous series of pulses having programmable period and duty cycle.
Page 530: Memory Map/Register Definition
Pulse Width Modulation (PWM) Module Main features include the following: • Double-buffered period and duty cycle • Left- or center-aligned outputs • Eight independent PWM modules. Notice that only the four odd PWM channel outputs are available on the device. The even channels can be used for concatenation purposes to generate 16-bit PWM for the odd channels.
Page 531 Pulse Width Modulation (PWM) Module 32-bit access to any of these registers will result in a bus transfer error (see Section 11.2.7, “SCM Interrupt Status Register (SCMISR)”). 29.2.1 PWM Enable Register (PWME) Each PWM channel has an enable bit (PWMEn) to start its waveform output. While in run mode, if all four PWM output channels are disabled (PWME[7:0] = 0), the prescaler counter shuts off for power savings.
Page 532 Pulse Width Modulation (PWM) Module Address: 0x001B_0001 (PWMPOL) Access: User Read/Write PPOL7 PPOL5 PPOL3 PPOL1 Reset: Figure 29-3. PWM Polarity Register (PWMPOL) Table 29-3. PWMPOL Field Descriptions Field Description 7,5,3,1 PWM channel n polarity. PPOLn 0 PWM channel n output is low at the beginning of the period, then goes high when the duty count is reached 1 PWM channel n output is high at the beginning of the period, then goes low when the duty count is reached 6,4,2,0 Reserved, should be cleared.
Page 533 Pulse Width Modulation (PWM) Module Table 29-4. PWMCLK Field Descriptions Field Description 7,5,3,1 PWM channel n clock select. Selects between one of two clock sources for each PWM channel. See Section 29.2.4, PCLKn “PWM Prescale Clock Select Register (PWMPRCLK)” Section 29.2.7, “PWM Scale A Register (PWMSCLA)” more information on how the different clock rates are generated.
Page 534 Pulse Width Modulation (PWM) Module Table 29-5. PWMPRCLK Field Descriptions (continued) Field Description Reserved, should be cleared. 2–0 Clock A prescalar select. These three bits control the rate of Clock A which can be used for PWM channels 1 and 5. PCKA PCKA Clock A Rate...
Page 535 Pulse Width Modulation (PWM) Module Address: 0x001B_0005 (PWMCTL) Access: User Read/Write CON67 CON45 CON23 CON01 PSWAI PFRZ Reset: Figure 29-7. PWM Control Register (PWMCTL) Table 29-7. PWMCTL Field Descriptions Field Description Concatenates PWM channels 6 and 7 to form one 16-bit PWM channel. CON67 0 Channels 6 and 7 are separate 8-bit PWMs.
Page 536 Pulse Width Modulation (PWM) Module Address: 0x001B_0008 (PWMSCLA) Access: User Read/Write SCALEA Reset: Figure 29-8. PWM Scale A Register (PWMSCLA) Table 29-8. PWMSCLA Field Descriptions Field Description 7–0 Part of divisor used to form Clock SA from Clock A. SCALEA SCALEA Value 0x00...
Page 537 Pulse Width Modulation (PWM) Module Table 29-9. PWMSCLB Field Descriptions Field Description 7–0 Divisor used to form Clock SB from Clock B. SCALEB SCALEB Value 0x00 0x01 0x02 0xFF 29.2.9 PWM Channel Counter Registers (PWMCNTn) Each channel has a dedicated 8-bit up/down counter that runs at the rate of the selected clock source, PWMCLK[PCLKn].
Page 538 Pulse Width Modulation (PWM) Module Table 29-10. PWMCNTn Field Descriptions Field Description 7–0 Current value of the PWM up counter. Resets to zero when written. COUNT 29.2.10 PWM Channel Period Registers (PWMPERn) The PWM period registers determine the period of the associated PWM channel. Refer to Section 29.3.2.3, “PWM Period and Duty”...
Page 539 Pulse Width Modulation (PWM) Module For boundary case programming values (e.g. PWMDTYn = 0x00 or PWMDTYn > PWMPERn), refer to Section Section 29.3.2.8, “PWM Boundary Cases.” Address: 0x001B_001C (PWMDTY0) Access: User Read/Write 0x001B_001D (PWMDTY1) 0x001B_001E (PWMDTY2) 0x001B_001F (PWMDTY3) 0x001B_0020 (PWMDTY4) 0x001B_00241 (PWMDTY5) 0x001B_0022 (PWMDTY6) 0x001B_0023 (PWMDTY7)
Page 540: Functional Description
Pulse Width Modulation (PWM) Module Table 29-13. PWMSDN Field Descriptions Field Description PWM interrupt flag. Any change in state of PWM7IN will be flagged by setting this bit. The flag is cleared by writing a ‘1’ to it. Writing ‘0’ has no effect. 0 No change in PWM7IN input 1 Change in PWM7IN input PWM interrupt enable.
Page 541 Pulse Width Modulation (PWM) Module PCLR0 Clock to PWM0 Clock to PWM1 PCLR1 Clock SA PCLR4 Clock to ÷2 PWMSCLA PWM4 PWMPRCLK [PCKA] Clock to PWM5 Clock A Clock PCLR5 PCLR2 Internal Bus Clock SB Clock (f sys/ Clock to ÷2 PWM2 PWMSCLB...
Page 542 Pulse Width Modulation (PWM) Module 29.3.1.2 Scaled Clock (SA or SB) The scaled A (SA) and scaled B (SB) clocks use clock A and B respectively as inputs, divide it further with a user programmable value, then divide this by 2. The rates available for clock SA are programmable to run at clock A divided by 2, 4,..., or 512.
Page 543 Pulse Width Modulation (PWM) Module Clock Source From Figure 29-14 PWMDTYn PWMCNTn PWMOUTn PWMEn PPOLn PWMPERn PWMCAE = 1 PWMCAE = 0 Figure 29-15. PWM Timer Channel Block Diagram 29.3.2.1 PWM Enable Each PWM channel has an enable bit (PWMEn) to start its waveform output. When any of the PWMEn bits are set (PWMEn=1), the associated PWM output signal is enabled immediately.
Page 544 Pulse Width Modulation (PWM) Module and/or period values to be latched. In addition, because the counter is readable, it is possible to know where the count is with respect to the duty value, and software can be used to make adjustments. When forcing a new period or duty into effect immediately, an irregular PWM cycle can occur.
Page 545 Pulse Width Modulation (PWM) Module 29.3.2.5 Left-Aligned Outputs The PWM timer provides the choice of two types of outputs: left- or center-aligned. They are selected with the PWMCAE[CAEn] bits. If the CAEn bit is cleared, the corresponding PWM output will be left-aligned. In left-aligned output mode, the 8-bit counter is configured as an up counter only.
Page 546 Pulse Width Modulation (PWM) Module The output waveform generated is below: E = 2.5ns DUTY CYCLE = 75% PERIOD = ns Figure 29-17. PWM Left-Aligned Output Example Waveform 29.3.2.6 Center-Aligned Outputs For center-aligned output mode selection, set the PWMCAE[CAEn] bit and the corresponding PWM output will be center-aligned.
Page 547 Pulse Width Modulation (PWM) Module The PWMn duty cycle (high time as a percentage of period) is expressed as: PWMDTYn ⎛ ⎞ × Duty Cycle 1 PWMPOL PPOLn – – 100% ------------------------------- Eqn. 29-10 ⎝ ⎠ PWMPERn 29.3.2.6.1 Center-Aligned Output Example As an example of a center-aligned output, consider the following case: Clock source = internal bus clock, where internal bus clock = 40 MHz (2.5 ns period) PPOLn = 0, PWMPERn = 4, PWMDTYn = 1...
Page 548 Pulse Width Modulation (PWM) Module Clock Source 7 High PWMCNT6 PWMCNT7 Period/Duty Compare PWMOUT7 Clock Source 5 High PWMCNT4 PWMCNT5 Period/Duty Compare PWMOUT5 Clock Source 3 High PWMCNT2 PWMCNT3 Period/Duty Compare PWMOUT3 Clock Source 1 High PWMCNT0 PWMCNT1 Period/Duty Compare PWMOUT1 Figure 29-20.
Page 549 Pulse Width Modulation (PWM) Module Table 29-16. PWM Boundary Cases PWMDTYn PWMPERn PPOLn PWMn Output 0x00 >0x00 Always Low (indicates no duty) 0x00 >0x00 Always High (indicates no duty) 0x00 Always High (indicates no period) 0x00 Always Low (indicates no period) ≥...
Page 550 Pulse Width Modulation (PWM) Module MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 0 29-22 Freescale Semiconductor Preliminary...
Page 551: Introduction
Chapter 30 FlexCAN 30.1 Introduction The FlexCAN is a communication controller implementing the controller area network (CAN) protocol, an asynchronous communications protocol used in automotive and industrial control systems. It is a high speed (1 Mbps), short distance, priority-based protocol that can communicate using a variety of mediums (such as fiber optic cable or an unshielded twisted pair of wires).
Page 552 FlexCAN Control Interrupt Request Serial Buffers Tx Shifter Data Rx Shifter Buffer 0 Transparent to User • • 16 Transmit/Receive • Data • • • Message Buffers • Buffer 13 Mask 14 Buffer 14 • Buffer 15 • • • •...
Page 553 FlexCAN 30.1.2 Features Following are the main features of the FlexCAN module: • Full implementation of the CAN protocol specification version 2.0B — Standard data and remote frames (up to 109 bits long) — Extended data and remote frames (up to 127 bits long) —...
Page 554 FlexCAN conditions exists, the FlexCAN waits for the completion of all internal activity such as arbitration, matching, move-in, and move-out. When this happens, the following events occur: • The FlexCAN stops transmitting/receiving frames. • The prescaler is disabled, thus halting all CAN bus communication. •...
Page 555: External Signal Description
FlexCAN 30.1.3.5 Listen-only Mode In listen-only mode, transmission is disabled, all error counters are frozen and the module operates in a CAN error passive mode. Only messages acknowledged by another CAN station will be received. If FlexCAN detects a message that has not been acknowledged, it will flag a BIT0 error (without changing the REC), as if it was trying to acknowledge the message.
Page 556 FlexCAN Table 30-1. FlexCAN Memory Map (continued) IPSBAR OffsetAddres Affected Affected Width Register by Hard by Soft Access Reset Value Section/Page (bits) Reset Reset FlexCAN 0x1C_0FC02_ Interrupt Mask Register (IMASK) 0x0000_0000 30.3.7/30-16 0028 0x1C_0FC02_ Interrupt Flag Register (IFLAG) 0x0000_0000 30.3.8/30-16 0030 0x1C_0FC02_ Message Buffers 0–15 (MB0–15)
Page 557 FlexCAN Table 30-2. CANMCR Field Descriptions Field Description Module disable. This bit controls whether FlexCAN is enabled or not. When disabled, FlexCAN shuts down the MDIS FlexCAN clocks that drive the CAN interface and Message Buffer sub-module. This is the only bit in CANMCR not affected by soft reset.
Page 558 FlexCAN Table 30-2. CANMCR Field Descriptions (continued) Field Description Low power mode acknowledge. Indicates that FlexCAN is disabled. Disabled mode cannot be entered until all LPMACK current transmission or reception processes have finished, so the CPU can poll the LPMACK bit to know when the FlexCAN has actually entered low power mode.
Page 559 FlexCAN Table 30-3. CANCTRL Field Descriptions Field Description 31–24 Prescaler division factor. Defines the ratio between the clock source frequency (set by CLK_SRC bit) and the serial PRESDIV clock (S clock) frequency. The S clock period defines the time quantum of the CAN protocol. For the reset value, the S clock frequency is equal to the clock source frequency.
Page 560 FlexCAN Table 30-3. CANCTRL Field Descriptions (continued) Field Description Bus off recovery mode. Defines how FlexCAN recovers from bus off state. If this bit is cleared, automatic recovering BOFFREC from bus off state occurs according to the CAN Specification 2.0B. If the bit is set, automatic recovering from bus off is disabled and the module remains in bus off state until the bit is cleared by the user.
Page 561 FlexCAN for the fact that the data will take some time to be actually written to the register. If desired, software can poll the register to discover when the data was actually written. IPSBAR 0x1C_0FC02_0008 (TIMER) Access: User read/write OffsetAd dress: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...
Page 562 FlexCAN Table 30-5. Mask Examples for Normal/Extended Messages (continued) Base ID Extended ID Match ID28....ID18 ID17........ID0 Rx_Msg in 1 1 1 1 1 1 1 1 0 0 1 Rx_Msg in 1 1 1 1 1 1 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 Rx_Msg in 0 1 1 1 1 1 1 1 0 0 0...
Page 563 FlexCAN Writing to the ERRCNT register while in freeze mode is an indirect operation. The data is first written to an auxiliary register, then an internal request/acknowledge procedure across clock domains is executed. All this is transparent to the user, except for the fact that the data will take some time to be actually written to the register.
Page 564 FlexCAN Table 30-7. ERRCNT Field Descriptions Field Description 31–16 Reserved, should be cleared. 15–8 Receive error counter. Indicates current number of receive errors. RXECTR 7–0 Transmit error counter. Indicates current number of transmit errors. TXECTR 30.3.6 FlexCAN Error and Status Register (ERRSTAT) ERRSTAT reflects various error conditions, some general status of the device, and is the source of three interrupts to the CPU.
Page 565 FlexCAN Table 30-8. ERRSTAT Field Descriptions (continued) Field Description Acknowledge error. Indicates whether an acknowledgment has been correctly received for a transmitted message. ACKERR 0 No ACK error was detected since the last read of this register. 1 An ACK error was detected since the last read of this register. Cyclic redundancy check error.
Page 566 FlexCAN 30.3.7 Interrupt Mask Register (IMASK) IMASK contains one interrupt mask bit per buffer. It enables the CPU to determine which buffer will generate an interrupt after a successful transmission/reception (that is, when the corresponding IFLAG bit is set). IPSBAR 0x1C_0FC02_0028 (IMASK) Access: User read/write OffsetAd...
Page 567 FlexCAN Table 30-10. IFLAG Field Descriptions Field Description 31–16 Reserved, should be cleared. 15–0 Buffer interrupt flag. Indicates a successful transmission/reception for the corresponding message buffer. If the BUFnI corresponding IMASK bit is set, an interrupt request will be generated. The user must write a 1 to clear an interrupt flag;...
Page 568 FlexCAN The message buffer structure used by the FlexCAN module is shown in Figure 30-13. Both standard and extended frames used in the CAN Specification Version 2.0, Part B are represented. A standard frame is represented by the 11-bit standard identifier, and an extended frame is represented by the combined 29-bits of the standard identifier (11 bits) and the extended identifier (18 bits).
Page 569 FlexCAN Table 30-11. Message Buffer Field Descriptions (continued) Field Description Standard frame identifier: In standard frame format, only the 11 most significant bits (28 to 18) are used for frame identification in both receive and transmit cases. The 18 least significant bits are ignored. 28–0 Extended frame identifier: In extended frame format, all bits (both the 11 bits of the standard frame identifier and the 18 bits of the extended frame identifier) are used for frame identification in both receive and transmit cases.
Page 570: Functional Overview
FlexCAN Table 30-13. Message Buffer Code for Tx Buffers Code After Initial Tx MBn[RTR] Successful Description Code Transmission 1000 — INACTIVE: Message buffer not ready for transmit and will participate in the arbitration process. 1100 1000 Data frame to be transmitted once, unconditionally. After transmission, the MB automatically returns to the INACTIVE state.
Page 571 FlexCAN 30.4.1 Transmit Process The CPU prepares or changes an MB for transmission by writing the following: 1. Control/status word to hold Tx MB inactive (CODE = 1000) 2. ID word 3. Data bytes 4. Control/status word (active CODE, LENGTH) NOTE The first and last steps are mandatory.
Page 572 FlexCAN is transmitted according to the CAN protocol rules. FlexCAN transmits up to 8 data bytes, even if the data length code (DLC) value is bigger. Refer to Section 30.4.5.1, “Serial Message Buffers (SMBs),” for more information on serial message buffers. 30.4.3 Receive Process The CPU prepares or changes an MB for frame reception by writing the following:...
Page 573 FlexCAN Note that the received identifier field is always stored in the matching MB, thus the contents of the ID field in an MB may change if the match was due to masking. 30.4.3.1 Self-Received Frames Self-received frames are frames that are sent by the FlexCAN and received by itself. The FlexCAN sends a frame externally through the physical layer onto the CAN bus, and if the ID of the frame matches the ID of the FlexCAN MB, then the frame will be received by the FlexCAN.
Page 574 FlexCAN 30.4.5.2 Message Buffer Deactivation If the CPU wants to change the function of an active MB, the recommended procedure is to put the module into freeze mode and then change the CODE field of that MB. This is a safe procedure because the FlexCAN waits for pending CAN bus and MB moving activities to finish before entering freeze mode.
Page 575 FlexCAN 3. If a receive frame with a matching ID is received during the time the message buffer is locked, the receive frame will not be immediately transferred into that message buffer, but will remain in the SMB. There is no indication when this occurs. 4.
Page 576 FlexCAN considered as a normal Tx MB, with no higher priority. The data length of this frame is independent of the data length code (DLC) field in the remote frame that initiated its transmission. 30.4.6.2 Overload Frames Overload frame transmissions are not initiated by the FlexCAN unless certain conditions are detected on the CAN bus.
Page 577 FlexCAN or EXTAL sys 3 ⁄ ---------------------------------------- - Eqn. 30-4 PRESDIV + 1 A bit time is subdivided into three segments (see Figure 30-15 Table 30-14): • SYNC_SEG: Has a fixed length of one time quantum. Signal edges are expected to happen within this section.
Page 578: Flexcan Initialization Sequence
FlexCAN NOTE It is the user’s responsibility to ensure the bit time settings are in compliance with the CAN standard. For bit time calculations, use an IPT (Information Processing Time) of 2, which is the value implemented in the FlexCAN module Table 30-15.
Page 579 FlexCAN For any configuration change/initialization, the FlexCAN must be in freeze mode (see Section 30.1.3.2, “Freeze Mode”). The following is a generic initialization sequence applicable to the FlexCAN module: 1. Initialize all operation modes in the CANCTRL register. a) Initialize the bit timing parameters PROPSEG, PSEGS1, PSEG2, and RJW. b) Select the S-clock rate by programming the PRESDIV field.
Page 580 FlexCAN MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 0 30-30 Preliminary Freescale Semiconductor...
Page 581: Debug Module
Chapter 31 Debug Module 31.1 Introduction This chapter describes the Revision B+ enhanced hardware debug module. 31.1.1 Overview The debug module is shown in Figure 31-1. High-speed ColdFire CPU Core core bus Debug Module Trace Port Control Communication Port PST[3:0], DDATA[3:0] DSCLK, DSI, DSO BKPT PSTCLK...
Page 582: External Signal Description
Debug Module of key registers and variables and return the system to normal operation. See Section 31.6, “Real-Time Debug Support. 31.1.1.1 The New Debug Module Hardware (Rev. B+) The revision B+ debug module features a small enhancement over revision B: the addition of three PC breakpoint registers (PCBR1–3).
Page 583: Real-Time Trace Support
Debug Module Table 31-1. Debug Module Signals Signal Description Development Serial Internally synchronized input. (The logic level on DSCLK is validated if it has the same value on Clock (DSCLK) two consecutive rising PSTCLK edges.) Clocks the serial communication port to the debug module during packet transfers.
Page 584 Debug Module address calculation is based on the contents of a program-visible register (variant addressing). DDATA outputs can be configured to display the target address of such instructions in sequential nibble increments across multiple processor clock cycles, as described in Section 31.3.1, “Begin Execution of Taken Branch (PST = 0x5).”...
Page 585 Debug Module Table 31-2. Processor Status Encoding (continued) PST[3:0] Definition Binary 1101 Entry into emulator mode. Displayed during emulation mode (debug interrupt or optionally trace). Because this encoding defines a multiple-cycle mode, PST outputs are driven with 0xD until exception processing completes.
Page 586: Memory Map/Register Definition
Debug Module PSTCLK default default default default DDATA A[3:0] A[7:4] A[11:8] A[15:12] Figure 31-3. Example JMP Instruction Output on PST/DDATA PST 0x5 indicates a taken branch and the marker value 0x9 indicates a 2-byte address. Thus, the subsequent 4 nibbles of DDATA display the lower 2 bytes of address register A0 in least-to-most-significant nibble order.
Page 587 Debug Module Table 31-3. Debug Module Memory Map (continued) Width DRc[4–0] Register Access Reset Value Section/Page (bits) 0x0C Address High Breakpoint Register (ABHR) See Note Undefined 31.4.7/31-15 0x0D Address Low Breakpoint Register (ABLR) See Note Undefined 31.4.7/31-15 0x0E Data Breakpoint Register (DBR) See Note Undefined 31.4.8/31-16...
Page 588 Debug Module DRc[4:0]: 0x00 (CSR) Access: Supervisor write-only BDM read/write BSTAT TRG HALT BKPT Reset Reset Figure 31-4. Configuration/Status Register (CSR) Table 31-5. CSR Field Descriptions Field Description 31–28 Breakpoint status. Provides read-only status (from the BDM port only) information concerning hardware breakpoints. BSTAT BSTAT is cleared by a TDR write or by a CSR read when either a level-2 breakpoint is triggered or a level-1 breakpoint is triggered and the level-2 breakpoint is disabled.
Page 589 Debug Module Table 31-5. CSR Field Descriptions (continued) Field Description Force emulation mode on trace exception. If TRC = 1, the processor enters emulator mode when a trace exception occurs. If TRC=0, the processor enters supervisor mode. Force emulation mode. If EMU = 1, the processor begins executing in emulator mode. See Section 31.6.1.1, “Emulator Mode.”...
Page 590 Debug Module loaded any time the AATR is written. The BAAR is initialized to a value of 0x05, setting supervisor data as the default address space. DRc[4:0]: 0x05 (BAAR) Access: Supervisor write-only BDM write-only Reset: Figure 31-5. BDM Address Attribute Register (BAAR) Table 31-6.
Page 591 Debug Module Table 31-7. AATR Field Descriptions Field Description Read/write mask. Setting RM masks R in address comparisons. 14–13 Size mask. Setting an SZM bit masks the corresponding SZ bit in address comparisons. 12–11 Transfer type mask. Setting a TTM bit masks the corresponding TT bit in address comparisons. 10–8 Transfer modifier mask.
Page 592 Debug Module 31.4.5 Trigger Definition Register (TDR) The TDR configures the operation of the hardware breakpoint logic that corresponds with the ABHR/ABLR/AATR, PBR/PBMR, and DBR/DBMR registers within the debug module. The TDR controls the actions taken under the defined conditions. Breakpoint logic may be configured as a one- or two-level trigger.
Page 593 Debug Module Table 31-8. TDR Field Descriptions (continued) Field Description 28–22 Enable level 2 data breakpoint. Setting an L2ED bit enables the corresponding data breakpoint condition based on L2ED the size and placement on the processor’s local data bus. Clearing all ED bits disables data breakpoints. TDR Bit Description Data longword.
Page 594 Debug Module Table 31-8. TDR Field Descriptions (continued) Field Description Level 1 trigger. Determines the logic operation for the trigger between the PC_condition and the (Address_range & Data_condition) where the inclusion of a Data_condition is optional. The ColdFire debug architecture supports the creation of single or double-level triggers.
Page 595 Debug Module 31.4.6 Program Counter Breakpoint/Mask Registers (PBR, PBMR) The PBR register defines an instruction address for use as part of the trigger. This register’s contents are compared with the processor’s program counter register when TDR is configured appropriately. PBR bits are masked by setting corresponding PBMR bits.
Page 596 Debug Module the processor’s high-speed local bus. The trigger definition register (TDR) identifies the trigger as one of three cases: 1. Identical to the value in ABLR 2. Inside the range bound by ABLR and ABHR inclusive 3. Outside that same range ABHR is accessible in supervisor mode as debug control register 0x0C using the WDEBUG instruction and via the BDM port using the commands.
Page 597: Background Debug Mode (Bdm)
Debug Module Table 31-13. DBR Field Descriptions Field Description 31–0 Data breakpoint value. Contains the value to be compared with the data value from the processor’s local bus as a Data breakpoint trigger. Table 31-14. DBMR Field Descriptions Field Description 31–0 Data breakpoint mask.
Page 598 Debug Module 2. A hardware breakpoint can be configured to generate a pending halt condition similar to the assertion of BKPT. This type of halt is always first made pending in the processor. Next, the processor samples for pending halt and interrupt conditions once per instruction. When a pending condition is asserted, the processor halts execution at the next sample point.
Page 599 Debug Module transmission consists of 17-bit packets composed of a status/control bit and a 16-bit data word. As shown Figure 31-12, all state transitions are enabled on a rising edge of PSTCLK when DSCLK is high; that is, DSI is sampled and DSO is driven. PSTCLK DSCLK Current...
Page 600 Debug Module Table 31-16. Receive BDM Packet Field Description Field Description Status. Indicates the status of CPU-generated messages listed below. The not-ready response can be ignored unless a memory-referencing cycle is in progress. Otherwise, the debug module can accept a new serial transfer after 32 processor clock periods.
Page 601 Debug Module Table 31-18. BDM Command Summary (continued) Section/ Command Command Mnemonic Description State Page (Hex) Read memory Read the data at the memory location specified Steal 31.5.3.3.3/ 0x1900 byte READ location by the longword address. 31-25 0x1940 word 0x1980 longword Write memory Write the operand data to the memory location Steal...
Page 602 Debug Module Operation Op Size Register Extension Word(s) Figure 31-15. BDM Command Format Table 31-19. BDM Field Descriptions Field Description 15–10 Specifies the command. These values are listed in Table 31-18. Operation Reserved, should be cleared. Direction of operand transfer. 0 Data is written to the CPU or to memory from the development system.
Page 603 Debug Module sends to the debug module; the bottom half indicates the debug module’s response to the previous development system commands. Command and result transactions overlap to minimize latency. Commands transmitted to the debug module Command code transmitted during this cycle High-order 16 bits of memory address Low-order 16 bits of memory address Non-serial-related...
Page 604 Debug Module sent to the debug module during the final transfer. If a memory or register access is terminated with a bus error, the error status (S = 1, DATA = 0x0001) is returned instead of result data. 31.5.3.3 Command Set Descriptions The following sections describe the commands summarized in Table 31-18.
Page 605 Debug Module Register D[31:16] D[15:0] Figure 31-19. Command Format WAREG WDREG Command Sequence: WAREG/WDREG MS DATA LS DATA NEXT CMD ’NOT READY’ ’NOT READY’ ’CMD COMPLETE’ NEXT CMD BERR ’NOT READY’ Figure 31-20. Command Sequence WAREG WDREG Operand Data: Longword data is written into the specified address or data register. The data is supplied most-significant word first.
Page 606 Debug Module Command Sequence: READ READ (B/W) MS ADDR LS ADDR MEMORY ’NOT READY’ ’NOT READY’ ’NOT READY’ LOCATION NEXT CMD RESULT NEXT CMD BERR ’NOT READY’ READ READ (LONG) MS ADDR LS ADDR MEMORY ’NOT READY’ ’NOT READY’ ’NOT READY’ LOCATION NEXT CMD MS RESULT...
Page 607 Debug Module Byte A[31:16] A[15:0] D[7:0] Word A[31:16] A[15:0] D[15:0] Longword A[31:16] A[15:0] D[31:16] D[15:0] Figure 31-23. Command Format WRITE MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 31-27 Preliminary...
Page 608 Debug Module Command Sequence: WRITE DATA WRITE (B/W) MS ADDR LS ADDR MEMORY ’NOT READY’ ’NOT READY’ ’NOT READY’ ’NOT READY’ LOCATION NEXT CMD ’CMD COMPLETE’ BERR NEXT CMD ’NOT READY’ WRITE (LONG) MS ADDR LS ADDR MS DATA ’NOT READY’ ’NOT READY’...
Page 609 Debug Module NOTE does not check for a valid address; it is a valid command only when DUMP preceded by , or another command. Otherwise, an illegal READ DUMP command response is returned. can be used for intercommand padding without corrupting the address pointer. The size field is examined each time a command is processed, allowing the operand size to be DUMP...
Page 610 Debug Module Result Data: Requested data is returned as either a word or longword. Byte data is returned in the least-significant byte of a word result. Word results return 16 bits of significant data; longword results return 32 bits. A value of 0x0001 (with S set) is returned if a bus error occurs.
Page 611 Debug Module Command Sequence: WRITE FILL (LONG) MS DATA LS DATA MEMORY ’NOT READY’ ’NOT READY’ ’NOT READY’ LOCATION NEXT CMD NEXT CMD ’CMD COMPLETE’ ’ILLEGAL’ ’NOT READY’ NEXT CMD BERR ’NOT READY’ WRITE FILL (B/W) DATA MEMORY ’NOT READY’ ’NOT READY’...
Page 612 Debug Module Operand Data: None Result Data: The command-complete response (0xFFFF) is returned during the next shift operation. 31.5.3.3.8 No Operation ( performs no operation and may be used as a null command where required. Command Formats: Figure 31-31. Command Format Command Sequence: NEXT CMD ’CMD COMPLETE’...
Page 613 Debug Module Command Sequence: SYNC_PC NEXT CMD “CMD COMPLETE” Operand Data: None Result Data: The command complete response, $FFFF (with the status bit cleared), is returned during the next shift operation. 31.5.3.3.10 Read Control Register ( RCREG Reads the selected control register and returns the 32-bit result. Accesses to the processor/memory control registers are always 32 bits wide, regardless of register width.
Page 614 Debug Module READ RCREG MS ADDR MS ADDR CONTROL ’NOT READY’ ’NOT READY’ ’NOT READY’ REGISTER NEXT CMD NEXT CMD MS RESULT LS RESULT NEXT CMD BERR ’NOT READY’ Figure 31-34. Command Sequence RCREG Operand Data: The only operand is the 32-bit Rc control register select field. Result Data: Control register contents are returned as a longword, most-significant word first.
Page 615 Debug Module Command Result D[31:16] D[15:0] Figure 31-35. Command/Result Formats WCREG Command Sequence: WCREG MS ADDR MS ADDR MS DATA ’NOT READY’ ’NOT READY’ ’NOT READY’ WRITE LS DATA CONTROL ’NOT READY’ ’NOT READY’ REGISTER NEXT CMD ’CMD COMPLETE’ BERR NEXT CMD ’NOT READY’...
Page 616 Debug Module Command Result D[31:16] D[15:0] Figure 31-37. Command/Result Formats RDMREG Table 31-21 shows the definition of DRc encoding. Table 31-21. Definition of DRc Encoding—Read DRc[4:0] Debug Register Definition Mnemonic Initial State Page 0x00 Configuration/Status p. 31-7 0x01–0x1F Reserved — —...
Page 617: Real-Time Debug Support
Debug Module WDMREG MS DATA LS DATA NEXT CMD ’NOT READY’ ’NOT READY’ ’CMD COMPLETE’ NEXT CMD ’ILLEGAL’ ’NOT READY’ Figure 31-40. Command Sequence WDMREG Operand Data: Longword data is written into the specified debug register. The data is supplied most-significant word first.
Page 618 Debug Module The breakpoint status is also posted in the CSR. Note that CSR[BSTAT] is cleared by a CSR read when either a level-2 breakpoint is triggered, or a level-1 breakpoint is triggered and a level-2 breakpoint is not enabled. Status is also cleared by writing to TDR. BDM instructions use the appropriate registers to load and configure breakpoints.
Page 619 Debug Module 31.6.1.1 Emulator Mode Emulator mode is used to facilitate non-intrusive emulator functionality. This mode can be entered in three different ways: • Setting CSR[EMU] forces the processor into emulator mode. EMU is examined only if RSTI is negated and the processor begins reset exception processing. It can be set while the processor is halted before reset exception processing begins.
Page 620: Processor Status, Ddata Definition
Debug Module 31.7 Processor Status, DDATA Definition This section specifies the ColdFire processor and debug module’s generation of the processor status (PST) and debug data (DDATA) output on an instruction basis. In general, the PST/DDATA output for an instruction is defined as follows: PST = 0x1, {PST = [0x89B], DDATA= operand} where the {...} definition is optional operand information defined by the setting of the CSR.
Page 621 Debug Module Table 31-23. PST/DDATA Specification for User-Mode Instructions (continued) Instruction Operand Syntax PST/DDATA bra.{b,w} PST = 0x5 bset #imm,<ea>x PST = 0x1, {PST = 0x8, DD = source}, {PST = 0x8, DD = destination} bset Dy,<ea>x PST = 0x1, {PST = 0x8, DD = source}, {PST = 0x8, DD = destination} bsr.{b,w} PST = 0x5, {PST = 0xB, DD = destination operand} btst...
Page 622 Debug Module Table 31-23. PST/DDATA Specification for User-Mode Instructions (continued) Instruction Operand Syntax PST/DDATA movem.l #list,<ea>x PST = 0x1, {PST = 0xB, DD = destination},... movem.l <ea>y,#list PST = 0x1, {PST = 0xB, DD = source},... moveq #imm,Dx PST = 0x1 muls.l <ea>y,Dx PST = 0x1, {PST = 0xB, DD = source operand}...
Page 623 Debug Module Table 31-23. PST/DDATA Specification for User-Mode Instructions (continued) Instruction Operand Syntax PST/DDATA wddata.b <ea>y PST = 0x4, {PST = 0x8, DD = source operand wddata.l <ea>y PST = 0x4, {PST = 0xB, DD = source operand wddata.w <ea>y PST = 0x4, {PST = 0x9, DD = source operand For JMP and JSR instructions, the optional target instruction address is displayed only for those effective address fields defining variant addressing modes.
Page 624: Freescale-Recommended Bdm Pinout
Debug Module Table 31-24. PST/DDATA Specification for MAC Instructions (continued) Instruction Operand Syntax PST/DDATA move.l Accy,Rx PST = 0x1 move.l MACSR,CCR PST = 0x1 move.l MACSR,Rx PST = 0x1 move.l MASK,Rx PST = 0x1 move.l Accext01,Rx PST = 0x1 move.l Accext23,Rx PST = 0x1 msac.l...
Page 625 Debug Module Developer reserved BKPT DSCLK Developer reserved RSTI Pad-Voltage PST3 PST1 PST2 DDATA3 PST0 DDATA1 DDATA2 DDATA0 Freescale reserved Freescale reserved PSTCLK Core-Voltage Pins reserved for BDM developer use. Supplied by target Figure 31-41. Recommended BDM Connector MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 31-45 Preliminary...
Page 626 Debug Module MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 0 31-46 Freescale Semiconductor Preliminary...
Page 627: Ieee 1149.1 Test Access Port (Jtag)
Chapter 32 IEEE 1149.1 Test Access Port (JTAG) 32.1 Introduction The joint test action group (JTAG) is a dedicated user-accessible test logic that complies with the IEEE 1149.1 standard for boundary-scan testability, which helps with system diagnostic and manufacturing testing. This architecture provides access to all data and chip control pins from the board-edge connector through the standard four-pin test access port (TAP) and the JTAG reset pin, TRST.
Page 628: External Signal Description
IEEE 1149.1 Test Access Port (JTAG) 32.1.2 Features The basic tasks of the JTAG module include the following: • Performs boundary-scan operations to test circuit board electrical continuity • Bypasses instruction to reduce the shift register path to a single cell •...
Page 629 IEEE 1149.1 Test Access Port (JTAG) Table 32-2. Pin Function Selected JTAG_EN = 0 JTAG_EN = 1 Pin Name Module selected JTAG — Pin Function — TCLK TCLK BKPT BKPT DSCLK TRST DSCLK When one module is selected, the inputs into the other module are disabled or forced to a known logic level, as shown in Table 32-3, in order to disable the corresponding module.
Page 630: Memory Map/Register Definition
IEEE 1149.1 Test Access Port (JTAG) 32.2.5 Test Reset/Development Serial Clock (TRST/DSCLK) The TRST pin is an active low asynchronous reset input with an internal pull-up resistor that forces the TAP controller to the test-logic-reset state. The DSCLK pin clocks the serial communication port to the debug module. Maximum frequency is 1/5 the processor clock speed.
Page 631 IEEE 1149.1 Test Access Port (JTAG) Table 32-4. IDCODE Field Descriptions Field Description 31–28 Part revision number. Indicate the revision number of the device. 27–22 Freescale Design Center number. 21–12 Part identification number. Indicate the device number. 11–1 Joint Electron Device Engineering Council ID bits. Indicate the reduced JEDEC ID for Freescale (0x0E). JEDEC IDCODE register ID.
Page 632: Functional Description
IEEE 1149.1 Test Access Port (JTAG) 32.4 Functional Description 32.4.1 JTAG Module The JTAG module consists of a TAP controller state machine, which is responsible for generating all control signals that execute the JTAG instructions and read/write data registers. 32.4.2 TAP Controller The TAP controller is a state machine that changes state based on the sequence of logical values on the TMS pin.
Page 633 IEEE 1149.1 Test Access Port (JTAG) TEST-LOGIC-RESET RUN-TEST/IDLE SELECT DR-SCAN SELECT IR-SCAN CAPTURE-DR CAPTURE-IR SHIFT-DR SHIFT-IR EXIT1-DR EXIT1-IR PAUSE-DR PAUSE-IR EXIT2-DR EXIT2-IR UPDATE-DR UPDATE-IR Figure 32-5. TAP Controller State Machine Flow 32.4.3 JTAG Instructions Table 32-5 describes public and private instructions. Table 32-5.
Page 634 IEEE 1149.1 Test Access Port (JTAG) Table 32-5. JTAG Instructions (continued) Instruction IR[4:0] Instruction Summary EXTEST 00100 Selects boundary scan register while applying preloaded values to output pins and asserting functional reset ENABLE_TEST_CTRL 00110 Selects TEST_CTRL register HIGHZ 01001 Selects bypass register while tri-stating all output pins and asserting functional reset CLAMP 01100...
Page 635 IEEE 1149.1 Test Access Port (JTAG) NOTE External synchronization is required to achieve meaningful results because there is no internal synchronization between TCLK and the system clock. 32.4.3.4 EXTEST Instruction The external test (EXTEST) instruction selects the boundary scan register. It forces all output pins and bidirectional pins configured as outputs to the values preloaded with the SAMPLE/PRELOAD instruction and held in the boundary scan update registers.
Page 636: Initialization/Application Information
IEEE 1149.1 Test Access Port (JTAG) 32.5 Initialization/Application Information 32.5.1 Restrictions The test logic is a static logic design, and TCLK can be stopped in either a high or low state without loss of data. However, the system clock is not synchronized to TCLK internally. Any mixed operation using both the test logic and the system functional logic requires external synchronization.
Page 637: Appendix A Register Memory Map Quick Reference
Appendix A Register Memory Map Quick Reference Table A-1 summarizes the address, name, and byte assignment for registers within the MCF52235 CPU space. Table A-2 lists an overview of the memory map for the on-chip modules, and Table A-3 is a detailed memory map including all of the registers for on-chip modules.
Page 638 Register Memory Map Quick Reference Table A-2. Module Memory Map Overview Address Module Size 0x0000_0000 On-chip Flash/RAM Array IPSBAR + 0x00_0000 System Control Module 64 bytes IPSBAR + 0x00_0040 Reserved 64 bytes IPSBAR + 0x00_0080 Reserved 128 bytes IPSBAR + 0x00_0100 DMA (Channel 0) 16 bytes IPSBAR + 0x00_0110...
Page 639 Register Memory Map Quick Reference Table A-2. Module Memory Map Overview (continued) Address Module Size IPSBAR + 0x16_0000 Programmable Interval Timer 1 IPSBAR + 0x17_0000 Reserved IPSBAR + 0x18_0000 Reserved IPSBAR + 0x19_0000 IPSBAR + 0x1A_0000 General Purpose Timer A IPSBAR + 0x1B_0000 IPSBAR + 0x1C_0000 FlexCAN...
Page 640 Register Memory Map Quick Reference Table A-3. Register Memory Map (continued) Address Name Mnemonic Size IPSBAR + 0x02A Peripheral Access Control Register 5 PACR5 IPSBAR + 0x02B Peripheral Access Control Register 6 PACR6 IPSBAR + 0x02C Peripheral Access Control Register 7 PACR7 IPSBAR + 0x02E Peripheral Access Control Register 8...
Page 641 Register Memory Map Quick Reference Table A-3. Register Memory Map (continued) Address Name Mnemonic Size IPSBAR + 0x210 (Read) UART Input Port Change Register 0 UIPCR0 (Write) UART Auxiliary Control Register 0 UACR0 IPSBAR + 0x214 (Read) UART Interrupt Status Register 0 UISR0 (Write) UART Interrupt Mask Register 0 UIMR0...
Page 642 Register Memory Map Quick Reference Table A-3. Register Memory Map (continued) Address Name Mnemonic Size IPSBAR + 0x278 (Read) Reserved (Write) UART Output Port Bit Set Command Register 1 UOP11 IPSBAR + 0x27C (Read) Reserved (Write) UART Output Port Bit Reset Command Register 1 UIP01 IPSBAR + 0x280 UART Mode Register 2...
Page 643 Register Memory Map Quick Reference Table A-3. Register Memory Map (continued) Address Name Mnemonic Size IPSBAR + 0x340 QSPI Mode Register IPSBAR + 0x344 QSPI Delay Register QDLYR IPSBAR + 0x348 QSPI Wrap Register IPSBAR + 0x34C QSPI Interrupt Register IPSBAR + 0x350 QSPI Address Register IPSBAR + 0x354...
Page 644 Register Memory Map Quick Reference Table A-3. Register Memory Map (continued) Address Name Mnemonic Size IPSBAR + 0x483 DMA Timer Event Register 2 DTER2 IPSBAR + 0x484 DMA Timer Reference Register 2 DTRR2 IPSBAR + 0x488 DMA Timer Capture Register 2 DTCR2 IPSBAR + 0x48C DMA Timer Counter Register 2...
Page 645 Register Memory Map Quick Reference Table A-3. Register Memory Map (continued) Address Name Mnemonic Size IPSBAR + 0xC4E Interrupt Control Register 0-14 ICR014 IPSBAR + 0xC4F Interrupt Control Register 0-15 ICR015 IPSBAR + 0xC51 Interrupt Control Register 0-17 ICR017 IPSBAR + 0xC52 Interrupt Control Register 0-18 ICR018 IPSBAR +0xC53...
Page 646 Register Memory Map Quick Reference Table A-3. Register Memory Map (continued) Address Name Mnemonic Size IPSBAR + 0xC70 Interrupt Control Register 0-48 ICR048 IPSBAR + 0xC71 Interrupt Control Register 0-49 ICR049 IPSBAR + 0xC72 Interrupt Control Register 0-50 ICR050 IPSBAR + 0xC73 Interrupt Control Register 0-51 ICR051 IPSBAR + 0xC74...
Page 647 Register Memory Map Quick Reference Table A-3. Register Memory Map (continued) Address Name Mnemonic Size IPSBAR + 0xD41 Interrupt Control Register 1-01 ICR101 IPSBAR + 0xD42 Interrupt Control Register 1-02 ICR102 IPSBAR + 0xD43 Interrupt Control Register 1-03 ICR103 IPSBAR + 0xD44 Interrupt Control Register 1-04 ICR104 IPSBAR + 0xD45...
Page 648 Register Memory Map Quick Reference Table A-3. Register Memory Map (continued) Address Name Mnemonic Size IPSBAR + 0xD63 Interrupt Control Register 1-35 ICR135 IPSBAR + 0xD64 Interrupt Control Register 1-36 ICR136 IPSBAR + 0xD65 Interrupt Control Register 1-37 ICR137 IPSBAR + 0xD66 Interrupt Control Register 1-38 ICR138 IPSBAR + 0xD67...
Page 649 Register Memory Map Quick Reference Table A-3. Register Memory Map (continued) Address Name Mnemonic Size IPSBAR + 0xDF4 Level 5 Interrupt Acknowledge Register 1 L5IACKR1 IPSBAR + 0xDF8 Level 6 Interrupt Acknowledge Register 1 L6IACKR1 IPSBAR + 0xDFC Level 7 Interrupt Acknowledge Register 1 L7IACKR1 Global Interrupt Acknowledge Cycle Registers IPSBAR + 0xFE4...
Page 650 Register Memory Map Quick Reference Table A-3. Register Memory Map (continued) Address Name Mnemonic Size IPSBAR + 0x10_0014 Port DD Output Data Register PORTDD IPSBAR + 0x10_0015 Port LD Output Data Register PORTLD IPSBAR + 0x10_0016 Port GP Output Data Register PORTGP IPSBAR + 0x10_0017 Reserved...
Page 651 Register Memory Map Quick Reference Table A-3. Register Memory Map (continued) Address Name Mnemonic Size IPSBAR + 0x10_0035 Reserved — IPSBAR + 0x10_0036 Reserved — IPSBAR + 0x10_0037 Reserved — IPSBAR + 0x10_0038 Port NQ Pin Data/Set Data Register PORTNQ/ SETNQ IPSBAR + 0x10_0039 Reserved...
Page 652 Register Memory Map Quick Reference Table A-3. Register Memory Map (continued) Address Name Mnemonic Size IPSBAR + 0x10_004E Reserved — IPSBAR + 0x10_004F Reserved — IPSBAR + 0x10_0050 Port NQ Clear Output Data Register CLRNQ IPSBAR + 0x10_0051 Reserved — IPSBAR + 0x10_0052 Port AN Clear Output Data Register CLRAN...
Page 653 Register Memory Map Quick Reference Table A-3. Register Memory Map (continued) Address Name Mnemonic Size IPSBAR + 0x10_0071 Port UA Pin Assignment Register PUAPAR IPSBAR + 0x10_0072 Port UB Pin Assignment Register PUBPAR IPSBAR + 0x10_0073 Port UC Pin Assignment Register PUCPAR IPSBAR + 0x10_0074 Port DD Pin Assignment Register...
Page 654 Register Memory Map Quick Reference Table A-3. Register Memory Map (continued) Address Name Mnemonic Size IPSBAR + 0x14_0002 EPORT1 Data Direction Register EPDDR1 IPSBAR + 0x14_0003 EPORT1 Interrupt Enable Register EPIER1 IPSBAR + 0x14_0004 EPORT1 Data Register EPDR1 IPSBAR + 0x14_0005 EPORT1 Pin Data Register EPPDR1 IPSBAR + 0x14_0006...
Page 655 Register Memory Map Quick Reference Table A-3. Register Memory Map (continued) Address Name Mnemonic Size IPSBAR + 0x1A_0000 GPTA IC/OC Select Register GPTAIOS IPSABAR + 0x1A_0001 GPTA Compare Force Register GPTACFORC IPSBAR + 0x1A_0002 GPTA Output Compare 3 Mask Register GPTAOC3M IPSBAR + 0x1A_0003 GPTA Output Compare 3 Data Register...
Page 656 Register Memory Map Quick Reference Table A-3. Register Memory Map (continued) Address Name Mnemonic Size IPSBAR + 0x1B_000D PWM channel Counter Register 1 PWMCNT1 IPSBAR + 0x1B_000E PWM channel Counter Register 2 PWMCNT2 IPSBAR + 0x1B_000F PWM channel Counter Register 3 PWMCNT3 IPSBAR + 0x1B_0010 PWM channel Counter Register 4...
Page 657 Register Memory Map Quick Reference Table A-3. Register Memory Map (continued) Address Name Mnemonic Size IPSBAR + 0x1D_0002 CFM Clock Divider Register CFMCLKD CFMSEC IPSBAR + 0x1D_0008 CFM Security Register IPSBAR + 0x1D_0010 CFM Protection Register CFMPROT IPSBAR + 0x1D_0014 CFM Supervisor Access Register CFMSACC IPSBAR + 0x1D_0018...
Page 658 Register Memory Map Quick Reference MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 0 A-22 Freescale Semiconductor Preliminary...

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