NXP Semiconductors MC9S08SU16 Reference Manual page 309

WI NDOW
Plus input
Minus input
CMPO
COUTA
EN, PMODE,HYSCTR
INP
INM
bus clock
FILT_PER
For control configurations which result in disabling the Filter Block, refer to
Bypass Logic diagram.
NXP Semiconductors
Figure 18-8. Windowed Mode Operation
INTERNAL BUS
FILT_PER
COS INV
+
+
Polarity
Select
-
-
CMPO
WINDOW/SAMPLE
Clock
divided
Prescaler
bus
clock
Figure 18-9. Windowed Mode
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 18 Chip-specific ACMP information
OPE
FILTER_CNT SE COUT
WE
0x01 0
Window
Filter
Control
Block
1
0
COUTA
CGMUX
SE=0
IER/F CFR/F
Interrupt
Control
IRQ
COUT
(TO OTHER SOC FUNCTIONS))
0
CMPO to
1
PAD
COS
Filter Block
309