Sci Control Register 3 (Scix_C3) - NXP Semiconductors MC9S08SU16 Reference Manual

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Field
4
Receive Data Inversion
RXINV
Setting this bit reverses the polarity of the received data input.
NOTE: Setting RXINV inverts the RxD input for all cases: data bits, start and stop bits, break, and idle.
0
Receive data not inverted.
1
Receive data inverted.
3
Receive Wake Up Idle Detect
RWUID
RWUID controls whether the idle character that wakes up the receiver sets the IDLE bit.
0
During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle
character.
1
During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character.
2
Break Character Generation Length
BRK13
BRK13 selects a longer transmitted break character length. Detection of a framing error is not affected by
the state of this bit.
0
Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS =
0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1).
1
Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS =
0 or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1).
1
LIN Break Detection Enable
LBKDE
LBKDE selects a longer break character detection length. While LBKDE is set, framing error (FE) and
receive data register full (RDRF) flags are prevented from setting.
0
Break character is detected at length 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M
= 0, SBNS = 1) or 12 (if M = 1, SBNS = 1).
1
Break character is detected at length of 11 bit times (if M = 0, SBNS = 0) or 12 (if M = 1, SBNS = 0 or
M = 0, SBNS = 1) or 13 (if M = 1, SBNS = 1).
0
Receiver Active Flag
RAF
RAF is set when the SCI receiver detects the beginning of a valid start bit, and RAF is cleared
automatically when the receiver detects an idle line. This status flag can be used to check whether an SCI
character is being received before instructing the MCU to go to stop mode.
0
SCI receiver idle waiting for a start bit.
1
SCI receiver active (RxD input not idle).

22.4.7 SCI Control Register 3 (SCIx_C3)

Address: 1868h base + 6h offset = 186Eh
Bit
7
Read
R8
Write
Reset
0
NXP Semiconductors
SCIx_S2 field descriptions (continued)
6
5
T8
TXDIR
TXINV
0
0
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 22 Serial Communications Interface (SCI)
Description
4
3
ORIE
NEIE
0
0
2
1
FEIE
PEIE
0
0
0
0
407

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