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Chapter 22 Serial Communications Interface (SCI)
After receiving the stop bit into the receive shifter, and provided the receive data register
is not already full, the data character is transferred to the receive data register and the
receive data register full (SCI_S1[RDRF]) status flag is set. If SCI_S1[RDRF] was
already set indicating the receive data register (buffer) was already full, the overrun (OR)
status flag is set and the new data is lost. Because the SCI receiver is double-buffered, the
program has one full character time after SCI_S1[RDRF] is set before the data in the
receive data buffer must be read to avoid a receiver overrun.
When a program detects that the receive data register is full (SCI_S1[RDRF] = 1), it gets
the data from the receive data register by reading SCI_D. The SCI_S1[RDRF] flag is
cleared automatically by a two-step sequence normally satisfied in the course of the user's
program that manages receive data. Refer to
Interrupts and status flags
for more details
about flag clearing.
22.5.3.1 Data sampling technique
The SCI receiver uses a 16× baud rate clock for sampling. The oversampling ratio is
fixed at 16. The receiver starts by taking logic level samples at 16 times the baud rate to
search for a falling edge on the RxD serial data input pin. A falling edge is defined as a
logic 0 sample after three consecutive logic 1 samples. The 16× baud rate clock divides
the bit time into 16 segments labeled SCI_D[RT1] through SCI_D[RT16]. When a falling
edge is located, three more samples are taken at SCI_D[RT3], SCI_D[RT5], and
SCI_D[RT7] to make sure this was a real start bit and not merely noise. If at least two of
these three samples are 0, the receiver assumes it is synchronized to a receive character.
The receiver then samples each bit time, including the start and stop bits, at SCI_D[RT8],
SCI_D[RT9], and SCI_D[RT10] to determine the logic level for that bit. The logic level
is interpreted to be that of the majority of the samples taken during the bit time. In the
case of the start bit, the bit is assumed to be 0 if at least two of the samples at
SCI_D[RT3], SCI_D[RT5], and SCI_D[RT7] are 0 even if one or all of the samples
taken at SCI_D[RT8], SCI_D[RT9], and SCI_D[RT10] are 1s. If any sample in any bit
time, including the start and stop bits, in a character frame fails to agree with the logic
level for that bit, the noise flag (SCI_S1[NF]) is set when the received character is
transferred to the receive data buffer.
The falling edge detection logic continuously looks for falling edges. If an edge is
detected, the sample clock is resynchronized to bit times. This improves the reliability of
the receiver in the presence of noise or mismatched baud rates. It does not improve worst
case analysis because some characters do not have any extra falling edges anywhere in
the character frame.
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
NXP Semiconductors
413
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