NXP Semiconductors MC9S08SU16 Reference Manual page 144

Instruction Set Summary
Source Form Operation
BCLR n,opr8a Clear Bit n in Memory
BCS rel Branch if Carry Bit Set
(same as BLO)
BEQ rel Branch if Equal
BGE rel Branch if Greater
Than or Equal To
(Signed Operands)
BGND Enter Active
Background if ENBDM
BGT rel Branch if Greater
Than (Signed
Operands)
BHCC rel Branch if Half Carry
Bit Clear
BHCS rel Branch if Half Carry
Bit Set
BHI rel Branch if Higher
BHS rel Branch if Higher or
Same (same as BCC)
BIH rel Branch if IRQ Pin High
BIL rel Branch if IRQ Pin Low
BIT #opr8i
BIT opr8a
BIT opr16a
Bit Test
BIT oprx16,X
BIT oprx8,X
BIT ,X
BIT oprx16,SP
BIT oprx8,SP
144
Table 10-3. Instruction Set Summary (continued)
Description
Mn ← 0
Branch if (C) = 1
Branch if (Z) = 1
Branch if (N ⊕ V) = 0
Waits For and
Processes BDM
= 1 Commands Until GO,
TRACE1, or TAGGO
Branch if (Z) | (N ⊕ V) =
0
Branch if (H) = 0
Branch if (H) = 1
Branch if (C) | (Z) = 0
Branch if (C) = 0
Branch if IRQ pin = 1
Branch if IRQ pin = 0
(A) & (M), (CCR
Updated but Operands
Not Changed)
Table continues on the next page...
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Effect on CCR
Address
V H I N Z C
Mode
– – – – – – DIR (b1)
– – – – – – DIR (b2)
– – – – – – DIR (b3)
– – – – – – DIR (b4)
– – – – – – DIR (b5)
– – – – – – DIR (b6)
– – – – – – DIR (b7)
– – – – – – REL
– – – – – – REL
– – – – – – REL
– – – – – – INH
− − − − − − REL
− − − − − − REL
− − − − − − REL
− − − − − − REL
− − − − − − REL
− − − − − − REL
− − − − − − REL
0 − − − IMM
↕ ↕
0 − − − DIR
↕ ↕
0 − − − EXT
↕ ↕
0 − − − IX2
↕ ↕
0 − − − IX1
↕ ↕
0 − − − IX
↕ ↕
0 − − − SP2
↕ ↕
0 − − − SP1
↕ ↕
13 dd 5
15 dd 5
17 dd 5
19 dd
1B dd 5
1D dd 5
1F dd 5
25 rr 3
27 rr 3
90 rr 3
82 5+
92 rr 3
28 rr 3
29 rr 3
22 rr 3
24 rr 3
2F rr 3
2E rr 3
A5 ii 2
B5 dd 3
C5 hh ll 4
D5 ee ff 4
E5 ff 3
F5 3
9ED5 ee ff 5
9EE5 ff 4
NXP Semiconductors