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NXP Semiconductors MC9S12XS256 Reference Manual

NXP Semiconductors MC9S12XS256 Reference Manual

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MC9S12XS256

Reference Manual

Covers MC9S12XS Family

MC9S12XS256

MC9S12XS128

MC9S12XS64

HCS12

Microcontrollers

MC9S12XS256RMV1

Rev. 1.13

08/2012

freescale.com

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Summary of Contents for NXP Semiconductors MC9S12XS256

Page 1 MC9S12XS256 Reference Manual Covers MC9S12XS Family MC9S12XS256 MC9S12XS128 MC9S12XS64 HCS12 Microcontrollers MC9S12XS256RMV1 Rev. 1.13 08/2012 freescale.com...
Page 2 To provide the most up-to-date information, the document revision on the World Wide Web is the most current. A printed copy may be an earlier revision. To verify you have the latest information available, refer to freescale.com. This document contains information for the complete S12XS Family and thus includes a set of separate flash (FTMR) module sections to cover the whole family.
Page 3: Table Of Contents
Chapter 1 Device Overview S12XS Family ....... . .19 Chapter 2 Port Integration Module (S12XSPIMV1) .
Page 4 S12XS Family Reference Manual, Rev. 1.13 Freescale Semiconductor...
Page 5 Chapter 1 Device Overview S12XS Family Introduction ..............19 1.1.1 Features .
Page 6 2.3.1 Memory Map ............65 2.3.2 Register Descriptions .
Page 7 2.3.46 Port P Pull Device Enable Register (PERP) ....... . . 106 2.3.47 Port P Polarity Select Register (PPSP) .
Page 8 External Signal Description ........... . . 130 Memory Map and Registers .
Page 9 5.3.3 Family ID Assignment ..........177 Functional Description .
Page 10 7.1.7 Complete Memory Erase (Special Modes) ........236 Chapter 8 S12XE Clocks and Reset Generator (S12XECRGV1) Introduction .
Page 11 10.1.3 Block Diagram ............273 10.1.4 Block Diagram of Input structure .
Page 12 12.1.2 Features ............. 349 12.1.3 Modes of Operation .
Page 13 14.1.3 Modes of Operation ........... . 398 14.1.4 Block Diagram .
Page 14 15.4.6 Error Conditions ............457 15.4.7 Low Power Mode Options .
Page 15 17.2.3 VDD, VSS — Regulator Output1 (Core Logic) Pins ......492 17.2.4 VDDF — Regulator Output2 (NVM Logic) Pins ......493 17.2.5 VDDPLL, VSSPLL —...
Page 16 Chapter 19 128 KByte Flash Module (S12XFTMR128K1V1) 19.1 Introduction ..............557 19.1.1 Glossary .
Page 17 Appendix A Electrical Characteristics A.1 General ..............657 A.1.1 Parameter Classification .
Page 18 C.1.2 80-Pin QFP Recommended PCB Layout ........710 C.1.3 64-Pin LQFP Recommended PCB Layout .
Page 19: Chapter 1 Device Overview S12Xs Family
Chapter 1 Device Overview S12XS Family Introduction The new S12XS family of 16-bit micro controllers is a compatible, reduced version of the S12XE family. These families provide an easy approach to develop common platforms from low-end to high-end applications, minimizing the redesign of software and hardware. Targeted at generic automotive applications and CAN nodes, some typical examples of these applications are: Body Controllers, Occupant Detection, Door Modules, RKE Receivers, Smart Actuators, Lighting Modules and Smart Junction Boxes amongst many others.
Page 20 Device Overview S12XS Family • INT (interrupt module) — Seven levels of nested interrupts — Flexible assignment of interrupt sources to each interrupt level. — External non-maskable high priority interrupt (XIRQ) — The following inputs can act as Wake-up Interrupts –...
Page 21 Device Overview S12XS Family – 16 data bits plus 6 syndrome ECC (Error Correction Code) bits allow single bit failure correction and double fault detection – Erase sector size 256 bytes – Automated program and erase algorithm — 4, 8 and 12 Kbyte RAM •...
Page 22 Device Overview S12XS Family — Time-out interrupt and peripheral triggers — Start of timers can be aligned • Up to 8 channel x 8-bit or 4 channel x 16-bit Pulse Width Modulator — Programmable period and duty cycle per channel —...
Page 23 Device Overview S12XS Family — 64-pin low-proﬁle quad ﬂat-pack (LQFP) • Operating Conditions — Wide single Supply Voltage range 3.135 V to 5.5 V at full performance – Separate supply for internal voltage regulator and I/O allow optimized EMC ﬁltering —...
Page 24 Device Overview S12XS Family 1.1.3 Block Diagram Figure 1-1 shows a block diagram of the S12XS Family devices VDDA 64, 128, 256 Kbytes Flash VSSA 8/10/12-bit 16-channel Analog-Digital Converter 4, 8, 12 Kbytes RAM 4, 8 Kbytes Data Flash AN[15:0] PAD[15:0] VDDR IOC0...
Page 25 Device Overview S12XS Family 1.1.4 Device Memory Map Table 1-1 shows the device register memory map. Table 1-1. Device Register Memory Map Size Address Module (Bytes) 0x0000–0x0009 PIM (port integration module 0x000A–0x000B MMC (memory map control) 0x000C–0x000D PIM (port integration module) 0x000E–0x000F Reserved 0x0010–0x0017...
Page 26 Device Overview S12XS Family Table 1-1. Device Register Memory Map (continued) Size Address Module (Bytes) 0x0368–0x07FF Reserved 1176 NOTE Reserved register space shown in Table 1-1 is not allocated to any module. This register space is reserved for future use. Writing to these locations has no effect.
Page 27 Device Overview S12XS Family CPU and BDM Global Memory Map Local Memory Map 0x00_0000 2K REGISTERS 0x00_07FF Unimplemented RAM_LOW 0x0000 2K REGISTERS 0x0800 1K DFLASH window 0x0F_FFFF EPAGE 0x0C00 Reserved DFLASH 0x1000 RPAGE 4K RAM window DF_HIGH 0x2000 DFLASH 8K RAM Resources 0x4000 0x13_FFFF...
Page 28 NVM variables used to patch NVM errata. The default is no patch (0xFFFF). Table 1-3. Assigned Part ID Numbers Device Mask Set Number Part ID Version ID MC9S12XS256 0M05M $C0C0 0xFFFF MC9S12XS128 0M04M $C1C0...
Page 29 Device Overview S12XS Family Signal Description This section describes signals that connect off-chip. It includes a pinout diagram, a table of signal properties, and detailed discussion of signals. It is built from the signal description sections of the individual IP blocks on the device. 1.2.1 Device Pinout The XS family of devices offers pin-compatible packaged devices to assist with system development and...
Page 30 Device Overview S12XS Family PWM3/KWP3/PP3 TXD1/IOC2/PWM2/KWP2/PP2 VDDA IOC1/PWM1/KWP1/PP1 PAD15/AN15 RXD1/IOC0/PWM0/KWP0/PP0 PAD07/AN07 PAD14/AN14 PAD06/AN06 PAD13/AN13 PAD05/AN05 S12XS Family IOC0/PT0 PAD12/AN12 IOC1/PT1 PAD04/AN04 112LQFP IOC2/PT2 PAD11/AN11 IOC3/PT3 PAD03/AN03 VDDF PAD10/AN10 VSS1 PAD02/AN02 PWM4/IOC4/PT4 PAD09/AN09 VREG_API/PWM5/IOC5/PT5 PAD01/AN01 PWM6/IOC6/PT6 PAD08/AN08 Pins shown in BOLD are not PWM7/IOC7/PT7 PAD00/AN00 available on the 80 QFP...
Page 31 Device Overview S12XS Family PWM3/KWP3/PP3 TXD1/IOC2/PWM2/KWP2/PP2 VDDA IOC1/PWM1/KWP1/PP1 PAD07/AN07 S12XS Family RXD1/IOC0/PWM0/KWP0/PP0 PAD06/AN06 IOC0/PT0 PAD05/AN05 80QFP IOC1/PT1 PAD04/AN04 IOC2/PT2 PAD03/AN03 IOC3/PT3 PAD02/AN02 VDDF PAD01/AN01 VSS1 PAD00/AN00 PWM4/IOC4/PT4 VSS2 VREG_API/PWM5/IOC5/PT5 PWM6/IOC6/PT6 Pins shown in BOLD are PWM7/IOC7/PT7 not available on the 64 MODC/BKGD QFP package Figure 1-4.
Page 32 Device Overview S12XS Family PWM3/KWP3/PP3 TXD1/IOC2/PWM2/KWP2/PP2 VDDA IOC1/PWM1/KWP1/PP1 PAD07/AN07 S12XS Family RXD1/IOC0/PWM0/KWP0/PP0 PAD06/AN06 64LQFP IOC0/PT0 PAD05/AN05 IOC1/PT1 PAD04/AN04 IOC2/PT2 PAD03/AN03 IOC3/PT3 PAD02/AN02 VDDF PAD01/AN01 VSS1 PAD00/AN00 PWM4/IOC4/PT4 VSS2 VREG_API/PWM5/IOC5/PT5 PWM6/IOC6/PT6 PWM7/IOC7/PT7 MODC/BKGD Figure 1-5. S12XS Family Pin Assignments 64-pin LQFP Package S12XS Family Reference Manual, Rev.
Page 33 Device Overview S12XS Family 1.2.2 Pin Assignment Overview Table 1-4 provides a summary of which ports are available for each package option. Routing of pin functions is summarized in Table 1-5. Table 1-4. Port Availability by Package Option Port 112 LQFP 80 QFP 64 LQFP Port AD/ADC Channels...
Page 34 Table 1-6 provides a pin out summary listing the availability and functionality of individual pins for each package option. Table 1-6. Pin-Out Summary Internal Pull Package Terminal Function Resistor Power Description Supply LQFP LQFP Reset CTRL Func. Func. Func. Func. State KWP3 PWM3...
Page 35 Table 1-6. Pin-Out Summary (continued) Internal Pull Package Terminal Function Resistor Power Description Supply LQFP LQFP Reset CTRL Func. Func. Func. Func. State IOC5 PWM5 VREG_ — PERT/PPST Disabled Port T I/O, PWM/TIM channel, API output IOC6 PWM6 — — PERT/PPST Disabled Port T I/O, channel of...
Page 36 Table 1-6. Pin-Out Summary (continued) Internal Pull Package Terminal Function Resistor Power Description Supply LQFP LQFP Reset CTRL Func. Func. Func. Func. State XCLKS ECLKX2 — — PUCR Port E I/O, system clock output, clock select input — — — —...
Page 37 Table 1-6. Pin-Out Summary (continued) Internal Pull Package Terminal Function Resistor Power Description Supply LQFP LQFP Reset CTRL Func. Func. Func. Func. State — — — PUCR Port E Input, maskable interrupt XIRQ — — — PUCR Port E Input, non- maskable interrupt —...
Page 38 Table 1-6. Pin-Out Summary (continued) Internal Pull Package Terminal Function Resistor Power Description Supply LQFP LQFP Reset CTRL Func. Func. Func. Func. State PAD10 AN10 — — — PER0AD Disabled Port AD I/O, analog input of ATD PAD03 AN03 — —...
Page 39 Table 1-6. Pin-Out Summary (continued) Internal Pull Package Terminal Function Resistor Power Description Supply LQFP LQFP Reset CTRL Func. Func. Func. Func. State — — — — PERM/PPSM Disabled Port M I/O — — — — PERM/PPSM Disabled Port M I/O RXD0 —...
Page 40 Table 1-6. Pin-Out Summary (continued) Internal Pull Package Terminal Function Resistor Power Description Supply LQFP LQFP Reset CTRL Func. Func. Func. Func. State VSSX1 — — — — — — — — VDDX1 — — — — — — — —...
Page 41 Device Overview S12XS Family 1.2.3 Detailed Signal Descriptions NOTE The pin list of the largest package version of each S12XS Family derivative gives the complete of interface signals that also exist on smaller package options, although some of them are not bonded out. For devices assembled in smaller packages all non-bonded out pins should be conﬁgured as outputs after reset in order to avoid current drawn from ﬂoating inputs.
Page 42 Device Overview S12XS Family 1.2.3.8 PE7 / ECLKX2 / XCLKS — Port E I/O Pin 7 PE7 is a general-purpose input or output pin. ECLKX2 is a clock output of twice the internal bus frequency. The XCLKS is an input signal which controls whether a crystal in combination with the internal loop controlled Pierce oscillator is used or whether full swing Pierce oscillator/external clock circuitry is used (refer to Section 1.10 Oscillator Conﬁguration).
Page 43 Device Overview S12XS Family 1.2.3.18 PM[7:6] — Port M I/O Pins 7-6 PM[7:6] are a general-purpose input or output pins. 1.2.3.19 PM5 / SCK0 — Port M I/O Pin 5 PM5 is a general-purpose input or output pin. It can be conﬁgured as the serial clock pin SCK of the serial peripheral interface 0 (SPI0).
Page 44 Device Overview S12XS Family 1.2.3.27 PP2 / KWP2 / PWM2 / TXD1 / IOC2 — Port P I/O Pin 2 PP2 is a general-purpose input or output pin. It can be conﬁgured as a keypad wakeup input. It can be conﬁgured as pulse width modulator (PWM) channel 2 output, TIM channel 2 or as the transmit pin TXD of serial communication interface 1 (SCI1).
Page 45 Device Overview S12XS Family 1.2.3.36 PS1 / TXD0 — Port S I/O Pin 1 PS1 is a general-purpose input or output pin. It can be conﬁgured as the transmit pin TXD of serial communication interface 0 (SCI0). 1.2.3.37 PS0 / RXD0 — Port S I/O Pin 0 PS0 is a general-purpose input or output pin.
Page 46 Device Overview S12XS Family 1.2.4.3 VDD, VSS2, VSS3 — Core Power Pins The voltage supply of nominally 1.8 V is derived from the internal voltage regulator. The return current path is through the VSS2 and VSS3 pins. No static external loading of these pins is permitted. 1.2.4.4 VDDF, VSS1 —...
Page 47 Device Overview S12XS Family Table 1-7. Power and Ground Connection Summary Nominal Mnemonic Description Voltage VDDPLL 1.8 V Provides operating voltage and ground for the phased-locked loop. This allows the VSSPLL supply voltage to the PLL to be bypassed independently. Internal power and ground generated by internal regulator.
Page 48 Device Overview S12XS Family System Clock Description The clock and reset generator module (CRG) provides the internal clock signals for the core and all peripheral modules. Figure 1-6 shows the clock connections from the CRG to all modules. Consult the S12XECRG section for details on clock generation. NOTE The XS family uses the XE family clock and reset generator module.
Page 49 Device Overview S12XS Family The clock generated by the PLL or oscillator provides the main system clock frequencies core clock and bus clock. As shown in Figure 1-6, these system clocks are used throughout the MCU to drive the core, the memories, and the peripherals.
Page 50 Device Overview S12XS Family 1.4.1.2 Special Single-Chip Mode This mode is used for debugging single-chip operation, boot-strapping, or security related operations. The background debug module BDM is active in this mode. The CPU executes a monitor program located in an on-chip ROM. BDM ﬁrmware waits for additional serial commands through the BKGD pin. 1.4.2 Power Modes The MCU features two main low-power modes.
Page 51 Device Overview S12XS Family 1.4.2.5 Run Mode Although this is not a low-power mode, unused peripheral modules should not be enabled in order to save power. 1.4.3 Freeze Mode The timer module, pulse width modulator, analog-to-digital converters, and the periodic interrupt timer provide a software programmable option to freeze the module status when the background debug module is active.
Page 52 Device Overview S12XS Family I-bit maskable service request is a conﬁguration register. It selects if the service request is enabled and the service request priority level. Table 1-10. Interrupt Vector Locations (Sheet 1 of 2) STOP WAIT Vector Address Interrupt Source Local Enable Mask Wake up...
Page 53 Device Overview S12XS Family Table 1-10. Interrupt Vector Locations (Sheet 2 of 2) STOP WAIT Vector Address Interrupt Source Local Enable Mask Wake up Wake up Vector base + $BA FLASH Fault Detect I bit FCNFG2 (SFDIE, DFDIE) Vector base + $B8 FLASH I bit FCNFG (CCIE)
Page 54 Device Overview S12XS Family 1.6.3.1 Flash Conﬁguration Reset Sequence Phase On each reset, the Flash module will hold CPU activity while loading Flash module registers from the Flash memory. If double faults are detected in the reset phase, Flash module protection and security may be active on leaving reset.
Page 55 Device Overview S12XS Family ATD0 Conﬁguration 1.7.1 External Trigger Input Connection The ATD module includes four external trigger inputs ETRIG0, ETRIG1, ETRIG2, and ETRIG3. The external trigger allows the user to synchronize ATD conversion to external trigger events. Table 1-13 shows the connection of the external trigger inputs.
Page 56 Device Overview S12XS Family BDM Clock Conﬁguration The BDM alternate clock source is the oscillator clock. 1.10 Oscillator Conﬁguration The XCLKS is an input signal which controls whether a crystal in combination with the internal loop controlled (low power) Pierce oscillator is used or whether full swing Pierce oscillator/external clock circuitry is used.
Page 57 Device Overview S12XS Family The selected oscillator conﬁguration is frozen with the rising edge of the RESET pin in any of these above described reset cases. EXTAL Crystal or Ceramic Resonator XTAL SSPLL Figure 1-7. Loop Controlled Pierce Oscillator Connections (XCLKS = 1) EXTAL Crystal or Ceramic Resonator...
Page 58 Device Overview S12XS Family S12XS Family Reference Manual, Rev. 1.13 Freescale Semiconductor...
Page 59: Chapter 2 Port Integration Module (S12Xspimv1)
Chapter 2 Port Integration Module (S12XSPIMV1) Revision History Revision Sections Revision Date Description of Changes Number Affected V01.07 08 Feb 2011 2.3.55/2-111 • Corrected addresses of PPSH,PIEH and PIFH in Register Descriptions 2.3.56/2-111 2.3.57/2-112 V01.08 08 Jul 2011 Table 2-2./2-65 •...
Page 60 Port Integration Module (S12XSPIMV1) NOTE This document assumes the availability of all features (112-pin package option). Some functions are not available on lower pin count package options. Refer to the pin-out summary section. 2.1.2 Features The Port Integration Module includes these distinctive registers: •...
Page 61 Port Integration Module (S12XSPIMV1) NOTE If there is more than one function associated with a pin, the priority is indicated by the position in the table from top (highest priority) to bottom (lowest priority) Table 2-1. Pin Functions and Priorities Pin Function Pin Function Port...
Page 62 Port Integration Module (S12XSPIMV1) Table 2-1. Pin Functions and Priorities (continued) Pin Function Pin Function Port Pin Name Description & Priority after Reset IOC7 I/O Timer Channel 7 GPIO (PWM7) I/O Pulse Width Modulator channel 7; emergency shut-down GPIO I/O General purpose IOC6 I/O Timer Channel 6 (PWM6)
Page 63 Port Integration Module (S12XSPIMV1) Table 2-1. Pin Functions and Priorities (continued) Pin Function Pin Function Port Pin Name Description & Priority after Reset PM[7:6] GPIO I/O General purpose GPIO (SCK0) I/O Serial Peripheral Interface 0 serial clock pin GPIO I/O General purpose (MOSI0) I/O Serial Peripheral Interface 0 master out/slave in pin GPIO...
Page 64 Port Integration Module (S12XSPIMV1) Table 2-1. Pin Functions and Priorities (continued) Pin Function Pin Function Port Pin Name Description & Priority after Reset PWM7 I/O Pulse Width Modulator channel 7; emergency shut-down GPIO GPIO/KWP7 I/O General purpose; with interrupt PP[6:3] PWM[6:3] O Pulse Width Modulator channel 6 - 3 GPIO/KWP[6:3]...
Page 65 Port Integration Module (S12XSPIMV1) 2.3.1 Memory Map Table 2-2 shows the register map of the Port Integration Module. Table 2-2. Block Memory Map Offset or Port Register Access Reset Value Section/Page Address 0x0000 PORTA—Port A Data Register 0x00 2.3.3/2-75 0x0001 PORTB—Port B Data Register 0x00 2.3.4/2-75...
Page 66 Port Integration Module (S12XSPIMV1) Table 2-2. Block Memory Map (continued) Offset or Port Register Access Reset Value Section/Page Address 0x0240 PTT—Port T Data Register 0x00 2.3.18/2-85 0x0241 PTIT—Port T Input Register 2.3.19/2-86 0x0242 DDRT—Port T Data Direction Register 0x00 2.3.20/2-87 0x0243 RDRT—Port T Reduced Drive Register 0x00...
Page 67 Port Integration Module (S12XSPIMV1) Table 2-2. Block Memory Map (continued) Offset or Port Register Access Reset Value Section/Page Address 0x0260 PTH—Port H Data Register 0x00 2.3.50/2-108 0x0261 PTIH—Port H Input Register 2.3.51/2-109 0x0262 DDRH—Port H Data Direction Register 0x00 2.3.52/2-109 0x0263 RDRH—Port H Reduced Drive Register 0x00...
Page 68 Port Integration Module (S12XSPIMV1) Register Bit 7 Bit 0 Name 0x0000 PORTA 0x0001 PORTB 0x0002 DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 DDRA 0x0003 DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 DDRB 0x0004 Reserved 0x0005 Reserved 0x0006 Reserved 0x0007 Reserved 0x0008...
Page 69 Port Integration Module (S12XSPIMV1) Register Bit 7 Bit 0 Name 0x001C NECLK NCLKX2 DIV16 EDIV4 EDIV3 EDIV2 EDIV1 EDIV0 ECLKCTL 0x001D Reserved 0x001E IRQE IRQEN IRQCR 0x001F Reserved 0x0020– 0x0031 Non-PIM Non-PIM Address Range Address Range 0x0032 PORTK 0x0033 DDRK7 DDRK5 DDRK4 DDRK3...
Page 70 Port Integration Module (S12XSPIMV1) Register Bit 7 Bit 0 Name 0x0246 Reserved 0x0247 PTTRR7 PTTRR6 PTTRR5 PTTRR4 PTTRR2 PTTRR1 PTTRR0 PTTRR 0x0248 PTS7 PTS6 PTS5 PTS4 PTS3 PTS2 PTS1 PTS0 0x0249 PTIS7 PTIS6 PTIS5 PTIS4 PTIS3 PTIS2 PTIS1 PTIS0 PTIS 0x024A DDRS7 DDRS6...
Page 71 Port Integration Module (S12XSPIMV1) Register Bit 7 Bit 0 Name 0x0256 WOMM7 WOMM6 WOMM5 WOMM4 WOMM3 WOMM2 WOMM1 WOMM0 WOMM 0x0257 MODRR7 MODRR6 MODRR4 MODRR 0x0258 PTP7 PTP6 PTP5 PTP4 PTP3 PTP2 PTP1 PTP0 0x0259 PTIP7 PTIP6 PTIP5 PTIP4 PTIP3 PTIP2 PTIP1 PTIP0...
Page 72 Port Integration Module (S12XSPIMV1) Register Bit 7 Bit 0 Name 0x0265 PPSH7 PPSH6 PPSH5 PPSH4 PPSH3 PPSH2 PPSH1 PPSH0 PPSH 0x0266 PIEH7 PIEH6 PIEH5 PIEH4 PIEH3 PIEH2 PIEH1 PIEH0 PIEH 0x0267 PIFH7 PIFH6 PIFH5 PIFH4 PIFH3 PIFH2 PIFH1 PIFH0 PIFH 0x0268 PTJ7 PTJ6...
Page 73 Port Integration Module (S12XSPIMV1) Register Bit 7 Bit 0 Name 0x0275 RDR1AD07 RDR1AD06 RDR1AD05 RDR1AD04 RDR1AD03 RDR1AD02 RDR1AD01 RDR1AD00 RDR1AD0 0x0276 PER0AD07 PER0AD06 PER0AD05 PER0AD04 PER0AD03 PER0AD02 PER0AD01 PER0AD00 PER0AD0 0x0277 PER1AD07 PER1AD06 PER1AD05 PER1AD04 PER1AD03 PER1AD02 PER1AD01 PER1AD00 PER1AD0 0x0278 Reserved 0x0279...
Page 74 Port Integration Module (S12XSPIMV1) Table 2-3. Pin Conﬁguration Summary Function Pull Device Interrupt Input Disabled Disabled Input Pull Up Disabled Input Pull Down Disabled Input Disabled Falling edge Input Disabled Rising edge Input Pull Up Falling edge Input Pull Down Rising edge Output, full drive to 0 Disabled...
Page 75 Port Integration Module (S12XSPIMV1) 2.3.3 Port A Data Register (PORTA) Address 0x0000 (PRR) Access: User read/write Reset Figure 2-1. Port A Data Register (PORTA) Read: Anytime, the data source depends on the data direction value Write: Anytime Table 2-4. PORTA Register Field Descriptions Field Description Port A general purpose input/output data—Data Register...
Page 76 Port Integration Module (S12XSPIMV1) 2.3.5 Port A Data Direction Register (DDRA) Address 0x0002 (PRR) Access: User read/write DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 Reset Figure 2-3. Port A Data Direction Register (DDRA) Read: Anytime, the data source depends on the data direction value Write: Anytime Table 2-6.
Page 77 Port Integration Module (S12XSPIMV1) 2.3.7 PIM Reserved Registers Address 0x0004 (PRR) to 0x0007 (PRR) Access: User read Reset = Unimplemented or Reserved Figure 2-5. PIM Reserved Registers Read: Always reads 0x00 Write: Unimplemented 2.3.8 Port E Data Register (PORTE) Address 0x0008 (PRR) Access: User read/write Altern.
Page 78 Port Integration Module (S12XSPIMV1) Table 2-8. PORTE Register Field Descriptions Field Description Port E general purpose input/output data—Data Register, ECLKX2 output, XCLKS input When not used with the alternative function, the associated pin can be used as general purpose I/O. In general purpose output mode the register bit value is driven to the pin.
Page 79 Port Integration Module (S12XSPIMV1) Table 2-9. DDRE Register Field Descriptions Field Description Port E Data Direction— DDRE This bit determines whether the associated pin is an input or output. 1 Associated pin conﬁgured as output 0 Associated pin conﬁgured as input 2.3.10 Ports ABEK, BKGD pin Pull-up Control Register (PUCR) Address 0x000C (PRR)
Page 80 Port Integration Module (S12XSPIMV1) Table 2-10. PUCR Register Field Descriptions (continued) Field Description Port B Pull-up Enable—Enable pull-up devices on all port input pins PUPBE This bit conﬁgures whether a pull-up device is activated on all associated port input pins. If a pin is used as output this bit has no effect.
Page 81 Port Integration Module (S12XSPIMV1) Table 2-11. RDRIV Register Field Descriptions (continued) Field Description Port B reduced drive—Select reduced drive for output port RDPB This bit conﬁgures the drive strength of all associated port output pins as either full or reduced. If a pin is used as input this bit has no effect.
Page 82 Port Integration Module (S12XSPIMV1) Table 2-12. ECLKCTL Register Field Descriptions Field Description No ECLK—Disable ECLK output NECLK This bit controls the availability of a free-running clock on the ECLK pin. This clock has a ﬁxed rate equivalent to the internal bus clock. 1 ECLK disabled 0 ECLK enabled No ECLKX2—Disable ECLKX2 output...
Page 83 Port Integration Module (S12XSPIMV1) 2.3.14 IRQ Control Register (IRQCR) Address 0x001E Access: User read/write IRQE IRQEN Reset = Unimplemented or Reserved Figure 2-12. IRQ Control Register (IRQCR) Read: See individual bit descriptions below Write: See individual bit descriptions below Table 2-13. IRQCR Register Field Descriptions Field Description IRQ select edge sensitive only—...
Page 84 Port Integration Module (S12XSPIMV1) Read: Always reads 0x00 Write: Unimplemented 2.3.16 Port K Data Register (PORTK) Address 0x0032 (PRR) Access: User read/write Reset Figure 2-14. Port K Data Register (PORTK) Read: Anytime, the data source depends on the data direction value Write: Anytime Table 2-14.
Page 85 Port Integration Module (S12XSPIMV1) Table 2-15. DDRK Register Field Descriptions Field Description 7,5-0 Port K Data Direction— DDRK This bit determines whether the associated pin is an input or output. 1 Associated pin conﬁgured as output 0 Associated pin conﬁgured as input 2.3.18 Port T Data Register (PTT) Address 0x0240...
Page 86 Port Integration Module (S12XSPIMV1) Table 2-16. PTT Register Field Descriptions (continued) Field Description Port T general purpose input/output data—Data Register, TIM output, routed PWM output, VREG_API output When not used with the alternative function, the associated pin can be used as general purpose I/O. In general purpose output mode the register bit value is driven to the pin.
Page 87 Port Integration Module (S12XSPIMV1) 2.3.20 Port T Data Direction Register (DDRT) Address 0x0242 Access: User read/write DDRT7 DDRT6 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0 Reset Figure 2-18. Port T Data Direction Register (DDRT) Read: Anytime Write: Anytime Table 2-18. DDRT Register Field Descriptions Field Description 7-6, 4...
Page 88 Port Integration Module (S12XSPIMV1) Read: Anytime Write: Anytime Table 2-19. RDRT Register Field Descriptions Field Description Port T reduced drive—Select reduced drive for output pin RDRT This bit conﬁgures the drive strength of the associated output pin as either full or reduced. If a pin is used as input this bit has no effect.
Page 89 Port Integration Module (S12XSPIMV1) Table 2-21. PPST Register Field Descriptions Field Description Port T pull device select—Conﬁgure pull device polarity on input pin PPST This bit selects a pull-up or a pull-down device if enabled on the associated port input pin. 1 A pull-down device selected 0 A pull-up device selected 2.3.24...
Page 90 Port Integration Module (S12XSPIMV1) Table 2-22. PTTRR Register Field Descriptions Field Description Port T peripheral routing— PTTRR This register controls the routing of PWM channel 7. 1 PWM7 routed to PT7 0 PWM7 routed to PP7 Port T peripheral routing— PTTRR This register controls the routing of PWM channel 6.
Page 91 Port Integration Module (S12XSPIMV1) 2.3.26 Port S Data Register (PTS) Address 0x0248 Access: User read/write PTS7 PTS6 PTS5 PTS4 PTS3 PTS2 PTS1 PTS0 Altern. SCK0 MOSI0 MISO0 TXD1 RXD1 TXD0 RXD0 Function Reset Figure 2-24. Port S Data Register (PTS) Read: Anytime, the data source depends on the data direction value Write: Anytime Table 2-23.
Page 92 Port Integration Module (S12XSPIMV1) Table 2-23. PTS Register Field Descriptions (continued) Field Description Port S general purpose input/output data—Data Register, SCI1 TXD output When not used with the alternative function, the associated pin can be used as general purpose I/O. In general purpose output mode the register bit value is driven to the pin.
Page 93 Port Integration Module (S12XSPIMV1) Table 2-24. PTIS Register Field Descriptions Field Description Port S input data— PTIS A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit conditions on output pins. 2.3.28 Port S Data Direction Register (DDRS) Address 0x0249...
Page 94 Port Integration Module (S12XSPIMV1) 2.3.29 Port S Reduced Drive Register (RDRS) Address 0x024A Access: User read/write RDRS7 RDRS6 RDRS5 RDRS4 RDRS3 RDRS2 RDRS1 RDRS0 Reset Figure 2-27. Port S Reduced Drive Register (RDRS) Read: Anytime Write: Anytime Table 2-26. RDRS Register Field Descriptions Field Description Port S reduced drive—Select reduced drive for output pin...
Page 95 Port Integration Module (S12XSPIMV1) 2.3.31 Port S Polarity Select Register (PPSS) Address 0x024C Access: User read/write PPSS7 PPSS6 PPSS5 PPSS4 PPSS3 PPSS2 PPSS1 PPSS0 Reset Figure 2-29. Port S Polarity Select Register (PPSS) Read: Anytime Write: Anytime Table 2-28. PPSS Register Field Descriptions Field Description Port S pull device select—Conﬁgure pull device polarity on input pin...
Page 96 Port Integration Module (S12XSPIMV1) 2.3.33 PIM Reserved Register Address 0x024F Access: User read Reset = Unimplemented or Reserved u = Unaffected by reset Figure 2-31. PIM Reserved Register Read: Always reads 0x00 Write: Unimplemented 2.3.34 Port M Data Register (PTM) Address 0x0250 Access: User read/write PTM7...
Page 97 Port Integration Module (S12XSPIMV1) Table 2-30. PTM Register Field Descriptions (continued) Field Description Port M general purpose input/output data—Data Register, routed SPI0 MOSI input/output When not used with the alternative function, the associated pin can be used as general purpose I/O. In general purpose output mode the register bit value is driven to the pin.
Page 98 Port Integration Module (S12XSPIMV1) 2.3.35 Port M Input Register (PTIM) Address 0x0251 Access: User read PTIM7 PTIM6 PTIM5 PTIM4 PTIM3 PTIM2 PTIM1 PTIM0 Reset = Unimplemented or Reserved u = Unaffected by reset Figure 2-33. Port M Input Register (PTIM) Read: Anytime Write:Never, writes to this register have no effect Table 2-31.
Page 99 Port Integration Module (S12XSPIMV1) Table 2-32. DDRM Register Field Descriptions Field Description Port M data direction— DDRM This bit determines whether the associated pin is an input or output. 1 Associated pin conﬁgured as output 0 Associated pin conﬁgured as input Port M data direction—...
Page 100 Port Integration Module (S12XSPIMV1) 2.3.38 Port M Pull Device Enable Register (PERM) Address 0x0254 Access: User read/write PERM7 PERM6 PERM5 PERM4 PERM3 PERM2 PERM1 PERM0 Reset Figure 2-36. Port M Pull Device Enable Register (PERM) Read: Anytime Write: Anytime Table 2-34. PERM Register Field Descriptions Field Description Port M pull device enable—Enable pull device on input pin or wired-or output pin...
Page 101 Port Integration Module (S12XSPIMV1) 2.3.40 Port M Wired-Or Mode Register (WOMM) Address 0x0256 Access: User read/write WOMM7 WOMM6 WOMM5 WOMM4 WOMM3 WOMM2 WOMM1 WOMM0 Reset Figure 2-38. Port M Wired-Or Mode Register (WOMM) Read: Anytime Write: Anytime Table 2-36. WOMM Register Field Descriptions Field Description Port M wired-or mode—Enable open-drain functionality on output pin...
Page 102 Port Integration Module (S12XSPIMV1) Table 2-37. SCI1 Routing MODRRx Related Pins Reserved Reserved Defaults to reset value Table 2-38. SPI0 Routing MODRRx Related Pins MISO0 MOSI0 SCK0 2.3.42 Port P Data Register (PTP) Address 0x0258 Access: User read/write PTP7 PTP6 PTP5 PTP4 PTP3...
Page 103 Port Integration Module (S12XSPIMV1) Table 2-39. PTP Register Field Descriptions Field Description Port P general purpose input/output data—Data Register, PWM input/output, pin interrupt input/output When not used with the alternative function, the associated pin can be used as general purpose I/O. In general purpose output mode the register bit value is driven to the pin.
Page 104 Port Integration Module (S12XSPIMV1) Table 2-39. PTP Register Field Descriptions (continued) Field Description Port P general purpose input/output data—Data Register, PWM output, routed TIM output, pin interrupt input/output When not used with the alternative function, the associated pin can be used as general purpose I/O. In general purpose output mode the register bit value is driven to the pin.
Page 105 Port Integration Module (S12XSPIMV1) 2.3.44 Port P Data Direction Register (DDRP) Address 0x025A Access: User read/write DDRP7 DDRP6 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0 Reset Figure 2-42. Port P Data Direction Register (DDRP) Read: Anytime Write: Anytime Table 2-41. DDRP Register Field Descriptions Field Description Port P data direction—...
Page 106 Port Integration Module (S12XSPIMV1) 2.3.45 Port P Reduced Drive Register (RDRP) Address 0x025B Access: User read/write RDRP7 RDRP6 RDRP5 RDRP4 RDRP3 RDRP2 RDRP1 RDRP0 Reset Figure 2-43. Port P Reduced Drive Register (RDRP) Read: Anytime Write: Anytime Table 2-42. RDRP Register Field Descriptions Field Description Port P reduced drive—Select reduced drive for output pin...
Page 107 Port Integration Module (S12XSPIMV1) 2.3.47 Port P Polarity Select Register (PPSP) Address 0x025D Access: User read/write PPSP7 PPSP6 PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSP0 Reset Figure 2-45. Port P Polarity Select Register (PPSP) Read: Anytime Write: Anytime Table 2-44. PPSP Register Field Descriptions Field Description Port P pull device select—Conﬁgure pull device and pin interrupt edge polarity on input pin...
Page 108 Port Integration Module (S12XSPIMV1) 2.3.49 Port P Interrupt Flag Register (PIFP) Address 0x025F Access: User read/write PIFP7 PIFP6 PIFP5 PIFP4 PIFP3 PIFP2 PIFP1 PIFP0 Reset Figure 2-47. Port P Interrupt Flag Register (PIFP) Read: Anytime Write: Anytime Table 2-46. PIFP Register Field Descriptions Field Description Port P interrupt ﬂag—...
Page 109 Port Integration Module (S12XSPIMV1) 2.3.51 Port H Input Register (PTIH) Address 0x0261 Access: User read PTIH7 PTIH6 PTIH5 PTIH4 PTIH3 PTIH2 PTIH1 PTIH0 Reset = Unimplemented or Reserved u = Unaffected by reset Figure 2-49. Port H Input Register (PTIH) Read: Anytime Write:Never, writes to this register have no effect Table 2-48.
Page 110 Port Integration Module (S12XSPIMV1) 2.3.53 Port H Reduced Drive Register (RDRH) Address 0x0263 Access: User read/write RDRH7 RDRH6 RDRH5 RDRH4 RDRH3 RDRH2 RDRH1 RDRH0 Reset Figure 2-51. Port H Reduced Drive Register (RDRH) Read: Anytime Write: Anytime Table 2-50. RDRH Register Field Descriptions Field Description Port H reduced drive—Select reduced drive for output pin...
Page 111 Port Integration Module (S12XSPIMV1) 2.3.55 Port H Polarity Select Register (PPSH) Address 0x0265 Access: User read/write PPSH7 PPSH6 PPSH5 PPSH4 PPSH3 PPSH2 PPSH1 PPSH0 Reset Figure 2-53. Port H Polarity Select Register (PPSH) Read: Anytime Write: Anytime Table 2-52. PPSH Register Field Descriptions Field Description Port H pull device select—Conﬁgure pull device and pin interrupt edge polarity on input pin...
Page 112 Port Integration Module (S12XSPIMV1) 2.3.57 Port H Interrupt Flag Register (PIFH) Address 0x0267 Access: User read/write PIFH7 PIFH6 PIFH5 PIFH4 PIFH3 PIFH2 PIFH1 PIFH0 Reset Figure 2-55. Port H Interrupt Flag Register (PIFH) Read: Anytime Write: Anytime Table 2-54. PIFH Register Field Descriptions Field Description Port H interrupt ﬂag—...
Page 113 Port Integration Module (S12XSPIMV1) 2.3.59 Port J Input Register (PTIJ) Address 0x0269 Access: User read PTIJ7 PTIJ6 PTIJ1 PTIJ0 Reset = Unimplemented or Reserved u = Unaffected by reset Figure 2-57. Port J Input Register (PTIJ) Read: Anytime Write:Never, writes to this register have no effect Table 2-56.
Page 114 Port Integration Module (S12XSPIMV1) 2.3.61 Port J Reduced Drive Register (RDRJ) Address 0x026B Access: User read/write RDRJ7 RDRJ6 RDRJ1 RDRJ0 Reset Figure 2-59. Port J Reduced Drive Register (RDRJ) Read: Anytime Write: Anytime Table 2-58. RDRJ Register Field Descriptions Field Description 7-6, 1-0 Port J reduced drive—Select reduced drive for outputs...
Page 115 Port Integration Module (S12XSPIMV1) 2.3.63 Port J Polarity Select Register (PPSJ) Address 0x026D Access: User read/write PPSJ7 PPSJ6 PPSJ1 PPSJ0 Reset Figure 2-61. Port J Polarity Select Register (PPSJ) Read: Anytime Write: Anytime Table 2-60. PPSJ Register Field Descriptions Field Description 7-6, 1-0 Port J pull device select—Conﬁgure pull device and pin interrupt edge polarity on input pin...
Page 116 Port Integration Module (S12XSPIMV1) 2.3.65 Port J Interrupt Flag Register (PIFJ) Address 0x026F Access: User read/write PIFJ7 PIFJ6 PIFJ1 PIFJ0 Reset Figure 2-63. Port J Interrupt Flag Register (PIFJ) Read: Anytime Write: Anytime Table 2-62. PIFJ Register Field Descriptions Field Description 7-6, 1-0 Port J interrupt ﬂag—...
Page 117 Port Integration Module (S12XSPIMV1) 2.3.67 Port AD0 Data Register 1 (PT1AD0) Address 0x0271 Access: User read/write PT1AD07 PT1AD06 PT1AD05 PT1AD04 PT1AD03 PT1AD02 PT1AD01 PT1AD00 Altern. Function Reset Figure 2-65. Port AD0 Data Register 1 (PT1AD0) Read: Anytime, the data source depends on the data direction value Write: Anytime Table 2-64.
Page 118 Port Integration Module (S12XSPIMV1) 2.3.69 Port AD0 Data Direction Register 1 (DDR1AD0) Address 0x0273 Access: User read/write DDR1AD07 DDR1AD06 DDR1AD05 DDR1AD04 DDR1AD03 DDR1AD02 DDR1AD01 DDR1AD00 Reset Figure 2-67. Port AD0 Data Direction Register 1 (DDR1AD0) Read: Anytime Write: Anytime Table 2-66. DDR1AD0 Register Field Descriptions Field Description Port AD0 data direction—...
Page 119 Port Integration Module (S12XSPIMV1) 2.3.71 Port AD0 Reduced Drive Register 1 (RDR1AD0) Address 0x0275 Access: User read/write RDR1AD07 RDR1AD06 RDR1AD05 RDR1AD04 RDR1AD03 RDR1AD02 RDR1AD01 RDR1AD00 Reset Figure 2-69. Port AD0 Reduced Drive Register 1 (RDR1AD0) Read: Anytime Write: Anytime Table 2-68. RDR1AD0 Register Field Descriptions Field Description Port AD0 reduced drive—Select reduced drive for output pin...
Page 120 Port Integration Module (S12XSPIMV1) 2.3.73 Port AD0 Pull Up Enable Register 1 (PER1AD0) Address 0x0277 Access: User read/write PER1AD07 PER1AD06 PER1AD05 PER1AD04 PER1AD03 PER1AD02 PER1AD01 PER1AD00 Reset Figure 2-71. Port AD0 Pull Up Enable Register 1 (PER1AD0) Read: Anytime Write: Anytime Table 2-70.
Page 121 Port Integration Module (S12XSPIMV1) 2.4.2 Registers A set of conﬁguration registers is common to all ports with exception of the ATD port (Table 2-71). All registers can be written at any time, however a speciﬁc conﬁguration might not become active. For example selecting a pull-up device: This device does not become active while the port is used as a push-pull output.
Page 122 Port Integration Module (S12XSPIMV1) NOTE Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on port data or port input registers, when changing the data direction register. data out Module output enable module enable...
Page 123 Port Integration Module (S12XSPIMV1) 2.4.2.7 Wired-or mode register (WOMx) If the pin is used as an output this register turns off the active high drive. This allows wired-or type connections of outputs. 2.4.2.8 Interrupt enable register (PIEx) If the pin is used as an interrupt input this register serves as a mask to the interrupt ﬂag to enable/disable the interrupt.
Page 124 Port Integration Module (S12XSPIMV1) Port E pin PE[1] can be used for either general-purpose input or as the level- or falling edge-sensitive IRQ interrupt input. IRQ will be enabled by setting the IRQEN conﬁguration bit (2.3.14/2-83) and clearing the I-bit in the CPU condition code register. It is inhibited at reset so this pin is initially conﬁgured as a simple input with a pull-up.
Page 125 Port Integration Module (S12XSPIMV1) Port P pins PP[7:3] can be used for either general purpose I/O with pin interrupt capability, or with the PWM or with the channels of the standard Timer.subsystem. Port P pins PP[2,0] can be used for either general purpose I/O, or with the PWM or with the TIM or with the SCI1 subsystem.
Page 126 Port Integration Module (S12XSPIMV1) Table 2-72. Pulse Detection Criteria Mode Pulse STOP STOP Unit ≤ 3 ≤ t Ignored bus clocks pulse pulse pign 3 < t < 4 < t < t Uncertain bus clocks pulse pign pulse pval ≥...
Page 127: Chapter 3 Memory Mapping Control (S12Xmmcv4)
Chapter 3 Memory Mapping Control (S12XMMCV4) Revision History Rev. No. Date (Submitted Sections Substantial Change(s) (Item No.) Affected v04.09 01-Feb-08 - Minor changes v04.10 17-Feb-09 - Minor changes v04.11 30-Jun-10 3.3.2.7/3-139 - Removed confusing statements in EPAGE description Introduction This section describes the functionality of the module mapping control (MMC) sub-block of the S12X platform.
Page 128 Memory Mapping Control (S12XMMCV4) 3.1.1 Terminology Table 3-1. Acronyms and Abbreviations Logic level “1” Voltage that corresponds to Boolean true state Logic level “0” Voltage that corresponds to Boolean false state Represents hexadecimal number Represents logic level ’don’t care’ Byte 8-bit data word 16-bit data...
Page 129 Memory Mapping Control (S12XMMCV4) 3.1.3 S12X Memory Mapping The S12X architecture implements a number of memory mapping schemes including • a CPU 8MB global map, deﬁned using a global page (GPAGE) register and dedicated 23-bit address load/store instructions. • a BDM 8MB global map, deﬁned using a global page (BDMGPR) register and dedicated 23-bit address load/store instructions.
Page 130 Memory Mapping Control (S12XMMCV4) Address Decoder & Priority Target Bus Controller Data FLASH PGMFLASH Peripherals Figure 3-1. MMC Block Diagram External Signal Description The user is advised to refer to the SoC Guide for port conﬁguration and location of external bus signals. Some pins may not be bonded out in all implementations.
Page 131 Memory Mapping Control (S12XMMCV4) Memory Map and Registers 3.3.1 Module Memory Map A summary of the registers associated with the MMC block is shown in Figure 3-2. Detailed descriptions of the registers and bits are given in the subsections that follow. Register Address Bit 7...
Page 132 Memory Mapping Control (S12XMMCV4) 3.3.2.1 Mode Register (MODE) Address: 0x000B PRR MODC Reset MODC 1. External signal (see Table 3-2). = Unimplemented or Reserved Figure 3-3. Mode Register (MODE) Read: Anytime. Write: Only if a transition is allowed (see Figure 3-5).
Page 133 Memory Mapping Control (S12XMMCV4) 3.3.2.2 Global Page Index Register (GPAGE) Address: 0x0010 Reset = Unimplemented or Reserved Figure 3-6. Global Page Index Register (GPAGE) Read: Anytime Write: Anytime The global page index register is used to construct a 23 bit address in the global map format. It is only used when the CPU is executing a global instruction (GLDAA, GLDAB, GLDD, GLDS, GLDX, GLDY,GSTAA, GSTAB, GSTD, GSTS, GSTX, GSTY) (see CPU Block Guide).
Page 134 Memory Mapping Control (S12XMMCV4) 3.3.2.3 Direct Page Register (DIRECT) Address: 0x0011 DP15 DP14 DP13 DP12 DP11 DP10 Reset Figure 3-8. Direct Register (DIRECT) Read: Anytime Write: anytime in special modes, one time only in other modes. This register determines the position of the 256B direct page within the memory map.It is valid for both global and local mapping scheme.
Page 135 Memory Mapping Control (S12XMMCV4) 3.3.2.4 MMC Control Register (MMCCTL1) Address: 0x0013 PRR MGRAMON DFIFRON PGMIFRON Reset = Unimplemented or Reserved Figure 3-10. MMC Control Register (MMCCTL1) Read: Anytime. . Write: Refer to each bit description. Table 3-6. MMCCTL1 Field Descriptions Field Description Flash Memory Controller SCRATCH RAM visible in the global memory map...
Page 136 Memory Mapping Control (S12XMMCV4) Write: Anytime These eight index bits are used to page 16KB blocks into the Flash page window located in the local (CPU or BDM) memory map from address 0x8000 to address 0xBFFF (see Figure 3-12). This supports accessing up to 4MB of Flash (in the Global map) within the 64KB Local map.
Page 137 Memory Mapping Control (S12XMMCV4) Read: Anytime Write: Anytime These eight index bits are used to page 4KB blocks into the RAM page window located in the local (CPU or BDM) memory map from address 0x1000 to address 0x1FFF (see Figure 3-14).
Page 138 Memory Mapping Control (S12XMMCV4) The two ﬁxed 4KB pages (0xFE, 0xFF) contain unimplemented area in the range not occupied by RAM if RAMSIZE is less than 8KB (Refer to Section 3.4.2.3, “Implemented Memory Map). S12XS Family Reference Manual, Rev. 1.13 Freescale Semiconductor...
Page 139 Memory Mapping Control (S12XMMCV4) 3.3.2.7 Data FLASH Page Index Register (EPAGE) Address: 0x0017 Reset Figure 3-15. Data FLASH Page Index Register (EPAGE) Read: Anytime Write: Anytime These eight index bits are used to page 1KB blocks into the Data FLASH page window located in the local (CPU or BDM) memory map from address 0x0800 to address 0x0BFF (see Figure 3-16).
Page 140 Memory Mapping Control (S12XMMCV4) Functional Description The MMC block performs several basic functions of the S12X sub-system operation: MCU operation modes, priority control, address mapping, select signal generation and access limitations for the system. Each aspect is described in the following subsections. 3.4.1 MCU Operating Mode •...
Page 141 Memory Mapping Control (S12XMMCV4) CPU and BDM Global Memory Map Local Memory Map 0x00_0000 2KB REGISTERS 0x00_0800 2KB RAM 0x00_1000 253*4KB paged 0x0F_E000 0x0000 2KB REGISTERS 8KB RAM 0x0800 EPAGE 1KB Data Flash window 0x10_0000 0x0C00 Reserved 0x1000 Data FLASH RPAGE 4KB RAM window 256*1KB paged...
Page 142 Memory Mapping Control (S12XMMCV4) 3.4.2.1.1 Expansion of the Local Address Map Expansion of the CPU Local Address Map The program page index register in MMC allows accessing up to 4MB of FLASH or ROM in the global memory map by using the eight page index bits to page 256 16KB blocks into the program page window located from address 0x8000 to address 0xBFFF in the local CPU memory map.
Page 143 Memory Mapping Control (S12XMMCV4) Expansion of the BDM Local Address Map PPAGE, RPAGE, and EPAGE registers are also used for the expansion of the BDM local address to the global address. These registers can be read and written by the BDM. The BDM expansion scheme is the same as the CPU expansion scheme.
Page 144 Memory Mapping Control (S12XMMCV4) BDM HARDWARE COMMAND Global Address [22:0] Bit22 Bit16 Bit15 Bit0 BDMGPR Register [6:0] BDM Local Address BDM FIRMWARE COMMAND Global Address [22:0] Bit22 Bit16 Bit15 Bit0 BDMGPR Register [6:0] CPU Local Address Figure 3-18. BDMGPR Address Mapping 3.4.2.3 Implemented Memory Map The global memory spaces reserved for the internal resources (RAM, Data FLASH, and FLASH) are not...
Page 145 Memory Mapping Control (S12XMMCV4) In single-chip modes accesses by the CPU (except for ﬁrmware commands) to any of the unimplemented areas (see Figure 3-19) will result in an illegal access reset (system reset) in case of no MPU error. BDM accesses to the unimplemented areas are allowed but the data will be undeﬁned.No misaligned word access from the BDM module will occur;...
Page 146 Memory Mapping Control (S12XMMCV4) CPU and BDM Global Memory Map Local Memory Map 0x00_0000 2K REGISTERS 0x00_07FF Unimplemented RAM_LOW 0x0000 2K REGISTERS 0x0800 0x0F_FFFF EPAGE 1K Data Flash window 0x0C00 Reserved Data FLASH DF_HIGH 0x1000 RPAGE 4K RAM window 0x2000 Data FLASH 8K RAM Resources...
Page 147 Memory Mapping Control (S12XMMCV4) 3.4.3 Chip Bus Control The MMC controls the address buses and the data buses that interface the S12X masters (CPU, BDM ) with the rest of the system (master buses). In addition the MMC handles all CPU read data bus swapping operations.
Page 148 Memory Mapping Control (S12XMMCV4) 3.4.3.1 Master Bus Prioritization regarding access conﬂicts on Target Buses The arbitration scheme allows only one master to be connected to a target at any given time. The following rules apply when prioritizing accesses from different masters to the same target bus: •...
Page 149 Memory Mapping Control (S12XMMCV4) During the execution of an RTC instruction the CPU performs the following steps: 1. Pulls the previously stored PPAGE value from the stack 2. Pulls the 16-bit return address from the stack and loads it into the PC 3.
Page 150 Memory Mapping Control (S12XMMCV4) S12XS Family Reference Manual, Rev. 1.13 Freescale Semiconductor...
Page 151: Chapter 4 Interrupt (S12Xintv2)
Chapter 4 Interrupt (S12XINTV2) Table 4-1. Revision History Revision Sections Revision Date Description of Changes Number Affected V02.00 01 Jul 2005 4.1.2/4-152 Initial V2 release, added new features: - XGATE threads can be interrupted. - SYS instruction vector. - Access violation interrupt vectors. V02.04 11 Jan 2007 4.3.2.2/4-157...
Page 152 Interrupt (S12XINTV2) 4.1.1 Glossary The following terms and abbreviations are used in the document. Table 4-2. Terminology Term Meaning Condition Code Register (in the S12X CPU) Direct Memory Access Interrupt Interrupt Processing Level Interrupt Service Routine Micro-Controller Unit XGATE refers to the XGATE co-processor; XGATE is an optional feature refers to the interrupt request associated with the IRQ pin XIRQ refers to the interrupt request associated with the XIRQ pin...
Page 153 Interrupt (S12XINTV2) 4.1.3 Modes of Operation • Run mode This is the basic mode of operation. • Wait mode In wait mode, the XINT module is frozen. It is however capable of either waking up the CPU if an interrupt occurs or waking up the XGATE if an XGATE request occurs. Please refer to Section 4.5.3, “Wake Up from Stop or Wait Mode”...
Page 154 Interrupt (S12XINTV2) 4.1.4 Block Diagram Figure 4-1 shows a block diagram of the XINT module. Peripheral Wake Up Interrupt Requests Non I Bit Maskable Channels Vector Address IRQ Channel IVBR Interrupt Requests PRIOLVL2 PRIOLVL1 Current RQST PRIOLVL0 One Set Per Channel (Up to 108 Channels) INT_XGPRIO XGATE...
Page 155 Interrupt (S12XINTV2) Memory Map and Register Deﬁnition This section provides a detailed description of all registers accessible in the XINT module. 4.3.1 Module Memory Map Table 4-3 gives an overview over all XINT module registers. Table 4-3. XINT Memory Map Address Access 0x0120...
Page 156 Interrupt (S12XINTV2) 4.3.2 Register Descriptions This section describes in address order all the XINT module registers and their individual bits. Register Address Bit 7 Bit 0 Name 0x0121 IVBR IVB_ADDR[7:0]7 0x0126 INT_XGPRIO XILVL[2:0] 0x0127 INT_CFADDR INT_CFADDR[7:4] 0x0128 INT_CFDATA0 R RQST PRIOLVL[2:0] 0x0129 INT_CFDATA1 R RQST...
Page 157 Interrupt (S12XINTV2) 4.3.2.1 Interrupt Vector Base Register (IVBR) Address: 0x0121 IVB_ADDR[7:0] Reset Figure 4-3. Interrupt Vector Base Register (IVBR) Read: Anytime Write: Anytime Table 4-4. IVBR Field Descriptions Field Description 7–0 Interrupt Vector Base Address Bits — These bits represent the upper byte of all vector addresses. Out of IVB_ADDR[7:0] reset these bits are set to 0xFF (i.e., vectors are located at 0xFF10–0xFFFE) to ensure compatibility to previous S12 microcontrollers.
Page 158 Interrupt (S12XINTV2) Table 4-6. XGATE Interrupt Priority Levels Priority XILVL2 XILVL1 XILVL0 Meaning Interrupt request is disabled Priority level 1 Priority level 2 Priority level 3 Priority level 4 Priority level 5 Priority level 6 high Priority level 7 4.3.2.3 Interrupt Request Conﬁguration Address Register (INT_CFADDR) Address: 0x0127 INT_CFADDR[7:4]...
Page 159 Interrupt (S12XINTV2) Address: 0x0128 RQST PRIOLVL[2:0] Reset = Unimplemented or Reserved Figure 4-6. Interrupt Request Conﬁguration Data Register 0 (INT_CFDATA0) 1. Please refer to the notes following the PRIOLVL[2:0] description below. Address: 0x0129 RQST PRIOLVL[2:0] Reset = Unimplemented or Reserved Figure 4-7.
Page 160 Interrupt (S12XINTV2) Address: 0x012C RQST PRIOLVL[2:0] Reset = Unimplemented or Reserved Figure 4-10. Interrupt Request Conﬁguration Data Register 4 (INT_CFDATA4) 1. Please refer to the notes following the PRIOLVL[2:0] description below. Address: 0x012D RQST PRIOLVL[2:0] Reset = Unimplemented or Reserved Figure 4-11.
Page 161 Interrupt (S12XINTV2) Table 4-8. INT_CFDATA0–7 Field Descriptions Field Description XGATE Request Enable — This bit determines if the associated interrupt request is handled by the CPU or by RQST the XGATE module. 0 Interrupt request is handled by the CPU 1 Interrupt request is handled by the XGATE module Note: The IRQ interrupt cannot be handled by the XGATE module.
Page 162 Interrupt (S12XINTV2) 4.4.1 S12X Exception Requests The CPU handles both reset requests and interrupt requests. The XINT module contains registers to conﬁgure the priority level of each I bit maskable interrupt request which can be used to implement an interrupt priority scheme. This also includes the possibility to nest interrupt requests. A priority decoder is used to evaluate the priority of a pending interrupt request.
Page 163 Interrupt (S12XINTV2) 4.4.3 XGATE Requests If the XGATE module is implemented on the device, the XINT module is also used to process all exception requests to be serviced by the XGATE module. The overall priority level of those exceptions is discussed in the subsections below.
Page 164 Interrupt (S12XINTV2) NOTE Care must be taken to ensure that all exception requests remain active until the system begins execution of the applicable service routine; otherwise, the exception request may not get processed at all or the result may be a spurious interrupt request (vector at address (vector base + 0x0010)).
Page 165 Interrupt (S12XINTV2) Initialization/Application Information 4.5.1 Initialization After system reset, software should: • Initialize the interrupt vector base register if the interrupt vector table is not located at the default location (0xFF10–0xFFF9). • Initialize the interrupt processing level conﬁguration data registers (INT_CFADDR, INT_CFDATA0–7) for all interrupt vector requests with the desired priority levels and the request target (CPU or XGATE module).
Page 166 Interrupt (S12XINTV2) Stacked IPL IPL in CCR Processing Levels L3 (Pending) L1 (Pending) Reset Figure 4-14. Interrupt Processing Example 4.5.3 Wake Up from Stop or Wait Mode 4.5.3.1 CPU Wake Up from Stop or Wait Mode Only I bit maskable interrupt requests which are conﬁgured to be handled by the CPU are capable of waking the MCU from wait mode.
Page 167 Interrupt (S12XINTV2) 4.5.3.2 XGATE Wake Up from Stop or Wait Mode Interrupt request channels which are conﬁgured to be handled by the XGATE module are capable of waking up the XGATE module. Interrupt request channels handled by the XGATE module do not affect the state of the CPU.
Page 168 Interrupt (S12XINTV2) S12XS Family Reference Manual, Rev. 1.13 Freescale Semiconductor...
Page 169: Chapter 5 Background Debug Module (S12Xbdmv2)
Chapter 5 Background Debug Module (S12XBDMV2) Table 5-1. Revision History Revision Sections Revision Date Description of Changes Number Affected V02.00 07 Mar 2006 - First version of S12XBDMV2 V02.01 14 May 2008 - Introduced standardized Revision History Table V02.02 12 Sep 2012 - Minor formatting corrections Introduction This section describes the functionality of the background debug module (BDM) sub-block of the...
Page 170 Background Debug Module (S12XBDMV2) • Hardware handshake protocol to increase the performance of the serial communication • Active out of reset in special single chip mode • Nine hardware commands using free cycles, if available, for minimal CPU intervention • Hardware commands not requiring active BDM •...
Page 171 Background Debug Module (S12XBDMV2) 5.1.2.3 Low-Power Modes The BDM can be used until all bus masters (e.g., CPU or XGATE or others depending on which masters are available on the SOC) are in stop mode. When CPU is in a low power mode (wait or stop mode) all BDM ﬁrmware commands as well as the hardware BACKGROUND command can not be used respectively are ignored.
Page 172 Background Debug Module (S12XBDMV2) Memory Map and Register Deﬁnition 5.3.1 Module Memory Map Table 5-2 shows the BDM memory map when BDM is active. Table 5-2. BDM Memory Map Size Global Address Module (Bytes) 0x7FFF00–0x7FFF0B BDM registers 0x7FFF0C–0x7FFF0E BDM ﬁrmware ROM 0x7FFF0F Family ID (part of BDM ﬁrmware ROM) 0x7FFF10–0x7FFFFF...
Page 173 Background Debug Module (S12XBDMV2) Global Register Bit 7 Bit 0 Address Name 0x7FFF07 BDMCCRH R CCR10 CCR9 CCR8 0x7FFF08 BDMGPR BGAE BGP6 BGP5 BGP4 BGP3 BGP2 BGP1 BGP0 0x7FFF09 Reserved 0x7FFF0A Reserved 0x7FFF0B Reserved = Unimplemented, Reserved = Implemented (do not alter) = Indeterminate = Always read zero Figure 5-2.
Page 174 Background Debug Module (S12XBDMV2) Read: All modes through BDM operation when not secured Write: All modes through BDM operation when not secured, but subject to the following: — ENBDM should only be set via a BDM hardware command if the BDM ﬁrmware commands are needed.
Page 175 Background Debug Module (S12XBDMV2) Table 5-3. BDMSTS Field Descriptions (continued) Field Description Clock Switch — The CLKSW bit controls which clock the BDM operates with. It is only writable from a hardware CLKSW BDM command. A minimum delay of 150 cycles at the clock speed that is active during the data portion of the command send to change the clock source should occur before the next command can be send.
Page 176 Background Debug Module (S12XBDMV2) 5.3.2.2 BDM CCR LOW Holding Register (BDMCCRL) Register Global Address 0x7FFF06 CCR7 CCR6 CCR5 CCR4 CCR3 CCR2 CCR1 CCR0 Reset Special Single-Chip Mode All Other Modes Figure 5-4. BDM CCR LOW Holding Register (BDMCCRL) Read: All modes through BDM operation when not secured Write: All modes through BDM operation when not secured NOTE When BDM is made active, the CPU stores the content of its CCR...
Page 177 Background Debug Module (S12XBDMV2) 5.3.2.4 BDM Global Page Index Register (BDMGPR) Register Global Address 0x7FFF08 BGAE BGP6 BGP5 BGP4 BGP3 BGP2 BGP1 BGP0 Reset Figure 5-6. BDM Global Page Register (BDMGPR) Read: All modes through BDM operation when not secured Write: All modes through BDM operation when not secured Table 5-5.
Page 178 Background Debug Module (S12XBDMV2) 5.4.1 Security If the user resets into special single chip mode with the system secured, a secured mode BDM ﬁrmware lookup table is brought into the map overlapping a portion of the standard BDM ﬁrmware lookup table. The secure BDM ﬁrmware veriﬁes that the on-chip non-volatile memory (e.g.
Page 179 Background Debug Module (S12XBDMV2) 5.4.3 BDM Hardware Commands Hardware commands are used to read and write target system memory locations and to enter active background debug mode. Target system memory includes all memory that is accessible by the CPU on the SOC which can be on-chip RAM, non-volatile memory (e.g.
Page 180 Background Debug Module (S12XBDMV2) Table 5-6. Hardware Commands (continued) Opcode Command Data Description (hex) WRITE_WORD 16-bit address Write to memory with standard BDM ﬁrmware lookup table out of map. 16-bit data in Must be aligned access. NOTE: If enabled, ACK will occur when data is ready for transmission for all BDM READ commands and will occur after the write is complete for all BDM WRITE commands.
Page 181 Background Debug Module (S12XBDMV2) Table 5-7. Firmware Commands Opcode Command Data Description (hex) READ_NEXT 16-bit data out Increment X index register by 2 (X = X + 2), then read word X points to. READ_PC 16-bit data out Read program counter. READ_D 16-bit data out Read D accumulator.
Page 182 Background Debug Module (S12XBDMV2) 16-bit misaligned reads and writes are generally not allowed. If attempted by BDM hardware command, the BDM will ignore the least signiﬁcant bit of the address and will assume an even address from the remaining bits. For devices with external bus: The following cycle count information is only valid when the external wait function is not used (see wait bit of EBI sub-block).
Page 183 Background Debug Module (S12XBDMV2) 8 Bits 16 Bits 150-BC 16 Bits AT ~16 TC/Bit AT ~16 TC/Bit Delay AT ~16 TC/Bit Hardware Next Command Address Data Command Read 150-BC Delay Hardware Next Command Address Data Command Write 48-BC DELAY Firmware Next Command Data...
Page 184 Background Debug Module (S12XBDMV2) cycle to recognize this edge. The target measures delays from this perceived start of the bit time while the host measures delays from the point it actually drove BKGD low to start the bit up to one target clock cycle earlier.
Page 185 Background Debug Module (S12XBDMV2) BDM Clock (Target MCU) Host Drive to High-Impedance BKGD Pin Target System Speedup Pulse High-Impedance High-Impedance Perceived Start of Bit Time R-C Rise BKGD Pin 10 Cycles 10 Cycles Earliest Start of Next Bit Host Samples BKGD Pin Figure 5-9.
Page 186 Background Debug Module (S12XBDMV2) Figure 5-10 shows the host receiving a logic 0 from the target. Since the host is asynchronous to the target, there is up to a one clock-cycle delay from the host-generated falling edge on BKGD to the start of the bit time as perceived by the target.
Page 187 Background Debug Module (S12XBDMV2) compared to the serial communication rate. This protocol allows a great ﬂexibility for the POD designers, since it does not rely on any accurate time measurement or short response time to any event in the serial communication.
Page 188 Background Debug Module (S12XBDMV2) Differently from the normal bit transfer (where the host initiates the transmission), the serial interface ACK handshake pulse is initiated by the target MCU by issuing a negative edge in the BKGD pin. The hardware handshake protocol in Figure 5-11 speciﬁes the timing when the BKGD pin is being driven, so the host should follow this timing constraint in order to avoid the risk of an electrical conﬂict in the BKGD pin.
Page 189 Background Debug Module (S12XBDMV2) GO_UNTIL command can not be aborted. Only the corresponding ACK pulse can be aborted by the SYNC command. Although it is not recommended, the host could abort a pending BDM command by issuing a low pulse in the BKGD pin shorter than 128 serial clock cycles, which will not be interpreted as the SYNC command.
Page 190 Background Debug Module (S12XBDMV2) Consider that the target CPU is executing a pending BDM command at the exact moment the POD is being connected to the BKGD pin. In this case, an ACK pulse is issued along with the SYNC command. In this case, there is an electrical conﬂict between the ACK speedup pulse and the SYNC pulse.
Page 191 Background Debug Module (S12XBDMV2) The ACK_ENABLE sends an ACK pulse when the command has been completed. This feature could be used by the host to evaluate if the target supports the hardware handshake protocol. If an ACK pulse is issued in response to this command, the host knows that the target supports the hardware handshake protocol.
Page 192 Background Debug Module (S12XBDMV2) within a few percent of the actual target speed and the communication protocol can easily tolerate speed errors of several percent. As soon as the SYNC request is detected by the target, any partially received command or bit retrieved is discarded.
Page 193 Background Debug Module (S12XBDMV2) after a system stop mode the handshake feature must be enabled again by sending the ACK_ENABLE command. 5.4.11 Serial Communication Time Out The host initiates a host-to-target serial transmission by generating a falling edge on the BKGD pin. If BKGD is kept low for more than 128 target clock cycles, the target understands that a SYNC command was issued.
Page 194 Background Debug Module (S12XBDMV2) S12XS Family Reference Manual, Rev. 1.13 Freescale Semiconductor...
Page 195: Chapter 6 S12X Debug (S12Xdbgv3) Module
Chapter 6 S12X Debug (S12XDBGV3) Module Table 6-1. Revision History Revision Sections Revision Date Description of Changes Number Affected V03.20 14 Sep 2007 6.3.2.7/6-205 - Clariﬁed reserved State Sequencer encodings. 6.4.2.2/6-218 - Added single databyte comparison limitation information V03.21 23 Oct 2007 6.4.2.4/6-219 - Added statement about interrupt vector fetches whilst tagging.
Page 196 S12X Debug (S12XDBGV3) Module Table 6-2. Glossary Of Terms (continued) Term Deﬁnition Data Line 64-bit data entity CPU12X module Tags can be attached to CPU opcodes as they enter the instruction pipe. If the tagged opcode reaches the execution stage a tag hit occurs. 6.1.2 Overview The comparators monitor the bus activity of the CPU12X.
Page 197 S12X Debug (S12XDBGV3) Module — Normal: change of ﬂow (COF) PC information is stored (see Section 6.4.5.2.1) for change of ﬂow deﬁnition. — Loop1: same as Normal but inhibits consecutive duplicate source address entries — Detail: address and data for all cycles except free cycles and opcode fetches are stored —...
Page 198 S12X Debug (S12XDBGV3) Module 6.1.5 Block Diagram TAGS TAGHITS BREAKPOINT REQUESTS S12XCPU SECURE MATCH0 TRIGGER COMPARATOR A TAG & S12XCPU BUS TRIGGER MATCH1 CONTROL STATE COMPARATOR B LOGIC STATE SEQUENCER MATCH2 STATE COMPARATOR C MATCH3 COMPARATOR D TRACE CONTROL TRIGGER TRACE BUFFER READ TRACE DATA (DBG READ DATA BUS) Figure 6-1.
Page 199 S12X Debug (S12XDBGV3) Module Address Name Bit 7 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0x0024 DBGTBH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0025...
Page 200 S12X Debug (S12XDBGV3) Module 6.3.2.1 Debug Control Register 1 (DBGC1) Address: 0x0020 reserved reserved COMRV DBGBRK TRIG Reset Figure 6-3. Debug Control Register (DBGC1) Read: Anytime Write: Bits 7, 1, 0 anytime Bit 6 can be written anytime but always reads back as 0. Bits 5:2 anytime S12XDBG is not armed.
Page 201 S12X Debug (S12XDBGV3) Module Table 6-4. DBGC1 Field Descriptions (continued) Field Description S12XDBG Breakpoint Enable Bit — The DBGBRK bit controls whether the debugger will request a breakpoint DBGBRK to S12XCPU upon reaching the state sequencer Final State. If tracing is enabled, the breakpoint is generated on completion of the tracing session.
Page 202 S12X Debug (S12XDBGV3) Module Table 6-7. SSF[2:0] — State Sequence Flag Bit Encoding SSF[2:0] Current State State0 (disarmed) State1 State2 State3 Final State 101,110,111 Reserved 6.3.2.3 Debug Trace Control Register (DBGTCR) Address: 0x0022 reserved TSOURCE TRANGE TRCMOD TALIGN Reset Figure 6-5. Debug Trace Control Register (DBGTCR) Read: Anytime Write: Bits 7:6 only when S12XDBG is neither secure nor armed.
Page 203 S12X Debug (S12XDBGV3) Module Table 6-9. TRANGE Trace Range Encoding TRANGE Tracing Range Trace from all addresses (No ﬁlter) Trace only in address range from $00000 to Comparator D Trace only in address range from Comparator C to $7FFFFF Trace only in range from Comparator C to Comparator D Table 6-10.
Page 204 S12X Debug (S12XDBGV3) Module Table 6-13. CDCM Encoding CDCM Description Match2 mapped to comparator C match..Match3 mapped to comparator D match. Match2 mapped to comparator C/D inside range..Match3 disabled. Match2 mapped to comparator C/D outside range..Match3 disabled. Reserved 1.
Page 205 S12X Debug (S12XDBGV3) Module 6.3.2.6 Debug Count Register (DBGCNT) Address: 0x0026 Reset — — — — — — — = Unimplemented or Reserved Figure 6-8. Debug Count Register (DBGCNT) Read: Anytime Write: Never Table 6-16. DBGCNT Field Descriptions Field Description 6–0 Count Value —...
Page 206 S12X Debug (S12XDBGV3) Module next state for the state sequencer following a match. The three debug state control registers are located at the same address in the register address map (0x0027). Each register can be accessed using the COMRV bits in DBGC1 to blend in the required register. The COMRV = 11 value blends in the match ﬂag register (DBGMFR).
Page 207 S12X Debug (S12XDBGV3) Module Table 6-20. State1 Sequencer Next State Selection (continued) SC[3:0] Description 0111 Match1 triggers to State3..Match0 triggers Final State..Other matches have no effect 1000 Match0 triggers to State2..Match2 triggers to State3..Other matches have no effect 1001 Match2 triggers to State3..
Page 208 S12X Debug (S12XDBGV3) Module Table 6-22. State2 —Sequencer Next State Selection (continued) SC[3:0] Description 0101 Match3 triggers to Final State..Other matches have no effect 0110 Match0 triggers to State1..Match1 triggers to State3..Other matches have no effect 0111 Match1 triggers to State3..
Page 209 S12X Debug (S12XDBGV3) Module Table 6-24. State3 — Sequencer Next State Selection SC[3:0] Description 0010 Any match triggers to Final State 0011 Match0 triggers to State1..Other matches have no effect 0100 Match0 triggers to State2..Other matches have no effect 0101 Match0 triggers to Final State..Match1 triggers to State1...Other matches have no effect 0110...
Page 210 S12X Debug (S12XDBGV3) Module Comparators B and D consist of four register bytes (three address bus compare registers and a control register). Each set of comparator registers is accessible in the same 8-byte window of the register address map and can be accessed using the COMRV bits in the DBGC1 register.
Page 211 S12X Debug (S12XDBGV3) Module unimplemented bus, thus preventing proper operation. The DBGC1_COMRV bits determine which comparator control, address, data and datamask registers are visible in the 8-byte window from 0x0028 to 0x002F as shown in Section Table 6-26. Table 6-26. Comparator Address Register Visibility COMRV Visible Comparator DBGACTL, DBGAAH ,DBGAAM, DBGAAL, DBGADH, DBGADL, DBGADHM, DBGADLM...
Page 212 S12X Debug (S12XDBGV3) Module Table 6-27. DBGXCTL Field Descriptions (continued) Field Description Determines if comparator is enabled COMPE 0 The comparator is not enabled 1 The comparator is enabled for state sequence triggers or tag generation Table 6-28 shows the effect for RWE and RW on the comparison conditions. These bits are not useful for tagged operations since the trigger occurs based on the tagged opcode reaching the execution stage of the instruction queue.
Page 213 S12X Debug (S12XDBGV3) Module 6.3.2.8.3 Debug Comparator Address Mid Register (DBGXAM) Address: 0x002A Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Reset Figure 6-16. Debug Comparator Address Mid Register (DBGXAM) Read: Anytime. See Table 6-26 for visible register encoding.
Page 214 S12X Debug (S12XDBGV3) Module 6.3.2.8.5 Debug Comparator Data High Register (DBGXDH) Address: 0x002C Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Reset Figure 6-18. Debug Comparator Data High Register (DBGXDH) Read: Anytime. See Table 6-26 for visible register encoding.
Page 215 S12X Debug (S12XDBGV3) Module 6.3.2.8.7 Debug Comparator Data High Mask Register (DBGXDHM) Address: 0x002E Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Reset Figure 6-20. Debug Comparator Data High Mask Register (DBGXDHM) Read: Anytime.
Page 216 S12X Debug (S12XDBGV3) Module 6.4.1 S12XDBG Operation Arming the S12XDBG module by setting ARM in DBGC1 allows triggering, and storing of data in the trace buffer and can be used to cause breakpoints to the CPU12X . The DBG module is made up of four main blocks, the comparators, control logic, the state sequencer, and the trace buffer.
Page 217 S12X Debug (S12XDBGV3) Module when the opcode is fetched from the memory. This precedes the instruction execution by an indeﬁnite number of cycles due to instruction pipe lining. For a comparator match of an opcode at an odd address when TAG = 0, the corresponding even address must be contained in the comparator register. Thus for an opcode at odd address (n), the comparator register must contain address (n–1).
Page 218 S12X Debug (S12XDBGV3) Module NOTE Using this configuration, a byte access of ADDR[n] can cause a comparator match if the databus low byte by chance contains the same value as ADDR[n+1] because the databus comparator does not feature access size comparison and uses the mask as a “don’t care” function. Thus masked bits do not prevent a match. Comparators A and C feature an NDB control bit to determine if a match occurs when the data bus differs to comparator register contents or when the data bus is equivalent to the comparator register contents.
Page 219 S12X Debug (S12XDBGV3) Module Table 6-38. NDB and MASK bit dependency DBGxDHM[n] / Comment DBGxDLM[n] Do not compare data bus bit. Compare data bus bit. Match on equivalence. Do not compare data bus bit. Compare data bus bit. Match on difference. 6.4.2.4 Range Comparisons When using the AB comparator pair for a range comparison, the data bus can also be used for qualiﬁcation...
Page 220 S12X Debug (S12XDBGV3) Module 6.4.3 Trigger Modes Trigger modes are used as qualiﬁers for a state sequencer change of state. The control logic determines the trigger mode and provides a trigger to the state sequencer. The individual trigger modes are described in the following sections.
Page 221 S12X Debug (S12XDBGV3) Module Table 6-39. Trigger Priorities Highest TRIG Trigger immediately to ﬁnal state (begin or mid aligned tracing enabled) Trigger immediately to state 0 (end aligned or no tracing enabled) Match0 (force or tag hit) Trigger to next state as deﬁned by state control registers Match1 (force or tag hit) Trigger to next state as deﬁned by state control registers Match2 (force or tag hit)
Page 222 S12X Debug (S12XDBGV3) Module 6.4.4.1 Final State On entering Final State a trigger may be issued to the trace buffer according to the trace position control as deﬁned by the TALIGN ﬁeld (see Section 6.3.2.3). If TSOURCE in the trace control register DBGTCR is cleared then the trace buffer is disabled and the transition to Final State can only generate a breakpoint request.
Page 223 S12X Debug (S12XDBGV3) Module be executed then the trace is continued for another 32 lines. Upon tracing completion the breakpoint is generated, thus the breakpoint does not occur at the tagged instruction boundary. 6.4.5.1.3 Storing with End-Trigger Storing with End-Trigger, data is stored in the Trace Buffer until the Final State is entered, at which point the S12XDBG module will become disarmed and no more data will be stored.
Page 224 S12X Debug (S12XDBGV3) Module SUB_1 ; JMP Destination address TRACE BUFFER ENTRY 1 ; RTI Destination address TRACE BUFFER ENTRY 3 ADDR1 DBNE A,PART5 ; Source address TRACE BUFFER ENTRY 4 IRQ_ISR LDAB #$F0 ; IRQ Vector $FFF2 = TRACE BUFFER ENTRY 2 STAB VAR_C1 The execution ﬂow taking into account the IRQ is as follows...
Page 225 S12X Debug (S12XDBGV3) Module 6.4.5.3 Trace Buffer Organization Referring to Table 6-40. ADRH, ADRM, ADRL denote address high, middle and low byte respectively. INF bytes contain control information (R/W, S/D etc.). The numerical sufﬁx indicates which tracing step. The information format for Loop1 Mode and PurePC Mode is the same as that of Normal Mode. Whilst tracing in Normal or Loop1 modes each array line contains 2 data entries, thus in this case the DBGCNT[0] is incremented after each separate entry.
Page 226 S12X Debug (S12XDBGV3) Module 6.4.5.3.1 Information Byte Organization The format of the control information byte is dependent upon the active trace mode as described below. In Normal, Loop1, or Pure PC modes tracing of CPU12X activity, CINF is used to store control information.
Page 227 S12X Debug (S12XDBGV3) Module Table 6-42. CXINF Field Descriptions (continued) Field Description Read Write Indicator — This bit indicates if the corresponding stored address corresponds to a read or write access. This bit only contains valid information when tracing CPU12X activity in Detail Mode. 0 Write Access 1 Read Access 6.4.5.4...
Page 228 S12X Debug (S12XDBGV3) Module 6.4.6 Tagging A tag follows program information as it advances through the instruction queue. When a tagged instruction reaches the head of the queue a tag hit occurs and triggers the state sequencer. Each comparator control register features a TAG bit, which controls whether the comparator match will cause a trigger immediately or tag the opcode at the matched address.
Page 229 S12X Debug (S12XDBGV3) Module Table 6-43. Breakpoint Setup TALIGN DBGBRK Breakpoint Alignment Fill Trace Buffer until trigger (no breakpoints — keep running) Fill Trace Buffer until trigger, then breakpoint request occurs Start Trace Buffer at trigger (no breakpoints — keep running) Start Trace Buffer at trigger A breakpoint request occurs when Trace Buffer is full Store a further 32 Trace Buffer line entries after trigger...
Page 230 S12X Debug (S12XDBGV3) Module Table 6-44. Breakpoint Mapping Summary Breakpoint to SWI Breakpoint to BDM No Breakpoint BDM cannot be entered from a breakpoint unless the ENABLE bit is set in the BDM. If entry to BDM via a BGND instruction is attempted and the ENABLE bit in the BDM is cleared, the CPU12X actually executes the BDM ﬁrmware code.
Page 231: Chapter 7 Security (S12Xs9Secv2)
Chapter 7 Security (S12XS9SECV2) Table 7-1. Revision History Version Revision Effective Author Description of Changes Number Date Date 02.00 27 Aug 08 Sep reviewed and updated for S12XD architecture 2004 2004 02.01 21 Feb 21 Feb added S12XE, S12XF and S12XS architectures 2007 2007 02.02...
Page 232 Security (S12XS9SECV2) Table 7-2. Feature Availability in Unsecure and Secure Modes on S12XS Unsecure Mode Secure Mode ✔ ✔ ✔ ✔ EEPROM Array Access ✔ ✔ ✔ ✔ NVM Commands ✔ ✔ ✔ — ✔ ✔ DBG Module Trace — —...
Page 233 Security (S12XS9SECV2) SEC[1:0] = ‘10’. All other combinations put the device in a secured mode. The recommended value to put the device in secured state is the inverse of the unsecured state, i.e. SEC[1:0] = ‘01’. Table 7-4. Security Bits SEC[1:0] Security State 1 (secured)
Page 234 Security (S12XS9SECV2) 7.1.4.1 Normal Single Chip Mode (NS) • Background debug module (BDM) operation is completely disabled. • Execution of Flash and EEPROM commands is restricted. Please refer to the NVM block guide for details. • Tracing code execution using the DBG module is disabled. 7.1.4.2 Special Single Chip Mode (SS) •...
Page 235 Security (S12XS9SECV2) 7.1.5 Unsecuring the Microcontroller Unsecuring the microcontroller can be done by three different methods: 1. Backdoor key access 2. Reprogramming the security bits 3. Complete memory erase (special modes) 7.1.5.1 Unsecuring the MCU Using the Backdoor Key Access In normal modes (single chip and expanded), security can be temporarily disabled using the backdoor key access method.
Page 236 Security (S12XS9SECV2) 7.1.7 Complete Memory Erase (Special Modes) The microcontroller can be unsecured in special modes by erasing the entire EEPROM and Flash memory contents. When a secure microcontroller is reset into special single chip mode (SS), the BDM ﬁrmware veriﬁes whether the EEPROM and Flash memory are erased.
Page 237: Chapter 8 S12Xe Clocks And Reset Generator (S12Xecrgv1)
Chapter 8 S12XE Clocks and Reset Generator (S12XECRGV1) Table 8-1. Revision History Revision Revision Sections Description of Changes Number Date Affected V01.00 26 Oct. 2005 Initial release V01.01 02 Nov 2006 8.4.1.1/8-254 Table “Examples of IPLL Divider settings”: corrected $32 to $31 8.4.1.4/8-257 V01.02 4 Mar.
Page 238 S12XE Clocks and Reset Generator (S12XECRGV1) • System Reset generation from the following possible sources: — Power on reset — Low voltage reset — Illegal address reset — COP reset — Loss of clock reset — External pin reset • Real-Time Interrupt (RTI) 8.1.2 Modes of Operation...
Page 239 S12XE Clocks and Reset Generator (S12XECRGV1) Illegal Address Reset S12X_MMC Power on Reset Voltage Regulator Low Voltage Reset ICRG RESET System Reset Reset Generator CM Fail Clock Monitor XCLKS OSCCLK Clock Quality Checker EXTAL Bus Clock Oscillator XTAL Core Clock Oscillator Clock Registers PLLCLK...
Page 240 S12XE Clocks and Reset Generator (S12XECRGV1) Memory Map and Registers This section provides a detailed description of all registers accessible in the S12XECRG. 8.3.1 Module Memory Map Figure 8-2 gives an overview on all S12XECRG registers. Address Name Bit 7 Bit 0 0x0000 SYNR...
Page 241 S12XE Clocks and Reset Generator (S12XECRGV1) 8.3.2 Register Descriptions This section describes in address order all the S12XECRG registers and their individual bits. 8.3.2.1 S12XECRG Synthesizer Register (SYNR) The SYNR register controls the multiplication factor of the IPLL and selects the VCO frequency range. Module Base + 0x0000 VCOFRQ[1:0] SYNDIV[5:0]...
Page 242 S12XE Clocks and Reset Generator (S12XECRGV1) 8.3.2.2 S12XECRG Reference Divider Register (REFDV) The REFDV register provides a ﬁner granularity for the IPLL multiplier steps. Module Base + 0x0001 REFFRQ[1:0] REFDIV[5:0] Reset Figure 8-4. S12XECRG Reference Divider Register (REFDV) Read: Anytime Write: Anytime except when PLLSEL = 1 NOTE Write to this register initializes the lock detector bit.
Page 243 S12XE Clocks and Reset Generator (S12XECRGV1) Module Base + 0x0002 POSTDIV[4:0] Reset = Unimplemented or Reserved Figure 8-5. S12XECRG Post Divider Register (POSTDIV) Read: Anytime Write: Anytime except if PLLSEL = 1 f VCO f PLL ------------------------------------- - 2xPOSTDIV NOTE If POSTDIV = $00 then f is identical to f (divide by one).
Page 244 S12XE Clocks and Reset Generator (S12XECRGV1) Table 8-4. CRGFLG Field Descriptions Field Description Real Time Interrupt Flag — RTIF is set to 1 at the end of the RTI period. This ﬂag can only be cleared by writing RTIF a 1. Writing a 0 has no effect. If enabled (RTIE=1), RTIF causes an interrupt request. 0 RTI time-out has not yet occurred.
Page 245 S12XE Clocks and Reset Generator (S12XECRGV1) Read: Anytime Write: Anytime Table 8-5. CRGINT Field Descriptions Field Description Real Time Interrupt Enable Bit RTIE 0 Interrupt requests from RTI are disabled. 1 Interrupt will be requested whenever RTIF is set. Lock Interrupt Enable Bit LOCKIE 0 LOCK interrupt requests are disabled.
Page 246 S12XE Clocks and Reset Generator (S12XECRGV1) Table 8-6. CLKSEL Field Descriptions Field Description PLL Select Bit PLLSEL Write: Anytime. Writing a one when LOCK=0 has no effect. This prevents the selection of an unstable PLLCLK as SYSCLK. PLLSEL bit is cleared when the MCU enters Self Clock Mode, Stop Mode or Wait Mode with PLLWAI bit set. It is recommended to read back the PLLSEL bit to make sure PLLCLK has really been selected as SYSCLK, as LOCK status bit could theoretically change at the very moment writing the PLLSEL bit.
Page 247 S12XE Clocks and Reset Generator (S12XECRGV1) Read: Anytime Write: Refer to each bit for individual write conditions Table 8-7. PLLCTL Field Descriptions Field Description Clock Monitor Enable Bit — CME enables the clock monitor. Write anytime except when SCM = 1. 0 Clock monitor is disabled.
Page 248 S12XE Clocks and Reset Generator (S12XECRGV1) Table 8-8. FM Amplitude selection FM Amplitude / Variation FM off ±1% ±2% ±4% 8.3.2.8 S12XECRG RTI Control Register (RTICTL) This register selects the timeout period for the Real Time Interrupt. Module Base + 0x0007 RTDEC RTR6 RTR5...
Page 249 S12XE Clocks and Reset Generator (S12XECRGV1) Table 8-10. RTI Frequency Divide Rates for RTDEC = 0 RTR[6:4] = RTR[3:0] (OFF) 0001 (÷2) 0010 (÷3) 0011 (÷4) 0100 (÷5) 0101 (÷6) 0110 (÷7) 0111 (÷8) 1000 (÷9) 10x2 10x2 10x2 10x2 10x2 10x2 10x2...
Page 250 S12XE Clocks and Reset Generator (S12XECRGV1) Table 8-11. RTI Frequency Divide Rates for RTDEC=1 RTR[6:4] = RTR[3:0] (1x10 (2x10 (5x10 (10x10 (20x10 (50x10 (100x10 (200x10 7x10 14x10 35x10 70x10 140x10 350x10 700x10 1.4x10 0110 (÷7) 8x10 16x10 40x10 80x10 160x10 400x10 800x10 1.6x10...
Page 251 S12XE Clocks and Reset Generator (S12XECRGV1) The COP time-out period is restarted if one these two conditions is true: 1. Writing a non zero value to CR[2:0] (anytime in special modes, once in all other modes) with WRTMASK = 0. 2.
Page 252 S12XE Clocks and Reset Generator (S12XECRGV1) Table 8-13. COP Watchdog Rates OSCCLK Cycles to Timeout 1. OSCCLK cycles are referenced from the previous COP time-out reset (writing $55/$AA to the ARMCOP register) 8.3.2.10 Reserved Register (FORBYP) NOTE This reserved register is designed for factory test purposes only, and is not intended for general user access.
Page 253 S12XE Clocks and Reset Generator (S12XECRGV1) Write: Only in special modes 8.3.2.12 S12XECRG COP Timer Arm/Reset Register (ARMCOP) This register is used to restart the COP time-out period. Module Base + 0x000B Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1...
Page 254 S12XE Clocks and Reset Generator (S12XECRGV1) Functional Description 8.4.1 Functional Blocks 8.4.1.1 Phase Locked Loop with Internal Filter (IPLL) The IPLL is used to run the MCU from a different time base than the incoming OSCCLK. Figure 8-15 shows a block diagram of the IPLL. REFCLK LOCK LOCK...
Page 255 S12XE Clocks and Reset Generator (S12XECRGV1) Table 8-14. Examples of IPLL Divider Settings REFDIV[5:0] REFFRQ[1:0] SYNDIV[5:0] VCOFRQ[1:0] POSTDIV[4:0] 4MHz 2MHz 100MHz 100MHz 50 MHz 8MHz 2MHz 100MHz 100MHz 50 MHz 4MHz 4MHz 80MHz 80MHz 40MHz 8MHz 8MHz 80MHz 80MHz 40MHz 4MHz 4MHz 32MHz...
Page 256 S12XE Clocks and Reset Generator (S12XECRGV1) 8.4.1.2 System Clocks Generator PLLSEL or SCM STOP PLLCLK PHASE SYSCLK LOCK Core Clock LOOP (IIPLL) ÷2 CLOCK PHASE Bus Clock GENERATOR WAIT(RTIWAI), STOP(PSTP, PRE), EXTAL RTI ENABLE OSCCLK OSCILLATOR WAIT(COPWAI), STOP(PSTP, PCE), XTAL COP ENABLE Clock Monitor...
Page 257 S12XE Clocks and Reset Generator (S12XECRGV1) 8.4.1.3 Clock Monitor (CM) If no OSCCLK edges are detected within a certain time, the clock monitor within the oscillator block generates a clock monitor fail event. The S12XECRG then asserts self clock mode or generates a system reset depending on the state of SCME bit.
Page 258 S12XE Clocks and Reset Generator (S12XECRGV1) The Sequence for clock quality check is shown in Figure 8-18. CM FAIL CLOCK OK EXIT FULL STOP SCME=1 & FSTWKP = 0 NUM = 0 ENTER SCM FSTWKP=1 CLOCK MONITOR RESET ENTER SCM NUM = 0 NUM = 50 ACTIVE?
Page 259 S12XE Clocks and Reset Generator (S12XECRGV1) 8.4.1.5 Computer Operating Properly Watchdog (COP) The COP (free running watchdog timer) enables the user to check that a program is running and sequencing properly. When the COP is being used, software is responsible for keeping the COP from timing out.
Page 260 S12XE Clocks and Reset Generator (S12XECRGV1) NOTE In order to detect a potential clock loss the CME bit should always be enabled (CME = 1). If CME bit is disabled and the MCU is conﬁgured to run on PLLCLK, a loss of external clock (OSCCLK) will not be detected and will cause the system clock to drift towards lower frequencies.
Page 261 S12XE Clocks and Reset Generator (S12XECRGV1) 8.4.3.3 Stop Mode All clocks are stopped in STOP mode, dependent of the setting of the PCE, PRE and PSTP bit. The oscillator is disabled in STOP mode unless the PSTP bit is set. If the PRE or PCE bits are set, the RTI or COP continues to run in Pseudo Stop Mode.
Page 262 S12XE Clocks and Reset Generator (S12XECRGV1) CPU resumes program execution immediately Instruction STOP STOP STOP IRQ service IRQ service FSTWKP=1 SCME=1 IRQ service Interrupt Interrupt Interrupt Power Saving Oscillator Clock Oscillator Disabled PLL Clock Core Clock Self-Clock Mode Figure 8-19. Fast Wake-up from Full Stop Mode: Example 1 Frequent Uncritical Frequent Critical CPU resumes program execution immediately...
Page 263 S12XE Clocks and Reset Generator (S12XECRGV1) Table 8-16. Reset Summary Reset Source Local Enable COP Watchdog Reset COPCTL (CR[2:0] nonzero) 8.5.1 Description of Reset Operation The reset sequence is initiated by any of the following events: • Low level is detected at the RESET pin (External Reset). •...
Page 264 S12XE Clocks and Reset Generator (S12XECRGV1) The internal reset of the MCU remains asserted while the reset generator completes the 192 SYSCLK long reset sequence. In case the RESET pin is externally driven low for more than these 192 SYSCLK cycles (External Reset), the internal reset remains asserted longer.
Page 265 S12XE Clocks and Reset Generator (S12XECRGV1) S12XECRG performs a quality check on the incoming clock signal. As soon as clock quality check indicates a valid Oscillator Clock signal the reset sequence starts using the Oscillator clock. If after 50 check windows the clock quality check indicated a non-valid Oscillator Clock the reset sequence starts using Self-Clock Mode.
Page 266 S12XE Clocks and Reset Generator (S12XECRGV1) 8.6.1 Description of Interrupt Operation 8.6.1.1 Real Time Interrupt The S12XECRG generates a real time interrupt when the selected interrupt time period elapses. RTI interrupts are locally disabled by setting the RTIE bit to zero. The real time interrupt ﬂag (RTIF) is set to1 when a timeout occurs, and is cleared to 0 by writing a 1 to the RTIF bit.
Page 267: Chapter 9 Pierce Oscillator (S12Xosclcpv2)
Chapter 9 Pierce Oscillator (S12XOSCLCPV2) Table 9-1. Revision History Revision Revision Sections Description of Changes Number Date Affected V01.05 19 Jul 2006 - All xclks info was removed V02.00 04 Aug 2006 - Incremented revision to match the design system spec revision Introduction The Pierce oscillator (XOSC) module provides a robust, low-noise and low-power clock source.
Page 268 Pierce Oscillator (S12XOSCLCPV2) 9.1.3 Block Diagram Figure 9-1 shows a block diagram of the XOSC. Monitor_Failure Clock Monitor OSCCLK Peak Gain Control Detector = 1.8 V DDPLL XTAL EXTAL Figure 9-1. XOSC Block Diagram External Signal Description This section lists and describes the signals that connect off chip 9.2.1 VDDPLL and VSSPLL —...
Page 269 Pierce Oscillator (S12XOSCLCPV2) from the EXTAL input frequency. In full stop mode (PSTP = 0), the EXTAL pin is pulled down by an internal resistor of typical 200 kΩ. NOTE Freescale recommends an evaluation of the application board and chosen resonator or crystal by the resonator or crystal supplier.
Page 270 Pierce Oscillator (S12XOSCLCPV2) Memory Map and Register Deﬁnition The CRG contains the registers and associated bits for controlling and monitoring the oscillator module. Functional Description The XOSC module has control circuitry to maintain the crystal oscillator circuit voltage level to an optimal level which is determined by the amount of hysteresis being used and the maximum oscillation range.
Page 271: Chapter 10 Analog-To-Digital Converter (Adc12B16Cv1)
Chapter 10 Analog-to-Digital Converter (ADC12B16CV1) Table 10-1. Revision History Revision Sections Revision Date Description of Changes Number Affected V01.00 13 Oct. 2005 Initial version V01.01 04 Mar. 2008 corrected reference to DJM bit 10.1 Introduction The ADC12B16C is a 16-channel, 12-bit, multiplexed input successive approximation analog-to-digital converter.
Page 272 Analog-to-Digital Converter (ADC12B16CV1) 10.1.2 Modes of Operation 10.1.2.1 Conversion Modes There is software programmable selection between performing single or continuous conversion on a single channel or multiple channels. 10.1.2.2 MCU Operating Modes • Stop Mode — ICLKSTP=0 (in ATDCTL2 register) Entering Stop Mode aborts any conversion sequence in progress and if a sequence was aborted restarts it after exiting stop mode.
Page 273 Analog-to-Digital Converter (ADC12B16CV1) 10.1.3 Block Diagram ICLK Bus Clock Internal Clock ATD_12B16C Clock Prescaler ATD Clock Sequence Complete Trigger ETRIG0 Interrupt ETRIG1 Mode and Compare Interrupt ETRIG2 Timing Control ETRIG3 (See device speciﬁ- cation for availability and connectivity) ATDCTL1 ATDDIEN Results ATD 0 ATD 1...
Page 274 Analog-to-Digital Converter (ADC12B16CV1) 10.1.4 Block Diagram of Input structure ch[4:0] = {SC, CD, CC, CB, CA} bits of ATDCTL5 register channel 23 channel 19 channel Pin 15 Pin 11 Pin 7 Pin 3 ch[1:0]=11 channel 22 ch[4:2] = 101 channel 18 ch[4:2] = 100 Pin 14 ch[4:2] = 011...
Page 275 Analog-to-Digital Converter (ADC12B16CV1) 10.2 Signal Description This section lists all inputs to the ADC12B16C block. 10.2.1 Detailed Signal Descriptions 10.2.1.1 ANx (x = 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) This pin serves as the analog input Channel x. It can also be conﬁgured as digital port or external trigger for the ATD conversion.
Page 276 Analog-to-Digital Converter (ADC12B16CV1) Address Name Bit 7 Bit 0 0x0000 ATDCTL0 Reserved WRAP3 WRAP2 WRAP1 WRAP0 0x0001 ATDCTL1 ETRIGSEL SRES1 SRES0 SMP_DIS ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0 0x0002 ATDCTL2 AFFC ICLKSTP ETRIGLE ETRIGP ETRIGE ASCIE ACMPIE 0x0003 ATDCTL3 FIFO FRZ1 FRZ0 0x0004 ATDCTL4 SMP2...
Page 277 Analog-to-Digital Converter (ADC12B16CV1) Address Name Bit 7 Bit 0 Section 10.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)” 0x001E ATDDR7 Section 10.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)” Section 10.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)” 0x0020 ATDDR8 Section 10.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)” Section 10.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)”...
Page 278 Analog-to-Digital Converter (ADC12B16CV1) Table 10-3. Multi-Channel Wrap Around Coding Multiple Channel Conversions (MULT = 1) WRAP3 WRAP2 WRAP1 WRAP0 Wraparound to AN0 after Converting Reserved AN10 AN11 AN12 AN13 AN14 AN15 If only AN0 should be converted use MULT=0. 10.3.2.2 ATD Control Register 1 (ATDCTL1) Writes to this register will abort current conversion sequence.
Page 279 Analog-to-Digital Converter (ADC12B16CV1) Table 10-4. ATDCTL1 Field Descriptions Field Description External Trigger Source Select — This bit selects the external trigger source to be either one of the AD ETRIGSEL channels or one of the ETRIG3-0 inputs. See device speciﬁcation for availability and connectivity of ETRIG3-0 inputs.
Page 280 Analog-to-Digital Converter (ADC12B16CV1) Table 10-6. External Trigger Channel Select Coding ETRIGSEL ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0 External trigger source is ETRIG2 ETRIG3 Reserved Reserved Only if ETRIG3-0 input option is available (see device speciﬁcation), else ETRISEL is ignored, that means external trigger source is still on one of the AD channels selected by ETRIGCH3-0 10.3.2.3 ATD Control Register 2 (ATDCTL2) Writes to this register will abort current conversion sequence.
Page 281 Analog-to-Digital Converter (ADC12B16CV1) Table 10-7. ATDCTL2 Field Descriptions (continued) Field Description External Trigger Level/Edge Control — This bit controls the sensitivity of the external trigger signal. See ETRIGLE Table 10-8 for details. External Trigger Polarity — This bit controls the polarity of the external trigger signal. See Table 10-8 for details.
Page 282 Analog-to-Digital Converter (ADC12B16CV1) Field Description Result Register Data Justiﬁcation — Result data format is always unsigned. This bit controls justiﬁcation of conversion data in the result registers. 0 Left justiﬁed data in the result registers. 1 Right justiﬁed data in the result registers. Table 10-10 gives examples ATD results for an input signal range between 0 and 5.12 Volts.
Page 283 Analog-to-Digital Converter (ADC12B16CV1) Table 10-10. Examples of ideal decimal ATD Results 12-Bit Input Signal 8-Bit 10-Bit Codes = 0 Volts Codes Codes (transfer curve has = 5.12 Volts (resolution=20mV) (resolution=5mV) 1.25mV offset) (resolution=1.25mV) 5.120 Volts 1023 4095 0.022 0.020 0.018 0.016 0.014 0.012...
Page 284 Analog-to-Digital Converter (ADC12B16CV1) Table 10-12. ATD Behavior in Freeze Mode (Breakpoint) FRZ1 FRZ0 Behavior in Freeze Mode Freeze Immediately 10.3.2.5 ATD Control Register 4 (ATDCTL4) Writes to this register will abort current conversion sequence. Module Base + 0x0004 SMP2 SMP1 SMP0 PRS[4:0] Reset...
Page 285 Analog-to-Digital Converter (ADC12B16CV1) 10.3.2.6 ATD Control Register 5 (ATDCTL5) Writes to this register will abort current conversion sequence and start a new conversion sequence. If external trigger is enabled (ETRIGE=1) an initial write to ATDCTL5 is required to allow starting of a conversion sequence which will then occur on each trigger event.
Page 286 Analog-to-Digital Converter (ADC12B16CV1) Table 10-16. Analog Input Channel Select Coding Analog Input Channel AN10 AN11 AN12 AN13 AN14 AN15 Reserved Reserved Reserved ) / 2 Reserved Reserved 10.3.2.7 ATD Status Register 0 (ATDSTAT0) This register contains the Sequence Complete Flag, overrun ﬂags for external trigger and FIFO mode, and the conversion counter.
Page 287 Analog-to-Digital Converter (ADC12B16CV1) Write: Anytime (No effect on (CC3, CC2, CC1, CC0)) Table 10-17. ATDSTAT0 Field Descriptions Field Description Sequence Complete Flag — This ﬂag is set upon completion of a conversion sequence. If conversion sequences are continuously performed (SCAN=1), the ﬂag is set after each one is completed. This ﬂag is cleared when one of the following occurs: A) Write “1”...
Page 288 Analog-to-Digital Converter (ADC12B16CV1) Module Base + 0x0008 CMPE[15:0] Reset Figure 10-11. ATD Compare Enable Register (ATDCMPE) Table 10-18. ATDCMPE Field Descriptions Field Description 15–0 Compare Enable for Conversion Number n (n= 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) of a Sequence CMPE[15:0] —...
Page 289 Analog-to-Digital Converter (ADC12B16CV1) 10.3.2.9 ATD Status Register 2 (ATDSTAT2) This read-only register contains the Conversion Complete Flags CCF[15:0]. Module Base + 0x000A CCF[15:0] Reset = Unimplemented or Reserved Figure 10-12. ATD Status Register 2 (ATDSTAT2) Read: Anytime Write: Anytime, no effect Table 10-19.
Page 290 Analog-to-Digital Converter (ADC12B16CV1) 10.3.2.10 ATD Input Enable Register (ATDDIEN) Module Base + 0x000C IEN[15:0] Reset Figure 10-13. ATD Input Enable Register (ATDDIEN) Read: Anytime Write: Anytime Table 10-20. ATDDIEN Field Descriptions Field Description 15–0 ATD Digital Input Enable on channel x (x= 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) — This bit controls IEN[15:0] the digital input buffer from the analog input pin (ANx) to the digital data register.
Page 291 Analog-to-Digital Converter (ADC12B16CV1) 10.3.2.12 ATD Conversion Result Registers (ATDDRn) The A/D conversion results are stored in 16 result registers. Results are always in unsigned data representation. Left and right justiﬁcation is selected using the DJM control bit in ATDCTL3. If automatic compare of conversions results is enabled (CMPE[n]=1 in ATDCMPE), these registers must be written with the compare values in left or right justiﬁed format depending on the actual value of the DJM bit.
Page 292 Analog-to-Digital Converter (ADC12B16CV1) Table 10-22. Conversion result mapping to ATDDRn conversion result mapping to ATDDRn resolution 8-bit data Bit[11:4] = result, Bit[3:0]=0000 8-bit data Bit[7:0] = result, Bit[11:8]=0000 10-bit data Bit[11:2] = result, Bit[1:0]=00 10-bit data Bit[9:0] = result, Bit[11:10]=00 12-bit data Bit[11:0] = result 10.4...
Page 293 Analog-to-Digital Converter (ADC12B16CV1) Only analog input signals within the potential range of V to V (A/D reference potentials) will result in a non-railed digital output code. 10.4.2 Digital Sub-Block This subsection explains some of the digital features in more detail. See Section 10.3.2, “Register Descriptions”...
Page 294 Analog-to-Digital Converter (ADC12B16CV1) 10.4.2.2 General-Purpose Digital Port Operation The input channel pins can be multiplexed between analog and digital data. As analog inputs, they are multiplexed and sampled as analog channels to the A/D converter. The analog/digital multiplex operation is performed in the input pads. The input pad is always connected to the analog input channels of the ADC12B16C.
Page 295: Chapter 11 Freescale's Scalable Controller Area Network (S12Mscanv3)
Chapter 11 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 11-1. Revision History Revision Sections Revision Date Description of Changes Number Affected V03.11 31 Mar 2009 • Orthographic corrections V03.12 09 Aug 2010 Table 11-37 • Added ‘Bosch CAN 2.0A/B’ to bit time settings table V03.13 03 Mar 2011 Figure 11-4...
Page 296 Freescale’s Scalable Controller Area Network (S12MSCANV3) 11.1.1 Glossary Table 11-2. Terminology Acknowledge of CAN message Controller Area Network Cyclic Redundancy Code End of Frame FIFO First-In-First-Out Memory Inter-Frame Sequence Start of Frame CPU bus CPU related read/write data bus CAN bus CAN protocol related serial bus oscillator clock Direct clock from external oscillator...
Page 297 Freescale’s Scalable Controller Area Network (S12MSCANV3) 11.1.3 Features The basic features of the MSCAN are as follows: • Implementation of the CAN protocol — Version 2.0A/B — Standard and extended data frames — Zero to eight bytes data length — Programmable bit rate up to 1 Mbps —...
Page 298 Freescale’s Scalable Controller Area Network (S12MSCANV3) 11.2 External Signal Description The MSCAN uses two external pins. NOTE On MCUs with an integrated CAN physical interface (transceiver) the MSCAN interface is connected internally to the transceiver interface. In these cases the external availability of signals TXCAN and RXCAN is optional.
Page 299 Freescale’s Scalable Controller Area Network (S12MSCANV3) 11.3 Memory Map and Register Deﬁnition This section provides a detailed description of all registers accessible in the MSCAN. 11.3.1 Module Memory Map Figure 11-3 gives an overview on all registers and their individual bits in the MSCAN memory map. The register address results from the addition of base address and address offset.
Page 300 Freescale’s Scalable Controller Area Network (S12MSCANV3) Register Bit 7 Bit 0 Name 0x0000 RXACT SYNCH RXFRM CSWAI TIME WUPE SLPRQ INITRQ CANCTL0 0x0001 SLPAK INITAK CANE CLKSRC LOOPB LISTEN BORM WUPM CANCTL1 0x0002 SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 CANBTR0 0x0003...
Page 301 Freescale’s Scalable Controller Area Network (S12MSCANV3) Register Bit 7 Bit 0 Name 0x000F TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 CANTXERR 0x0010–0x0013 CANIDAR0–3 0x0014–0x0017 CANIDMRx 0x0018–0x001B CANIDAR4–7 0x001C–0x001F CANIDMR4–7 0x0020–0x002F Section 11.3.3, “Programmer’s Model of Message Storage” CANRXFG 0x0030–0x003F Section 11.3.3, “Programmer’s Model of Message Storage”...
Page 302 Freescale’s Scalable Controller Area Network (S12MSCANV3) 1. Read: Anytime Write: Anytime when out of initialization mode; exceptions are read-only RXACT and SYNCH, RXFRM (which is set by the module only), and INITRQ (which is also writable in initialization mode) NOTE The CANCTL0 register, except WUPE, INITRQ, and SLPRQ, is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1).
Page 303 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 11-3. CANCTL0 Register Field Descriptions (continued) Field Description Sleep Mode Request — This bit requests the MSCAN to enter sleep mode, which is an internal power saving SLPRQ mode (see Section 11.4.5.5, “MSCAN Sleep Mode”).
Page 304 Freescale’s Scalable Controller Area Network (S12MSCANV3) Module Base + 0x0001 Access: User read/write SLPAK INITAK CANE CLKSRC LOOPB LISTEN BORM WUPM Reset: = Unimplemented Figure 11-5. MSCAN Control Register 1 (CANCTL1) 1. Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1), except CANE which is write once in normal and anytime in special system operation modes when the MSCAN is in initialization mode (INITRQ = 1 and INITAK = 1) Table 11-4.
Page 305 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 11-4. CANCTL1 Register Field Descriptions (continued) Field Description Sleep Mode Acknowledge — This ﬂag indicates whether the MSCAN module has entered sleep mode (see SLPAK Section 11.4.5.5, “MSCAN Sleep Mode”). It is used as a handshake ﬂag for the SLPRQ sleep mode request. Sleep mode is active when SLPRQ = 1 and SLPAK = 1.
Page 306 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 11-7. Baud Rate Prescaler BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 Prescaler value (P) 11.3.2.4 MSCAN Bus Timing Register 1 (CANBTR1) The CANBTR1 register conﬁgures various CAN bus timing parameters of the MSCAN module. Module Base + 0x0003 Access: User read/write SAMP...
Page 307 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 11-9. Time Segment 2 Values TSEG22 TSEG21 TSEG20 Time Segment 2 1 Tq clock cycle 2 Tq clock cycles 7 Tq clock cycles 8 Tq clock cycles 1. This setting is not valid. Please refer to Table 11-37 for valid settings.
Page 308 Freescale’s Scalable Controller Area Network (S12MSCANV3) 1. Read: Anytime Write: Anytime when not in initialization mode, except RSTAT[1:0] and TSTAT[1:0] ﬂags which are read-only; write of 1 clears ﬂag; write of 0 is ignored NOTE The CANRFLG register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1).
Page 309 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 11-11. CANRFLG Register Field Descriptions (continued) Field Description Overrun Interrupt Flag — This ﬂag is set when a data overrun condition occurs. If not masked, an error interrupt OVRIF is pending while this ﬂag is set. No data overrun condition A data overrun detected Receive Buffer Full Flag —...
Page 310 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 11-12. CANRIER Register Field Descriptions Field Description Wake-Up Interrupt Enable WUPIE 0 No interrupt request is generated from this event. 1 A wake-up event causes a Wake-Up interrupt request. CAN Status Change Interrupt Enable CSCIE 0 No interrupt request is generated from this event.
Page 311 Freescale’s Scalable Controller Area Network (S12MSCANV3) Module Base + 0x0006 Access: User read/write TXE2 TXE1 TXE0 Reset: = Unimplemented Figure 11-10. MSCAN Transmitter Flag Register (CANTFLG) 1. Read: Anytime Write: Anytime when not in initialization mode; write of 1 clears ﬂag, write of 0 is ignored NOTE The CANTFLG register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1).
Page 312 Freescale’s Scalable Controller Area Network (S12MSCANV3) 1. Read: Anytime Write: Anytime when not in initialization mode NOTE The CANTIER register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is writable when not in initialization mode (INITRQ = 0 and INITAK = 0).
Page 313 Freescale’s Scalable Controller Area Network (S12MSCANV3) 11.3.2.10 MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK) The CANTAAK register indicates the successful abort of a queued message, if requested by the appropriate bits in the CANTARQ register. Module Base + 0x0009 Access: User read/write ABTAK2 ABTAK1 ABTAK0...
Page 314 Freescale’s Scalable Controller Area Network (S12MSCANV3) NOTE The CANTBSEL register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK=1). This register is writable when not in initialization mode (INITRQ = 0 and INITAK = 0). Table 11-17.
Page 315 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 11-18. CANIDAC Register Field Descriptions Field Description Identiﬁer Acceptance Mode — The CPU sets these ﬂags to deﬁne the identiﬁer acceptance ﬁlter organization IDAM[1:0] (see Section 11.4.3, “Identiﬁer Acceptance Filter”). Table 11-19 summarizes the different settings. In ﬁlter closed mode, no message is accepted such that the foreground buffer is never reloaded.
Page 316 Freescale’s Scalable Controller Area Network (S12MSCANV3) Module Base + 0x000C to Module Base + 0x000D Access: User read/write Reset: = Unimplemented Figure 11-16. MSCAN Reserved Register 1. Read: Always reads zero in normal system operation modes Write: Unimplemented in normal system operation modes NOTE Writing to this register when in special system operating modes can alter the MSCAN functionality.
Page 317 Freescale’s Scalable Controller Area Network (S12MSCANV3) Module Base + 0x000E Access: User read/write RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0 Reset: = Unimplemented Figure 11-18. MSCAN Receive Error Counter (CANRXERR) 1. Read: Only when in sleep mode (SLPRQ = 1 and SLPAK = 1) or initialization mode (INITRQ = 1 and INITAK = 1) Write: Unimplemented NOTE Reading this register when in any other mode other than sleep or...
Page 318 Freescale’s Scalable Controller Area Network (S12MSCANV3) 11.3.2.17 MSCAN Identiﬁer Acceptance Registers (CANIDAR0-7) On reception, each message is written into the background receive buffer. The CPU is only signalled to read the message if it passes the criteria in the identiﬁer acceptance and identiﬁer mask registers (accepted);...
Page 319 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 11-23. CANIDAR4–CANIDAR7 Register Field Descriptions Field Description Acceptance Code Bits — AC[7:0] comprise a user-deﬁned sequence of bits with which the corresponding bits AC[7:0] of the related identiﬁer register (IDRn) of the receive message buffer are compared. The result of this comparison is then masked with the corresponding identiﬁer mask register.
Page 320 Freescale’s Scalable Controller Area Network (S12MSCANV3) 1. Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1) Table 11-25. CANIDMR4–CANIDMR7 Register Field Descriptions Field Description Acceptance Mask Bits — If a particular bit in this register is cleared, this indicates that the corresponding bit in AM[7:0] the identiﬁer acceptance register must be the same as its identiﬁer bit before a match is detected.
Page 321 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 11-26. Message Buffer Organization Offset Register Access Address 0x00X0 Identiﬁer Register 0 0x00X1 Identiﬁer Register 1 0x00X2 Identiﬁer Register 2 0x00X3 Identiﬁer Register 3 0x00X4 Data Segment Register 0 0x00X5 Data Segment Register 1 0x00X6 Data Segment Register 2 0x00X7...
Page 322 Freescale’s Scalable Controller Area Network (S12MSCANV3) Figure 11-24. Receive/Transmit Message Buffer — Extended Identiﬁer Mapping Register Bit 7 Bit0 Name 0x00X0 ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 IDR0 0x00X1 ID20 ID19 ID18 SRR (=1) IDE (=1) ID17 ID16 ID15 IDR1 0x00X2...
Page 323 Freescale’s Scalable Controller Area Network (S12MSCANV3) Figure 11-24. Receive/Transmit Message Buffer — Extended Identiﬁer Mapping (continued) Register Bit 7 Bit0 Name = Unused, always read ‘x’ Read: • For transmit buffers, anytime when TXEx ﬂag is set (see Section 11.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section 11.3.2.11, “MSCAN Transmit Buffer Selection Register...
Page 324 Freescale’s Scalable Controller Area Network (S12MSCANV3) 11.3.3.1.1 IDR0–IDR3 for Extended Identiﬁer Mapping Module Base + 0x00X0 ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 Reset: Figure 11-26. Identiﬁer Register 0 (IDR0) — Extended Identiﬁer Mapping Table 11-27. IDR0 Register Field Descriptions — Extended Field Description Extended Format Identiﬁer —...
Page 325 Freescale’s Scalable Controller Area Network (S12MSCANV3) Module Base + 0x00X2 ID14 ID13 ID12 ID11 ID10 Reset: Figure 11-28. Identiﬁer Register 2 (IDR2) — Extended Identiﬁer Mapping Table 11-29. IDR2 Register Field Descriptions — Extended Field Description Extended Format Identiﬁer — The identiﬁers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the ID[14:7] most signiﬁcant bit and is transmitted ﬁrst on the CAN bus during the arbitration procedure.
Page 326 Freescale’s Scalable Controller Area Network (S12MSCANV3) 11.3.3.1.2 IDR0–IDR3 for Standard Identiﬁer Mapping Module Base + 0x00X0 ID10 Reset: Figure 11-30. Identiﬁer Register 0 — Standard Mapping Table 11-31. IDR0 Register Field Descriptions — Standard Field Description Standard Format Identiﬁer — The identiﬁers consist of 11 bits (ID[10:0]) for the standard format. ID10 is the ID[10:3] most signiﬁcant bit and is transmitted ﬁrst on the CAN bus during the arbitration procedure.
Page 327 Freescale’s Scalable Controller Area Network (S12MSCANV3) Module Base + 0x00X2 Reset: = Unused; always read ‘x’ Figure 11-32. Identiﬁer Register 2 — Standard Mapping Module Base + 0x00X3 Reset: = Unused; always read ‘x’ Figure 11-33. Identiﬁer Register 3 — Standard Mapping 11.3.3.2 Data Segment Registers (DSR0-7) The eight data segment registers, each with bits DB[7:0], contain the data to be transmitted or received.
Page 328 Freescale’s Scalable Controller Area Network (S12MSCANV3) 11.3.3.3 Data Length Register (DLR) This register keeps the data length ﬁeld of the CAN frame. Module Base + 0x00XC DLC3 DLC2 DLC1 DLC0 Reset: = Unused; always read “x” Figure 11-35. Data Length Register (DLR) — Extended Identiﬁer Mapping Table 11-34.
Page 329 Freescale’s Scalable Controller Area Network (S12MSCANV3) • The transmission buffer with the lowest local priority ﬁeld wins the prioritization. In cases of more than one buffer having the same lowest priority, the message buffer with the lower index number wins. Module Base + 0x00XD Access: User read/write PRIO7...
Page 330 Freescale’s Scalable Controller Area Network (S12MSCANV3) Module Base + 0x00XF Access: User read/write TSR7 TSR6 TSR5 TSR4 TSR3 TSR2 TSR1 TSR0 Reset: Figure 11-38. Time Stamp Register — Low Byte (TSRL) 1. Read: Anytime when TXEx ﬂag is set (see Section 11.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see...
Page 331 Freescale’s Scalable Controller Area Network (S12MSCANV3) 11.4 Functional Description 11.4.1 General This section provides a complete functional description of the MSCAN. 11.4.2 Message Storage CAN Receive / Transmit Engine Memory Mapped I/O MSCAN CPU bus Receiver TXE0 PRIO TXE1 CPU bus MSCAN PRIO TXE2...
Page 332 Freescale’s Scalable Controller Area Network (S12MSCANV3) The MSCAN facilitates a sophisticated message storage system which addresses the requirements of a broad range of network applications. 11.4.2.1 Message Transmit Background Modern application layer software is built upon two fundamental assumptions: • Any CAN node is able to send out a stream of scheduled messages without releasing the CAN bus between the two messages.
Page 333 Freescale’s Scalable Controller Area Network (S12MSCANV3) software simpler because only one address area is applicable for the transmit process, and the required address space is minimized. The CPU then stores the identiﬁer, the control bits, and the data content into one of the transmit buffers. Finally, the buffer is ﬂagged as ready for transmission by clearing the associated TXE ﬂag.
Page 334 Freescale’s Scalable Controller Area Network (S12MSCANV3) generates a receive interrupt (see Section 11.4.7.3, “Receive Interrupt”) to the CPU. The user’s receive handler must read the received message from the RxFG and then reset the RXF ﬂag to acknowledge the interrupt and to release the foreground buffer. A new message, which can follow immediately after the IFS ﬁeld of the CAN frame, is received into the next available RxBG.
Page 335 Freescale’s Scalable Controller Area Network (S12MSCANV3) Figure 11-40 shows how the ﬁrst 32-bit ﬁlter bank (CANIDAR0–CANIDAR3, CANIDMR0–CANIDMR3) produces a ﬁlter 0 hit. Similarly, the second ﬁlter bank (CANIDAR4–CANIDAR7, CANIDMR4–CANIDMR7) produces a ﬁlter 1 hit. • Four identiﬁer acceptance ﬁlters, each to be applied to: —...
Page 336 Freescale’s Scalable Controller Area Network (S12MSCANV3) CAN 2.0B ID28 IDR0 ID21 ID20 IDR1 ID15 ID14 IDR2 IDR3 Extended Identiﬁer CAN 2.0A/B ID10 IDR0 IDR1 ID10 IDR2 ID10 IDR3 Standard Identiﬁer CANIDMR0 CANIDMR1 CANIDAR0 CANIDAR1 ID Accepted (Filter 0 Hit) CANIDMR2 CANIDMR3 CANIDAR2 CANIDAR3...
Page 337 Freescale’s Scalable Controller Area Network (S12MSCANV3) CAN 2.0B Extended Identiﬁer ID28 IDR0 ID21 ID20 IDR1 ID15 ID14 IDR2 IDR3 CAN 2.0A/B ID10 IDR0 IDR1 ID10 IDR2 ID10 IDR3 Standard Identiﬁer CIDMR0 CIDAR0 ID Accepted (Filter 0 Hit) CIDMR1 CIDAR1 ID Accepted (Filter 1 Hit) CIDMR2 CIDAR2 ID Accepted (Filter 2 Hit)
Page 338 Freescale’s Scalable Controller Area Network (S12MSCANV3) 11.4.3.1 Protocol Violation Protection The MSCAN protects the user from accidentally violating the CAN protocol through programming errors. The protection logic implements the following features: • The receive and transmit error counters cannot be written or otherwise manipulated. •...
Page 339 Freescale’s Scalable Controller Area Network (S12MSCANV3) For microcontrollers without a clock and reset generator (CRG), CANCLK is driven from the crystal oscillator (oscillator clock). A programmable prescaler generates the time quanta (Tq) clock from CANCLK. A time quantum is the atomic unit of time handled by the MSCAN.
Page 340 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 11-36. Time Segment Syntax Syntax Description System expects transitions to occur on the CAN bus during this SYNC_SEG period. A node in transmit mode transfers a new value to the CAN bus at Transmit Point this point.
Page 341 Freescale’s Scalable Controller Area Network (S12MSCANV3) 11.4.4.2 Special System Operating Modes The MSCAN module behaves as described within this speciﬁcation in all special system operating modes. Write restrictions which exist on speciﬁc registers in normal modes are lifted for test purposes in special modes.
Page 342 Freescale’s Scalable Controller Area Network (S12MSCANV3) Bus Clock Domain CAN Clock Domain INIT INITRQ SYNC sync. Flag INITRQ Init Request INITAK sync. SYNC INITAK Flag INITAK Figure 11-45. Initialization Request/Acknowledge Cycle Due to independent clock domains within the MSCAN, INITRQ must be synchronized to all domains by using a special handshake mechanism.
Page 343 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 11-38. CPU vs. MSCAN Operating Modes MSCAN Mode Reduced Power Consumption CPU Mode Normal Disabled Sleep Power Down (CANE=0) CSWAI = X CSWAI = X CSWAI = X SLPRQ = 1 SLPRQ = X SLPRQ = 0 SLPAK = 1 SLPAK = X...
Page 344 Freescale’s Scalable Controller Area Network (S12MSCANV3) 11.4.5.5 MSCAN Sleep Mode The CPU can request the MSCAN to enter this low power mode by asserting the SLPRQ bit in the CANCTL0 register. The time when the MSCAN enters sleep mode depends on a ﬁxed synchronization delay and its current activity: •...
Page 345 Freescale’s Scalable Controller Area Network (S12MSCANV3) If the WUPE bit in CANCTL0 is not asserted, the MSCAN will mask any activity it detects on CAN. RXCAN is therefore held internally in a recessive state. This locks the MSCAN in sleep mode. WUPE must be set before entering sleep mode to take effect.
Page 346 Freescale’s Scalable Controller Area Network (S12MSCANV3) 11.4.5.7 Disabled Mode The MSCAN is in disabled mode out of reset (CANE=0). All module clocks are stopped for power saving, however the register map can still be accessed as speciﬁed. 11.4.5.8 Programmable Wake-Up Function The MSCAN can be programmed to wake up from sleep or power down mode as soon as CAN bus activity is detected (see control bit WUPE in MSCAN Control Register 0 (CANCTL0).
Page 347 Freescale’s Scalable Controller Area Network (S12MSCANV3) 11.4.7.3 Receive Interrupt A message is successfully received and shifted into the foreground buffer (RxFG) of the receiver FIFO. This interrupt is generated immediately after receiving the EOF symbol. The RXF ﬂag is set. If there are multiple messages in the receiver FIFO, the RXF ﬂag is set as soon as the next message is shifted to the foreground buffer.
Page 348 Freescale’s Scalable Controller Area Network (S12MSCANV3) 11.5 Initialization/Application Information 11.5.1 MSCAN initialization The procedure to initially start up the MSCAN module out of reset is as follows: 1. Assert CANE 2. Write to the conﬁguration registers in initialization mode 3. Clear INITRQ to leave initialization mode If the conﬁguration of registers which are only writable in initialization mode shall be changed: 1.
Page 349: Chapter 12 Periodic Interrupt Timer (S12Pit24B4Cv1)
Chapter 12 Periodic Interrupt Timer (S12PIT24B4CV1) Table 12-1. Revision History Version Revision Effective Author Description of Changes Number Date Date 01.00 28-Apr-05 28-Apr-05 Initial Release 01.01 05-Jul-05 05-Jul-05 Added application section, removed table 1-1 12.1 Introduction The period interrupt timer (PIT) is an array of 24-bit timers that can be used to trigger peripheral modules or raise periodic interrupts.
Page 350 Periodic Interrupt Timer (S12PIT24B4CV1) • Run mode This is the basic mode of operation. • Wait mode PIT operation in wait mode is controlled by the PITSWAI bit located in the PITCFLMT register. In wait mode, if the bus clock is globally enabled and if the PITSWAI bit is clear, the PIT operates like in run mode.
Page 351 Periodic Interrupt Timer (S12PIT24B4CV1) 12.3 Register Deﬁnition This section consists of register descriptions in address order of the PIT. Each description includes a standard register diagram with an associated ﬁgure number. Details of register bit and ﬁeld function follow the register diagrams, in bit order. Register Bit 7 Bit 0...
Page 352 Periodic Interrupt Timer (S12PIT24B4CV1) Register Bit 7 Bit 0 Name 0x000D PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0 PITLD1 (Low) 0x000E PCNT15 PCNT14 PCNT13 PCNT12 PCNT11 PCNT10 PCNT9 PCNT8 PITCNT1 (High) 0x000F PCNT7 PCNT6 PCNT5 PCNT4 PCNT3 PCNT2 PCNT1 PCNT0 PITCNT1 (Low) 0x0010...
Page 353 Periodic Interrupt Timer (S12PIT24B4CV1) 12.3.0.1 PIT Control and Force Load Micro Timer Register (PITCFLMT) Module Base + 0x0000 PITE PITSWAI PITFRZ PFLMT1 PFLMT0 Reset = Unimplemented or Reserved Figure 12-3. PIT Control and Force Load Micro Timer Register (PITCFLMT) Read: Anytime Write: Anytime;...
Page 354 Periodic Interrupt Timer (S12PIT24B4CV1) 12.3.0.2 PIT Force Load Timer Register (PITFLT) Module Base + 0x0001 PFLT3 PFLT2 PFLT1 PFLT0 Reset Figure 12-4. PIT Force Load Timer Register (PITFLT) Read: Anytime Write: Anytime Table 12-3. PITFLT Field Descriptions Field Description PIT Force Load Bits for Timer 3-0 — These bits have only an effect if the corresponding timer channel (PCE PFLT[3:0] set) is enabled and if the PIT module is enabled (PITE set).
Page 355 Periodic Interrupt Timer (S12PIT24B4CV1) 12.3.0.4 PIT Multiplex Register (PITMUX) Module Base + 0x0003 PMUX3 PMUX2 PMUX1 PMUX0 Reset Figure 12-6. PIT Multiplex Register (PITMUX) Read: Anytime Write: Anytime Table 12-5. PITMUX Field Descriptions Field Description PIT Multiplex Bits for Timer Channel 3:0 — These bits select if the corresponding 16-bit timer is connected to PMUX[3:0] micro time base 1 or 0.
Page 356 Periodic Interrupt Timer (S12PIT24B4CV1) 12.3.0.6 PIT Time-Out Flag Register (PITTF) Module Base + 0x0005 PTF3 PTF2 PTF1 PTF0 Reset Figure 12-8. PIT Time-Out Flag Register (PITTF) Read: Anytime Write: Anytime (write to clear) Table 12-7. PITTF Field Descriptions Field Description PIT Time-out Flag Bits for Timer Channel 3:0 —...
Page 357 Periodic Interrupt Timer (S12PIT24B4CV1) Table 12-8. PITMTLD0–1 Field Descriptions Field Description PIT Micro Timer Load Bits 7:0 — These bits set the 8-bit modulus down-counter load value of the micro timers. PMTLD[7:0] Writing a new value into the PITMTLD register will not restart the timer. When the micro timer has counted down to zero, the PMTLD register value will be loaded.
Page 358 Periodic Interrupt Timer (S12PIT24B4CV1) 12.3.0.8 PIT Load Register 0 to 3 (PITLD0–3) Module Base + 0x0008, 0x0009 PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0 Reset Figure 12-11. PIT Load Register 0 (PITLD0) Module Base + 0x000C, 0x000D PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0 Reset...
Page 359 Periodic Interrupt Timer (S12PIT24B4CV1) 12.3.0.9 PIT Count Register 0 to 3 (PITCNT0–3) Module Base + 0x000A, 0x000B R PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT Reset Figure 12-15. PIT Count Register 0 (PITCNT0) Module Base + 0x000E, 0x000F R PCNT PCNT...
Page 360 Periodic Interrupt Timer (S12PIT24B4CV1) 12.4 Functional Description Figure 12-19 shows a detailed block diagram of the PIT module. The main parts of the PIT are status, control and data registers, two 8-bit down-counters, four 16-bit down-counters and an interrupt/trigger interface. PIT24B4C PFLT0 PITFLT Register...
Page 361 Periodic Interrupt Timer (S12PIT24B4CV1) Whenever a 16-bit timer counter and the connected 8-bit micro timer counter have counted to zero, the PITLD register is reloaded and the corresponding time-out ﬂag PTF in the PIT time-out ﬂag (PITTF) register is set, as shown in Figure 12-20.
Page 362 Periodic Interrupt Timer (S12PIT24B4CV1) is set, an interrupt service is requested whenever the corresponding time-out ﬂag PTF in the PIT time-out ﬂag (PITTF) register is set. The ﬂag can be cleared by writing a one to the ﬂag bit. NOTE Be careful when resetting the PITE, PINTE or PITCE bits in case of pending PIT interrupt requests, to avoid spurious interrupt requests.
Page 363 Periodic Interrupt Timer (S12PIT24B4CV1) 12.6 Application Information To get started quickly with the PIT24B8C module this section provides a small code example how to use the block. Please note that the example provided is only one speciﬁc case out of the possible conﬁgurations and implementations.
Page 364 Periodic Interrupt Timer (S12PIT24B4CV1) S12XS Family Reference Manual, Rev. 1.13 Freescale Semiconductor...
Page 365: Chapter 13 Pulse-Width Modulator (S12Pwm8B8Cv1)
Chapter 13 Pulse-Width Modulator (S12PWM8B8CV1) Version Revision Effective Author Description of Changes Number Date Date Added clariﬁcation of PWMIF operation in STOP and WAIT mode. 01.17 08-01-2004 Added notes on minimum pulse width of emergency shutdown signal. 13.1 Introduction The PWM deﬁnition is based on the HC12 PWM deﬁnitions. It contains the basic features from the HC11 with some of the enhancements incorporated on the HC12: center aligned output mode and four available clock sources.The PWM module has eight channels with independent control of left and center aligned outputs on each channel.
Page 366 Pulse-Width Modulator (S12PWM8B8CV1) 13.1.2 Modes of Operation There is a software programmable option for low power consumption in wait mode that disables the input clock to the prescaler. In freeze mode there is a software programmable option to disable the input clock to the prescaler. This is useful for emulation.
Page 367 Pulse-Width Modulator (S12PWM8B8CV1) 13.2.1 PWM7 — PWM Channel 7 This pin serves as waveform output of PWM channel 7 and as an input for the emergency shutdown feature. 13.2.2 PWM6 — PWM Channel 6 This pin serves as waveform output of PWM channel 6. 13.2.3 PWM5 —...
Page 368 Pulse-Width Modulator (S12PWM8B8CV1) with the PWM and their relative offset from the base address. The register detail description follows the order they appear in the register map. Reserved bits within a register will always read as 0 and the write will be unimplemented. Unimplemented functions are indicated by shading the bit.
Page 369 Pulse-Width Modulator (S12PWM8B8CV1) Register Bit 7 Bit 0 Name 0x000A PWMSCNTA 0x000B PWMSCNTB 0x000C Bit 7 Bit 0 PWMCNT0 0x000D Bit 7 Bit 0 PWMCNT1 0x000E Bit 7 Bit 0 PWMCNT2 0x000F Bit 7 Bit 0 PWMCNT3 0x0010 Bit 7 Bit 0 PWMCNT4 0x0011...
Page 370 Pulse-Width Modulator (S12PWM8B8CV1) Register Bit 7 Bit 0 Name 0x0019 Bit 7 Bit 0 PWMPER5 0x001A Bit 7 Bit 0 PWMPER6 0x001B Bit 7 Bit 0 PWMPER7 0x001C Bit 7 Bit 0 PWMDTY0 0x001D Bit 7 Bit 0 PWMDTY1 0x001E Bit 7 Bit 0 PWMDTY2...
Page 371 Pulse-Width Modulator (S12PWM8B8CV1) NOTE The ﬁrst PWM cycle after enabling the channel can be irregular. An exception to this is when channels are concatenated. Once concatenated mode is enabled (CONxx bits set in PWMCTL register), enabling/disabling the corresponding 16-bit PWM channel is controlled by the low order PWMEx bit.In this case, the high order bytes PWMEx bits have no effect and their corresponding PWM output lines are disabled.
Page 372 Pulse-Width Modulator (S12PWM8B8CV1) Table 13-1. PWME Field Descriptions (continued) Field Description Pulse Width Channel 1 Enable PWME1 0 Pulse width channel 1 is disabled. 1 Pulse width channel 1 is enabled. The pulse modulated signal becomes available at PWM, output bit 1 when its clock source begins its next cycle.
Page 373 Pulse-Width Modulator (S12PWM8B8CV1) Module Base + 0x0002 PCLK7 PCLKL6 PCLK5 PCLK4 PCLK3 PCLK2 PCLK1 PCLK0 Reset Figure 13-5. PWM Clock Select Register (PWMCLK) Read: Anytime Write: Anytime NOTE Register bits PCLK0 to PCLK7 can be written anytime. If a clock select is changed while a PWM signal is being generated, a truncated or stretched pulse can occur during the transition.
Page 374 Pulse-Width Modulator (S12PWM8B8CV1) Module Base + 0x0003 PCKB2 PCKB1 PCKB0 PCKA2 PCKA1 PCKA0 Reset = Unimplemented or Reserved Figure 13-6. PWM Prescale Clock Select Register (PWMPRCLK) Read: Anytime Write: Anytime NOTE PCKB2–0 and PCKA2–0 register bits can be written anytime. If the clock pre-scale is changed while a PWM signal is being generated, a truncated or stretched pulse can occur during the transition.
Page 375 Pulse-Width Modulator (S12PWM8B8CV1) 13.3.2.5 PWM Center Align Enable Register (PWMCAE) The PWMCAE register contains eight control bits for the selection of center aligned outputs or left aligned outputs for each PWM channel. If the CAEx bit is set to a one, the corresponding PWM output will be center aligned.
Page 376 Pulse-Width Modulator (S12PWM8B8CV1) 2 registers become the high order bytes of the double byte channel. When channels 0 and 1 are concatenated, channel 0 registers become the high order bytes of the double byte channel. Section 13.4.2.7, “PWM 16-Bit Functions” for a more detailed description of the concatenation PWM Function.
Page 377 Pulse-Width Modulator (S12PWM8B8CV1) 13.3.2.7 Reserved Register (PWMTST) This register is reserved for factory testing of the PWM module and is not available in normal modes. Module Base + 0x0006 Reset = Unimplemented or Reserved Figure 13-9. Reserved Register (PWMTST) Read: Always read $00 in normal modes Write: Unimplemented in normal modes NOTE Writing to this register when in special modes can alter the PWM...
Page 378 Pulse-Width Modulator (S12PWM8B8CV1) NOTE When PWMSCLA = $00, PWMSCLA value is considered a full scale value of 256. Clock A is thus divided by 512. Any value written to this register will cause the scale counter to load the new scale value (PWMSCLA). Module Base + 0x0008 Bit 7 Bit 0...
Page 379 Pulse-Width Modulator (S12PWM8B8CV1) Module Base + 0x000A, 0x000B Reset = Unimplemented or Reserved Figure 13-13. Reserved Registers (PWMSCNTx) Read: Always read $00 in normal modes Write: Unimplemented in normal modes NOTE Writing to these registers when in special modes can alter the PWM functionality.
Page 380 Pulse-Width Modulator (S12PWM8B8CV1) Write: Anytime (any value written causes PWM counter to be reset to $00). 13.3.2.13 PWM Channel Period Registers (PWMPERx) There is a dedicated period register for each channel. The value in this register determines the period of the associated PWM channel.
Page 381 Pulse-Width Modulator (S12PWM8B8CV1) 13.3.2.14 PWM Channel Duty Registers (PWMDTYx) There is a dedicated duty register for each channel. The value in this register determines the duty of the associated PWM channel. The duty value is compared to the counter and if it is equal to the counter value a match occurs and the output changes state.
Page 382 Pulse-Width Modulator (S12PWM8B8CV1) Write: Anytime 13.3.2.15 PWM Shutdown Register (PWMSDN) The PWMSDN register provides for the shutdown functionality of the PWM module in the emergency cases. For proper operation, channel 7 must be driven to the active level for a minimum of two bus clocks. Module Base + 0x0024 PWM7IN PWMIF...
Page 383 Pulse-Width Modulator (S12PWM8B8CV1) 13.4 Functional Description 13.4.1 PWM Clock Select There are four available clocks: clock A, clock B, clock SA (scaled A), and clock SB (scaled B). These four clocks are based on the bus clock. Clock A and B can be software selected to be 1, 1/2, 1/4, 1/8,..., 1/64, 1/128 times the bus clock. Clock SA uses clock A as an input and divides it further with a reloadable counter.
Page 384 Pulse-Width Modulator (S12PWM8B8CV1) Clock A Clock to PWM Ch 0 Clock A/2, A/4, A/6,..A/512 PCLK0 Count = 1 8-Bit Down Counter Clock to PWM Ch 1 Load PCLK1 Clock SA PWMSCLA DIV 2 Clock to PWM Ch 2 PCLK2 Clock to PWM Ch 3 PCLK3 Clock B...
Page 385 Pulse-Width Modulator (S12PWM8B8CV1) Clock A is used as an input to an 8-bit down counter. This down counter loads a user programmable scale value from the scale register (PWMSCLA). When the down counter reaches one, a pulse is output and the 8-bit counter is re-loaded.
Page 386 Pulse-Width Modulator (S12PWM8B8CV1) 13.4.2 PWM Channel Timers The main part of the PWM module are the actual timers. Each of the timer channels has a counter, a period register and a duty register (each are 8-bit). The waveform output period is controlled by a match between the period register and the value in the counter.
Page 387 Pulse-Width Modulator (S12PWM8B8CV1) On the front end of the PWM timer, the clock is enabled to the PWM circuit by the PWMEx bit being high. There is an edge-synchronizing circuit to guarantee that the clock will only be enabled or disabled at an edge.
Page 388 Pulse-Width Modulator (S12PWM8B8CV1) Each channel counter can be read at anytime without affecting the count or the operation of the PWM channel. Any value written to the counter causes the counter to reset to $00, the counter direction to be set to up, the immediate load of both duty and period registers with values from the buffers, and the output to change according to the polarity bit.
Page 389 Pulse-Width Modulator (S12PWM8B8CV1) NOTE Changing the PWM output mode from left aligned to center aligned output (or vice versa) while channels are operating can cause irregularities in the PWM output. It is recommended to program the output mode before enabling the PWM channel. PPOLx = 0 PPOLx = 1 PWMDTYx...
Page 390 Pulse-Width Modulator (S12PWM8B8CV1) E = 100 ns Duty Cycle = 75% Period = 400 ns Figure 13-21. PWM Left Aligned Output Example Waveform 13.4.2.6 Center Aligned Outputs For center aligned output mode selection, set the CAEx bit (CAEx = 1) in the PWMCAE register and the corresponding PWM output will be center aligned.
Page 391 Pulse-Width Modulator (S12PWM8B8CV1) To calculate the output frequency in center aligned output mode for a particular channel, take the selected clock source frequency for the channel (A, B, SA, or SB) and divide it by twice the value in the period register for that channel.
Page 392 Pulse-Width Modulator (S12PWM8B8CV1) As an example of a center aligned output, consider the following case: Clock Source = E, where E = 10 MHz (100 ns period) PPOLx = 0 PWMPERx = 4 PWMDTYx = 1 PWMx Frequency = 10 MHz/8 = 1.25 MHz PWMx Period = 800 ns PWMx Duty Cycle = 3/4 *100% = 75% Shown in...
Page 393 Pulse-Width Modulator (S12PWM8B8CV1) Clock Source 7 High PWMCNT6 PWCNT7 PWM7 Period/Duty Compare Clock Source 5 High PWMCNT4 PWCNT5 PWM5 Period/Duty Compare Clock Source 3 High PWMCNT2 PWCNT3 PWM3 Period/Duty Compare Clock Source 1 High PWMCNT0 PWCNT1 PWM1 Period/Duty Compare Figure 13-24. PWM 16-Bit Mode Once concatenated mode is enabled (CONxx bits set in PWMCTL register), enabling/disabling the corresponding 16-bit PWM channel is controlled by the low order PWMEx bit.
Page 394 Pulse-Width Modulator (S12PWM8B8CV1) Either left aligned or center aligned output mode can be used in concatenated mode and is controlled by the low order CAEx bit. The high order CAEx bit has no effect. Table 13-11 is used to summarize which channels are used to set the various control bits when in 16-bit mode.
Page 395 Pulse-Width Modulator (S12PWM8B8CV1) 13.6 Interrupts The PWM module has only one interrupt which is generated at the time of emergency shutdown, if the corresponding enable bit (PWMIE) is set. This bit is the enable for the interrupt. The interrupt ﬂag PWMIF is set whenever the input level of the PWM7 channel changes while PWM7ENA = 1 or when PWMENA is being asserted while the level at PWM7 is active.
Page 396 Pulse-Width Modulator (S12PWM8B8CV1) S12XS Family Reference Manual, Rev. 1.13 Freescale Semiconductor...
Page 397: Chapter 14 Serial Communication Interface (S12Sciv5)
Chapter 14 Serial Communication Interface (S12SCIV5) Table 14-1. Revision History Version Revision Effective Author Description of Changes Number Date Date 05.03 12/25/2008 remove redundancy comments in Figure1-2 fix typo, SCIBDL reset value be 0x04, not 0x00 05.04 08/05/2009 fix typo, Table 14-4,SCICR1 Even parity should be PT=0 05.05...
Page 398 Serial Communication Interface (S12SCIV5) 14.1.2 Features The SCI includes these distinctive features: • Full-duplex or single-wire operation • Standard mark/space non-return-to-zero (NRZ) format • Selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse widths • 13-bit baud rate selection • Programmable 8-bit or 9-bit data format •...
Page 399 Serial Communication Interface (S12SCIV5) 14.1.4 Block Diagram Figure 14-1 is a high level block diagram of the SCI module, showing the interaction of various function blocks. SCI Data Register RXD Data In Infrared Receive Shift Register Decoder IDLE Receive RDRF/OR Interrupt Receive &...
Page 400 Serial Communication Interface (S12SCIV5) 14.2 External Signal Description The SCI module has a total of two external pins. 14.2.1 TXD — Transmit Pin The TXD pin transmits SCI (standard or infrared) data. It will idle high in either mode and is high impedance anytime the transmitter is disabled.
Page 401 Serial Communication Interface (S12SCIV5) 14.3.2 Register Descriptions This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated ﬁgure number. Writes to a reserved register locations do not have any effect and reads of these locations return a zero. Details of register bit and ﬁeld function follow the register diagrams, in bit order.
Page 402 Serial Communication Interface (S12SCIV5) 14.3.2.1 SCI Baud Rate Registers (SCIBDH, SCIBDL) Module Base + 0x0000 IREN TNP1 TNP0 SBR12 SBR11 SBR10 SBR9 SBR8 Reset Figure 14-3. SCI Baud Rate Register (SCIBDH) Module Base + 0x0001 SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0...
Page 403 Serial Communication Interface (S12SCIV5) Table 14-3. IRSCI Transmit Pulse Width TNP[1:0] Narrow Pulse Width 1/32 1/16 3/16 14.3.2.2 SCI Control Register 1 (SCICR1) Module Base + 0x0002 LOOPS SCISWAI RSRC WAKE Reset Figure 14-5. SCI Control Register 1 (SCICR1) Read: Anytime, if AMAP = 0. Write: Anytime, if AMAP = 0.
Page 404 Serial Communication Interface (S12SCIV5) Table 14-4. SCICR1 Field Descriptions (continued) Field Description Idle Line Type Bit — ILT determines when the receiver starts counting logic 1s as idle character bits. The counting begins either after the start bit or after the stop bit. If the count begins after the start bit, then a string of logic 1s preceding the stop bit may cause false recognition of an idle character.
Page 405 Serial Communication Interface (S12SCIV5) 14.3.2.3 SCI Alternative Status Register 1 (SCIASR1) Module Base + 0x0000 BERRV RXEDGIF BERRIF BKDIF Reset = Unimplemented or Reserved Figure 14-6. SCI Alternative Status Register 1 (SCIASR1) Read: Anytime, if AMAP = 1 Write: Anytime, if AMAP = 1 Table 14-6.
Page 406 Serial Communication Interface (S12SCIV5) 14.3.2.4 SCI Alternative Control Register 1 (SCIACR1) Module Base + 0x0001 RXEDGIE BERRIE BKDIE Reset = Unimplemented or Reserved Figure 14-7. SCI Alternative Control Register 1 (SCIACR1) Read: Anytime, if AMAP = 1 Write: Anytime, if AMAP = 1 Table 14-7.
Page 407 Serial Communication Interface (S12SCIV5) 14.3.2.5 SCI Alternative Control Register 2 (SCIACR2) Module Base + 0x0002 BERRM1 BERRM0 BKDFE Reset = Unimplemented or Reserved Figure 14-8. SCI Alternative Control Register 2 (SCIACR2) Read: Anytime, if AMAP = 1 Write: Anytime, if AMAP = 1 Table 14-8.
Page 408 Serial Communication Interface (S12SCIV5) 14.3.2.6 SCI Control Register 2 (SCICR2) Module Base + 0x0003 TCIE ILIE Reset Figure 14-9. SCI Control Register 2 (SCICR2) Read: Anytime Write: Anytime Table 14-10. SCICR2 Field Descriptions Field Description Transmitter Interrupt Enable Bit — TIE enables the transmit data register empty ﬂag, TDRE, to generate interrupt requests.
Page 409 Serial Communication Interface (S12SCIV5) 14.3.2.7 SCI Status Register 1 (SCISR1) The SCISR1 and SCISR2 registers provides inputs to the MCU for generation of SCI interrupts. Also, these registers can be polled by the MCU to check the status of these bits. The ﬂag-clearing procedures require that the status register be read followed by a read or write to the SCI data register.It is permissible to execute other instructions between the two steps as long as it does not compromise the handling of I/O, but the order of operations is important for ﬂag clearing.
Page 410 Serial Communication Interface (S12SCIV5) Table 14-11. SCISR1 Field Descriptions (continued) Field Description Overrun Flag — OR is set when software fails to read the SCI data register before the receive shift register receives the next frame. The OR bit is set immediately after the stop bit has been completely received for the second frame.
Page 411 Serial Communication Interface (S12SCIV5) 14.3.2.8 SCI Status Register 2 (SCISR2) Module Base + 0x0005 AMAP TXPOL RXPOL BRK13 TXDIR Reset = Unimplemented or Reserved Figure 14-11. SCI Status Register 2 (SCISR2) Read: Anytime Write: Anytime Table 14-12. SCISR2 Field Descriptions Field Description Alternative Map —...
Page 412 Serial Communication Interface (S12SCIV5) 14.3.2.9 SCI Data Registers (SCIDRH, SCIDRL) Module Base + 0x0006 Reset = Unimplemented or Reserved Figure 14-12. SCI Data Registers (SCIDRH) Module Base + 0x0007 Reset Figure 14-13. SCI Data Registers (SCIDRL) Read: Anytime; reading accesses SCI receive data register Write: Anytime;...
Page 413 Serial Communication Interface (S12SCIV5) 14.4 Functional Description This section provides a complete functional description of the SCI block, detailing the operation of the design from the end user perspective in a number of subsections. Figure 14-14 shows the structure of the SCI module. The SCI allows full duplex, asynchronous, serial communication between the CPU and remote devices, including other CPUs.
Page 414 Serial Communication Interface (S12SCIV5) 14.4.1 Infrared Interface Submodule This module provides the capability of transmitting narrow pulses to an IR LED and receiving narrow pulses and transforming them to serial bits, which are sent to the SCI. The IrDA physical layer speciﬁcation deﬁnes a half-duplex infrared communication link for exchange data.
Page 415 Serial Communication Interface (S12SCIV5) 14.4.3 Data Format The SCI uses the standard NRZ mark/space data format. When Infrared is enabled, the SCI uses RZI data format where zeroes are represented by light pulses and ones remain low. See Figure 14-15 below.
Page 416 Serial Communication Interface (S12SCIV5) The address bit identiﬁes the frame as an address character. See Section 14.4.6.6, “Receiver Wakeup”. 14.4.4 Baud Rate Generation A 13-bit modulus counter in the baud rate generator derives the baud rate for both the receiver and the transmitter.
Page 417 Serial Communication Interface (S12SCIV5) 14.4.5 Transmitter Internal Bus ÷ 16 Baud Divider SCI Data Registers Clock SBR12:SBR0 TXPOL 11-Bit Transmit Register SCTXD LOOP To Receiver CONTROL Parity LOOPS Generation RSRC TDRE IRQ TDRE Transmitter Control TC IRQ TCIE BERRM[1:0] SCTXD BERRIF Transmit BER IRQ...
Page 418 Serial Communication Interface (S12SCIV5) The SCI also sets a ﬂag, the transmit data register empty ﬂag (TDRE), every time it transfers data from the buffer (SCIDRH/L) to the transmitter shift register.The transmit driver routine may respond to this ﬂag by writing another byte to the Transmitter buffer (SCIDRH/SCIDRL), while the shift register is still shifting out the ﬁrst byte.
Page 419 Serial Communication Interface (S12SCIV5) When the transmit shift register is not transmitting a frame, the TXD pin goes to the idle condition, logic 1. If at any time software clears the TE bit in SCI control register 2 (SCICR2), the transmitter enable signal goes low and the transmit signal goes idle.
Page 420 Serial Communication Interface (S12SCIV5) Figure 14-17 shows two cases of break detect. In trace RXD_1 the break symbol starts with the start bit, while in RXD_2 the break starts in the middle of a transmission. If BRKDFE = 1, in RXD_1 case there will be no byte transferred to the receive buffer and the RDRF ﬂag will not be modiﬁed.
Page 421 Serial Communication Interface (S12SCIV5) 14.4.5.5 LIN Transmit Collision Detection This module allows to check for collisions on the LIN bus. LIN Physical Interface Synchronizer Stage Receive Shift Register Compare RXD Pin Bit Error LIN Bus Bus Clock Sample Point Transmit Shift Register TXD Pin Figure 14-18.
Page 422 Serial Communication Interface (S12SCIV5) 14.4.6 Receiver Internal Bus SBR12:SBR0 SCI Data Register Baud Divider Clock 11-Bit Receive Shift Register RXPOL Data Recovery SCRXD Loop From TXD Pin Control or Transmitter LOOPS RSRC WAKE Wakeup Logic Parity Checking Idle IRQ IDLE ILIE RDRF/OR BRKDFE...
Page 423 Serial Communication Interface (S12SCIV5) indicating that the received byte can be read. If the receive interrupt enable bit, RIE, in SCI control register 2 (SCICR2) is also set, the RDRF ﬂag generates an RDRF interrupt request. 14.4.6.3 Data Sampling The RT clock rate. The RT clock is an internal signal with a frequency 16 times the baud rate. To adjust for baud rate mismatch, the RT clock (see Figure 14-21) is re-synchronized:...
Page 424 Serial Communication Interface (S12SCIV5) To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 14-18 summarizes the results of the data bit samples. Table 14-18. Data Bit Recovery RT8, RT9, and RT10 Samples Data Bit Determination Noise Flag...
Page 425 Serial Communication Interface (S12SCIV5) Figure 14-22 the veriﬁcation samples RT3 and RT5 determine that the ﬁrst low detected was noise and not the beginning of a start bit. The RT clock is reset and the start bit search begins again. The noise ﬂag is not set because the noise occurred before the start bit was found.
Page 426 Serial Communication Interface (S12SCIV5) Figure 14-24, a large burst of noise is perceived as the beginning of a start bit, although the test sample at RT5 is high. The RT5 sample sets the noise ﬂag. Although this is a worst-case misalignment of perceived bit time, the data samples RT8, RT9, and RT10 are within the bit time and data recovery is successful.
Page 427 Serial Communication Interface (S12SCIV5) Figure 14-26 shows a burst of noise near the beginning of the start bit that resets the RT clock. The sample after the reset is low but is not preceded by three high samples that would qualify as a falling edge. Depending on the timing of the start bit search and on the data, the frame may be missed entirely or it may set the framing error ﬂag.
Page 428 Serial Communication Interface (S12SCIV5) 14.4.6.5 Baud Rate Tolerance A transmitting device may be operating at a baud rate below or above the receiver baud rate. Accumulated bit time misalignment can cause one of the three stop bit data samples (RT8, RT9, and RT10) to fall outside the actual stop bit.
Page 429 Serial Communication Interface (S12SCIV5) 14.4.6.5.2 Fast Data Tolerance Figure 14-29 shows how much a fast received frame can be misaligned. The fast stop bit ends at RT10 instead of RT16 but is still sampled at RT8, RT9, and RT10. Stop Idle or Next Frame Receiver RT Clock...
Page 430 Serial Communication Interface (S12SCIV5) 14.4.6.6.1 Idle Input line Wakeup (WAKE = 0) In this wakeup method, an idle condition on the RXD pin clears the RWU bit and wakes up the SCI. The initial frame or frames of every message contain addressing information. All receivers evaluate the addressing information, and receivers for which the message is addressed process the frames that follow.
Page 431 Serial Communication Interface (S12SCIV5) Enable single-wire operation by setting the LOOPS bit and the receiver source bit, RSRC, in SCI control register 1 (SCICR1). Setting the LOOPS bit disables the path from the RXD pin to the receiver. Setting the RSRC bit connects the TXD pin to the receiver. Both the transmitter and receiver must be enabled (TE = 1 and RE = 1).The TXDIR bit (SCISR2[1]) determines whether the TXD pin is going to be used as an input (TXDIR = 0) or an output (TXDIR = 1) in this mode of operation.
Page 432 Serial Communication Interface (S12SCIV5) 14.5.2.2 Wait Mode SCI operation in wait mode depends on the state of the SCISWAI bit in the SCI control register 1 (SCICR1). • If SCISWAI is clear, the SCI operates normally when the CPU is in wait mode. •...
Page 433 Serial Communication Interface (S12SCIV5) 14.5.3.1 Description of Interrupt Operation The SCI only originates interrupt requests. The following is a description of how the SCI makes a request and how the MCU should acknowledge that request. The interrupt vector offset and interrupt number are chip dependent.
Page 434 Serial Communication Interface (S12SCIV5) 14.5.3.1.6 RXEDGIF Description The RXEDGIF interrupt is set when an active edge (falling if RXPOL = 0, rising if RXPOL = 1) on the RXD pin is detected. Clear RXEDGIF by writing a “1” to the SCIASR1 SCI alternative status register 1. 14.5.3.1.7 BERRIF Description The BERRIF interrupt is set when a mismatch between the transmitted and the received data in a single...
Page 435: Chapter 15 Serial Peripheral Interface (S12Spiv5)
Chapter 15 Serial Peripheral Interface (S12SPIV5) Table 15-1. Revision History Revision Sections Revision Date Description of Changes Number Affected V05.00 24 Mar 2005 15.3.2/15-439 - Added 16-bit transfer width feature. 15.1 Introduction The SPI module allows a duplex, synchronous, serial communication between the MCU and peripheral devices.
Page 436 Serial Peripheral Interface (S12SPIV5) • Run mode This is the basic mode of operation. • Wait mode SPI operation in wait mode is a conﬁgurable low power mode, controlled by the SPISWAI bit located in the SPICR2 register. In wait mode, if the SPISWAI bit is clear, the SPI operates like in run mode.
Page 437 Serial Peripheral Interface (S12SPIV5) SPI Control Register 1 BIDIROE SPI Control Register 2 SPC0 SPI Status Register Slave CPOL CPHA MOSI Control SPIF MODF SPTEF Phase + SCK In Interrupt Control Polarity Slave Baud Rate Control Interrupt Master Baud Rate Phase + SCK Out Polarity...
Page 438 Serial Peripheral Interface (S12SPIV5) 15.2.3 SS — Slave Select Pin This pin is used to output the select signal from the SPI module to another peripheral with which a data transfer is to take place when it is conﬁgured as a master and it is used as an input to receive the slave select signal when the SPI is conﬁgured as slave.
Page 439 Serial Peripheral Interface (S12SPIV5) 15.3.2 Register Descriptions This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated ﬁgure number. Details of register bit and ﬁeld function follow the register diagrams, in bit order. 15.3.2.1 SPI Control Register 1 (SPICR1) Module Base +0x0000...
Page 440 Serial Peripheral Interface (S12SPIV5) Table 15-2. SPICR1 Field Descriptions (continued) Field Description Slave Select Output Enable — The SS output feature is enabled only in master mode, if MODFEN is set, by SSOE asserting the SSOE as shown in Table 15-3.
Page 441 Serial Peripheral Interface (S12SPIV5) Table 15-4. SPICR2 Field Descriptions Field Description Transfer Width — This bit is used for selecting the data transfer width. If 8-bit transfer width is selected, SPIDRL XFRW becomes the dedicated data register and SPIDRH is unused. If 16-bit transfer width is selected, SPIDRH and SPIDRL form a 16-bit data register.
Page 442 Serial Peripheral Interface (S12SPIV5) 15.3.2.3 SPI Baud Rate Register (SPIBR) Module Base +0x0002 SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 Reset = Unimplemented or Reserved Figure 15-5. SPI Baud Rate Register (SPIBR) Read: Anytime Write: Anytime; writes to the reserved bits have no effect Table 15-6.
Page 443 Serial Peripheral Interface (S12SPIV5) Table 15-7. Example SPI Baud Rate Selection (25 MHz Bus Clock) (Sheet 2 of 3) Baud Rate SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 Baud Rate Divisor 390.63 kbit/s 195.31 kbit/s 97.66 kbit/s 48.83 kbit/s 4.16667 Mbit/s 2.08333 Mbit/s 1.04167 Mbit/s 520.83 kbit/s...
Page 444 Serial Peripheral Interface (S12SPIV5) Table 15-7. Example SPI Baud Rate Selection (25 MHz Bus Clock) (Sheet 3 of 3) Baud Rate SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 Baud Rate Divisor 27.90 kbit/s 1792 13.95 kbit/s 1.5625 Mbit/s 781.25 kbit/s 390.63 kbit/s 195.31 kbit/s 97.66 kbit/s 48.83 kbit/s...
Page 445 Serial Peripheral Interface (S12SPIV5) Table 15-9. SPIF Interrupt Flag Clearing Sequence XFRW Bit SPIF Interrupt Flag Clearing Sequence Read SPISR with SPIF == 1 Read SPIDRL then Read SPISR with SPIF == 1 Byte Read SPIDRL then Byte Read SPIDRH Byte Read SPIDRL Word Read (SPIDRH:SPIDRL) Data in SPIDRH is lost in this case.
Page 446 Serial Peripheral Interface (S12SPIV5) 15.3.2.5 SPI Data Register (SPIDR = SPIDRH:SPIDRL) Module Base +0x0004 Reset Figure 15-7. SPI Data Register High (SPIDRH) Module Base +0x0005 Reset Figure 15-8. SPI Data Register Low (SPIDRL) Read: Anytime; read data only valid when SPIF is set Write: Anytime The SPI data register is both the input and output register for SPI data.
Page 447 Serial Peripheral Interface (S12SPIV5) Data A Received Data B Received Data C Received SPIF Serviced Receive Shift Register Data B Data A Data C SPIF Data B Data C SPI Data Register Data A = Unspeciﬁed = Reception in progress Figure 15-9.
Page 448 Serial Peripheral Interface (S12SPIV5) The main element of the SPI system is the SPI data register. The n-bit data register in the master and the n-bit data register in the slave are linked by the MOSI and MISO pins to form a distributed 2n-bit register.
Page 449 Serial Peripheral Interface (S12SPIV5) drive the MOSI and SCK lines. In this case, the SPI immediately switches to slave mode, by clearing the MSTR bit and also disables the slave output buffer MISO (or SISO in bidirectional mode). So the result is that all outputs are disabled and SCK, MOSI, and MISO are inputs. If a transmission is in progress when the mode fault occurs, the transmission is aborted and the SPI is forced into idle state.
Page 450 Serial Peripheral Interface (S12SPIV5) As long as no more than one slave device drives the system slave’s serial data output line, it is possible for several slaves to receive the same transmission from a master, although the master would not receive return information from all of the receiving slaves.
Page 451 Serial Peripheral Interface (S12SPIV5) The CPOL clock polarity control bit speciﬁes an active high or low clock and has no signiﬁcant effect on the transmission format. The CPHA clock phase control bit selects one of two fundamentally different transmission formats. Clock phase and polarity should be identical for the master SPI device and the communicating slave device.
Page 452 Serial Peripheral Interface (S12SPIV5) End of Idle State Begin of Idle State Begin Transfer 13 14 SCK Edge Number SCK (CPOL = 0) SCK (CPOL = 1) SAMPLE I MOSI/MISO CHANGE O MOSI pin CHANGE O MISO pin SEL SS (O) Master only SEL SS (I) MSB ﬁrst (LSBFE = 0):...
Page 453 Serial Peripheral Interface (S12SPIV5) End of Idle State Begin of Idle State Begin Transfer SCK Edge Number SCK (CPOL = 0) SCK (CPOL = 1) SAMPLE I MOSI/MISO CHANGE O MOSI pin CHANGE O MISO pin SEL SS (O) Master only SEL SS (I) Bit 14 Bit 13...
Page 454 Serial Peripheral Interface (S12SPIV5) When the third edge occurs, the value previously latched from the serial data input pin is shifted into the LSB or MSB of the SPI shift register, depending on LSBFE bit. After this edge, the next bit of the master data is coupled out of the serial data output pin of the master to the serial input pin on the slave.
Page 455 Serial Peripheral Interface (S12SPIV5) End of Idle State Begin of Idle State Begin Transfer SCK Edge Number SCK (CPOL = 0) SCK (CPOL = 1) SAMPLE I MOSI/MISO CHANGE O MOSI pin CHANGE O MISO pin SEL SS (O) Master only SEL SS (I) Minimum 1/2 SCK Bit 14...
Page 456 Serial Peripheral Interface (S12SPIV5) When all bits are clear (the default condition), the SPI module clock is divided by 2. When the selection bits (SPR2–SPR0) are 001 and the preselection bits (SPPR2–SPPR0) are 000, the module clock divisor becomes 4. When the selection bits are 010, the module clock divisor becomes 8, etc. When the preselection bits are 001, the divisor determined by the selection bits is multiplied by 2.
Page 457 Serial Peripheral Interface (S12SPIV5) Table 15-11. Normal Mode and Bidirectional Mode When SPE = 1 Master Mode MSTR = 1 Slave Mode MSTR = 0 MOSI Serial Out Serial In MOSI Normal Mode SPC0 = 0 Serial Out MISO Serial In MISO Serial In Serial Out...
Page 458 Serial Peripheral Interface (S12SPIV5) the SPI system is conﬁgured as a slave, the SS pin is a dedicated input pin. Mode fault error doesn’t occur in slave mode. If a mode fault error occurs, the SPI is switched to slave mode, with the exception that the slave output buffer is disabled.
Page 459 Serial Peripheral Interface (S12SPIV5) NOTE Care must be taken when expecting data from a master while the slave is in wait or stop mode. Even though the shift register will continue to operate, the rest of the SPI is shut down (i.e., a SPIF interrupt will not be generated until exiting stop or wait mode).
Page 460 Serial Peripheral Interface (S12SPIV5) 15.4.7.5.2 SPIF SPIF occurs when new data has been received and copied to the SPI data register. After SPIF is set, it does not clear until it is serviced. SPIF has an automatic clearing process, which is described in Section 15.3.2.4, “SPI Status Register (SPISR)”.
Page 461: Chapter 16 Timer Module (Tim16B8Cv2)
Chapter 16 Timer Module (TIM16B8CV2) Table 16-1. Revision History Revision Revision Date Sections Affected Description of Changes Number V02.05 9 Jul 2009 16.3.2.12/16-477 - Revised ﬂag clearing procedure, whereby TEN or PAEN bit must be set 16.3.2.13/16-477 when clearing ﬂags. 16.3.2.15/16-479 - Add fomula to describe prescaler 16.3.2.16/16-480...
Page 462 Timer Module (TIM16B8CV2) • Eight input capture/output compare channels. • Clock prescaling. • 16-bit counter. • 16-bit pulse accumulator. 16.1.2 Modes of Operation Stop: Timer is off because clocks are stopped. Freeze: Timer counter keep on running, unless TSFRZ in TSCR1 (0x0006) is set to 1. Wait: Counters keep on running, unless TSWAI in TSCR1 (0x0006) is set to 1.
Page 463 Timer Module (TIM16B8CV2) 16.1.3 Block Diagrams Channel 0 Input capture Prescaler Bus clock IOC0 Output compare Channel 1 Input capture 16-bit Counter IOC1 Output compare Channel 2 Timer overflow Input capture interrupt IOC2 Output compare Timer channel 0 Channel 3 interrupt Input capture IOC3...
Page 464 Timer Module (TIM16B8CV2) TIMCLK (Timer clock) CLK1 4:1 MUX CLK0 Clock select Prescaled clock (PCLK) (PAMOD) Edge detector Interrupt PACNT M clock Divide by 64 Figure 16-2. 16-Bit Pulse Accumulator Block Diagram 16-bit Main Timer Edge detector Set CnF Interrupt TCn Input Capture Reg.
Page 465 Timer Module (TIM16B8CV2) PULSE ACCUMULATOR CHANNEL 7 OUTPUT COMPARE OCPD TIOS7 Figure 16-4. Channel 7 Output Compare/Pulse Accumulator Logic 16.2 External Signal Description The TIM16B8CV2 module has a total of eight external pins. 16.2.1 IOC7 — Input Capture and Output Compare Channel 7 Pin This pin serves as input capture or output compare for channel 7.
Page 466 Timer Module (TIM16B8CV2) 16.2.7 IOC1 — Input Capture and Output Compare Channel 1 Pin This pin serves as input capture or output compare for channel 1. 16.2.8 IOC0 — Input Capture and Output Compare Channel 0 Pin This pin serves as input capture or output compare for channel 0. NOTE For the description of interrupts see Section 16.6,...
Page 467 Timer Module (TIM16B8CV2) Register Bit 7 Bit 0 Name 0x0006 TSWAI TSFRZ TFFCA PRNT TSCR1 0x0007 TOV7 TOV6 TOV5 TOV4 TOV3 TOV2 TOV1 TOV0 TTOV 0x0008 TCTL1 0x0009 TCTL2 0x000A EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A TCTL3 0x000B EDG3B EDG3A EDG2B...
Page 468 Timer Module (TIM16B8CV2) Register Bit 7 Bit 0 Name 0x002C OCPD7 OCPD6 OCPD5 OCPD4 OCPD3 OCPD2 OCPD1 OCPD0 OCPD 0x002D 0x002E PTPS7 PTPS6 PTPS5 PTPS4 PTPS3 PTPS2 PTPS1 PTPS0 PTPSR 0x002F Reserved = Unimplemented or Reserved Figure 16-5. TIM16B8CV2 Register Summary (Sheet 3 of 3) 16.3.2.1 Timer Input Capture/Output Compare Select (TIOS) Module Base + 0x0000...
Page 469 Timer Module (TIM16B8CV2) Read: Anytime but will always return 0x0000 (1 state is transient) Write: Anytime Table 16-3. CFORC Field Descriptions Field Description Force Output Compare Action for Channel 7:0 — A write to this register with the corresponding data bit(s) set FOC[7:0] causes the action which is programmed for output compare “x”...
Page 470 Timer Module (TIM16B8CV2) 16.3.2.4 Output Compare 7 Data Register (OC7D) Module Base + 0x0003 OC7D7 OC7D6 OC7D5 OC7D4 OC7D3 OC7D2 OC7D1 OC7D0 Reset Figure 16-9. Output Compare 7 Data Register (OC7D) Read: Anytime Write: Anytime Table 16-5. OC7D Field Descriptions Field Description Output Compare 7 Data —...
Page 471 Timer Module (TIM16B8CV2) Write: Has no meaning or effect in the normal mode; only writable in special modes (test_mode = 1). The period of the ﬁrst count after a write to the TCNT registers may be a different size because the write is not synchronized with the prescaler clock.
Page 472 Timer Module (TIM16B8CV2) Table 16-6. TSCR1 Field Descriptions (continued) Field Description Timer Fast Flag Clear All TFFCA 0 Allows the timer ﬂag clearing to function normally. 1 For TFLG1(0x000E), a read from an input capture or a write to the output compare channel (0x0010–0x001F) causes the corresponding channel ﬂag, CnF, to be cleared.
Page 473 Timer Module (TIM16B8CV2) 16.3.2.8 Timer Control Register 1/Timer Control Register 2 (TCTL1/TCTL2) Module Base + 0x0008 Reset Figure 16-14. Timer Control Register 1 (TCTL1) Module Base + 0x0009 Reset Figure 16-15. Timer Control Register 2 (TCTL2) Read: Anytime Write: Anytime Table 16-8.
Page 474 Timer Module (TIM16B8CV2) To operate the 16-bit pulse accumulator independently of input capture or output compare 7 and 0 respectively the user must set the corresponding bits IOSx = 1, OMx = 0 and OLx = 0. OC7M7 in the OC7M register must also be cleared.
Page 475 Timer Module (TIM16B8CV2) Read: Anytime Write: Anytime. Table 16-11. TCTL3/TCTL4 Field Descriptions Field Description Input Capture Edge Control — These eight pairs of control bits conﬁgure the input capture edge detector EDGnB circuits. EDGnA Table 16-12. Edge Detector Circuit Conﬁguration EDGnB EDGnA Conﬁguration...
Page 476 Timer Module (TIM16B8CV2) 16.3.2.11 Timer System Control Register 2 (TSCR2) Module Base + 0x000D TCRE Reset = Unimplemented or Reserved Figure 16-19. Timer System Control Register 2 (TSCR2) Read: Anytime Write: Anytime. Table 16-14. TSCR2 Field Descriptions Field Description Timer Overﬂow Interrupt Enable 0 Interrupt inhibited.
Page 477 Timer Module (TIM16B8CV2) NOTE The newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter stages equal zero. 16.3.2.12 Main Timer Interrupt Flag 1 (TFLG1) Module Base + 0x000E Reset Figure 16-20. Main Timer Interrupt Flag 1 (TFLG1) Read: Anytime Write: Used in the clearing mechanism (set bits cause corresponding bits to be cleared).
Page 478 Timer Module (TIM16B8CV2) Table 16-17. TRLG2 Field Descriptions Field Description Timer Overﬂow Flag — Set when 16-bit free-running timer overﬂows from 0xFFFF to 0x0000. Clearing this bit requires writing a one to bit 7 of TFLG2 register while the TEN bit of TSCR1 or PAEN bit of PACTL is set to one (See also TCRE control bit explanation.) 16.3.2.14 Timer Input Capture/Output Compare Registers High and Low 0–7 (TCxH and TCxL)
Page 479 Timer Module (TIM16B8CV2) 16.3.2.15 16-Bit Pulse Accumulator Control Register (PACTL) Module Base + 0x0020 PAEN PAMOD PEDGE CLK1 CLK0 PAOVI Reset Unimplemented or Reserved Figure 16-24. 16-Bit Pulse Accumulator Control Register (PACTL) When PAEN is set, the PACT is enabled.The PACT shares the input pin with IOC7. Read: Any time Write: Any time Table 16-18.
Page 480 Timer Module (TIM16B8CV2) Table 16-19. Pin Action PAMOD PEDGE Pin Action Falling edge Rising edge Div. by 64 clock enabled with pin high level Div. by 64 clock enabled with pin low level NOTE If the timer is not active (TEN = 0 in TSCR), there is no divide-by-64 because the ÷64 clock is generated by the timer prescaler.
Page 481 Timer Module (TIM16B8CV2) Table 16-21. PAFLG Field Descriptions Field Description Pulse Accumulator Overﬂow Flag — Set when the 16-bit pulse accumulator overﬂows from 0xFFFF to 0x0000. PAOVF Clearing this bit requires writing a one to this bit in the PAFLG register while TEN bit of TSCR1 or PAEN bit of PACTL register is set to one.
Page 482 Timer Module (TIM16B8CV2) 16.3.2.18 Output Compare Pin Disconnect Register(OCPD) Module Base + 0x002C OCPD7 OCPD6 OCPD5 OCPD4 OCPD3 OCPD2 OCPD1 OCPD0 Reset Figure 16-28. Ouput Compare Pin Disconnect Register (OCPD) Read: Anytime Write: Anytime All bits reset to zero. Table 16-22. OCPD Field Description Field Description Output Compare Pin Disconnect Bits...
Page 483 Timer Module (TIM16B8CV2) Table 16-23. PTPSR Field Descriptions Field Description Precision Timer Prescaler Select Bits — These eight bits specify the division rate of the main Timer prescaler. PTPS[7:0] These are effective only when the PRNT bit of TSCR1 is set to 1. Table 16-24 shows some selection examples in this case.
Page 484 Timer Module (TIM16B8CV2) Bus Clock CLK[1:0] channel 7 output PR[2:1:0] PACLK compare PACLK/256 PACLK/65536 TCRE PRESCALER TCNT(hi):TCNT(lo) CLEAR COUNTER 16-BIT COUNTER INTERRUPT LOGIC CHANNEL 0 16-BIT COMPARATOR CH. 0 CAPTURE OM:OL0 IOC0 PIN IOC0 PIN TOV0 LOGIC CH. 0COMPARE EDGE EDG0A EDG0B DETECT...
Page 485 Timer Module (TIM16B8CV2) The prescaler divides the bus clock by a prescalar value. Prescaler select bits PR[2:0] of in timer system control register 2 (TSCR2) are set to deﬁne a prescalar value that generates a divide by 1, 2, 4, 8, 16, 32, 64 and 128 when the PRNT bit in TSCR1 is disabled.
Page 486 Timer Module (TIM16B8CV2) Note: in Figure 16-31,if PR[2:0] is equal to 0, one prescaler counter equal to one bus clock Figure 16-31. The TCNT cycle diagram under TCRE=1 condition prescaler 1 bus counter clock ----- TC7-1 TC7 event TC7 event 16.4.3.1 OC Channel Initialization Internal register whose output drives OCx can be programmed before timer drives OCx.
Page 487 Timer Module (TIM16B8CV2) NOTE The pulse accumulator counter can operate in event counter mode even when the timer enable bit, TEN, is clear. 16.4.6 Gated Time Accumulation Mode Setting the PAMOD bit conﬁgures the pulse accumulator for gated time accumulation operation. An active level on the PACNT input pin enables a divided-by-64 clock to drive the pulse accumulator.
Page 488 Timer Module (TIM16B8CV2) 16.6.1 Channel [7:0] Interrupt (C[7:0]F) This active high outputs will be asserted by the module to request a timer channel 7 – 0 interrupt to be serviced by the system controller. 16.6.2 Pulse Accumulator Input Interrupt (PAOVI) This active high output will be asserted by the module to request a timer pulse accumulator input interrupt to be serviced by the system controller.
Page 489: Chapter 17 Voltage Regulator (S12Vregl3V3V1)
Chapter 17 Voltage Regulator (S12VREGL3V3V1) Table 17-1. Revision History Table Rev. No. Date Sections Substantial Change(s) (Item No.) (Submitted By) Affected V01.02 09 Sep 2005 Updates for API external access and LVR ﬂags. V01.03 23 Sep 2005 VAE reset value is 1. V01.04 08 Jun 2007 Added temperature sensor to customer information...
Page 490 Voltage Regulator (S12VREGL3V3V1) 3. Shutdown mode Controlled by VREGEN (see device level speciﬁcation for connectivity of VREGEN). This mode is characterized by minimum power consumption. The regulator outputs are in a high- impedance state, only the POR feature is available, LVD, LVR and HTD are disabled. The API internal RC oscillator clock is not available.
Page 491 Voltage Regulator (S12VREGL3V3V1) Figure 17-1. VREG_3V3 Block Diagram VDDPLL REG3 VSSPLL VDDR VDDF REG2 VDDA VSSA REG1 VDDX VREGEN CTRL Rate Select Bus Clock LVD: Low Voltage Detect REG: Regulator Core LVR: Low Voltage Reset CTRL: Regulator Control POR: Power-on Reset API: Auto.
Page 492 Voltage Regulator (S12VREGL3V3V1) 17.2 External Signal Description Due to the nature of VREG_3V3 being a voltage regulator providing the chip internal power supply voltages, most signals are power supply signals connected to pads. Table 17-2 shows all signals of VREG_3V3 associated with pins. Table 17-2.
Page 493 Voltage Regulator (S12VREGL3V3V1) In Shutdown Mode an external supply driving VDD/VSS can replace the voltage regulator. 17.2.4 VDDF — Regulator Output2 (NVM Logic) Pins Signals VDDF/VSS are the secondary outputs of VREG_3V3 that provide the power supply for the NVM logic.
Page 494 Voltage Regulator (S12VREGL3V3V1) 17.3.1 Module Memory Map A summary of the registers associated with the VREG_3V3 sub-block is shown in Table 17-3. Detailed descriptions of the registers and bits are given in the subsections that follow Address Name Bit 7 Bit 0 HTDS 0x02F0...
Page 495 Voltage Regulator (S12VREGL3V3V1) 17.3.2 Register Descriptions This section describes all the VREG_3V3 registers and their individual bits. emperature 17.3.2.1 Control Register (VREGHTCL) The VREGHTCL register allows to conﬁgure the VREG temperature sense features. 0x02F0 HTDS VSEL HTEN HTIE HTIF Reset = Unimplemented or Reserved Table 17-4.
Page 496 Voltage Regulator (S12VREGL3V3V1) 17.3.2.2 Control Register (VREGCTRL) The VREGCTRL register allows the conﬁguration of the VREG_3V3 low-voltage detect features. 0x02F1 LVDS LVIE LVIF Reset = Unimplemented or Reserved Figure 17-2. Control Register (VREGCTRL) Table 17-5. VREGCTRL Field Descriptions Field Description Low-Voltage Detect Status Bit —...
Page 497 Voltage Regulator (S12VREGL3V3V1) 17.3.2.3 Autonomous Periodical Interrupt Control Register (VREGAPICL) The VREGAPICL register allows the conﬁguration of the VREG_3V3 autonomous periodical interrupt features. 0x02F2 APICLK APIES APIEA APIFE APIE APIF Reset = Unimplemented or Reserved Figure 17-3. Autonomous Periodical Interrupt Control Register (VREGAPICL) Table 17-6.
Page 498 Voltage Regulator (S12VREGL3V3V1) 17.3.2.4 Autonomous Periodical Interrupt Trimming Register (VREGAPITR) The VREGAPITR register allows to trim the API timeout period. 0x02F3 APITR5 APITR4 APITR3 APITR2 APITR1 APITR0 Reset 1. Reset value is either 0 or preset by factory. See Section 1 (Device Overview) for details. = Unimplemented or Reserved Figure 17-4.
Page 499 Voltage Regulator (S12VREGL3V3V1) 17.3.2.5 Autonomous Periodical Interrupt Rate High and Low Register (VREGAPIRH / VREGAPIRL) The VREGAPIRH and VREGAPIRL register allows the conﬁguration of the VREG_3V3 autonomous periodical interrupt rate. 0x02F4 APIR15 APIR14 APIR13 APIR12 APIR11 APIR10 APIR9 APIR8 Reset = Unimplemented or Reserved Figure 17-5.
Page 500 Voltage Regulator (S12VREGL3V3V1) Table 17-10. Selectable Autonomous Periodical Interrupt Periods APICLK APIR[15:0] Selected Period 0000 0.2 ms 0001 0.4 ms 0002 0.6 ms 0003 0.8 ms 0004 1.0 ms 0005 1.2 ms ..FFFD 13106.8 ms FFFE 13107.0 ms FFFF 13107.2 ms 0000...
Page 501: Reserved 06
Voltage Regulator (S12VREGL3V3V1) 17.3.2.6 Reserved 06 The Reserved 06 is reserved for test purposes. 0x02F6 Reset = Unimplemented or Reserved Figure 17-7. Reserved 06 17.3.2.7 High Temperature Trimming Register (VREGHTTR) The VREGHTTR register allows to trim the VREG temperature sense. Fiption 0x02F7 HTOEN...
Page 502 Voltage Regulator (S12VREGL3V3V1) 17.4 Functional Description 17.4.1 General Module VREG_3V3 is a voltage regulator, as depicted in Figure 17-1. The regulator functional elements are the regulator core (REG), a low-voltage detect module (LVD), a control block (CTRL), a power-on reset module (POR), and a low-voltage reset module (LVR)and a high temperature sensor (HTD). 17.4.2 Regulator Core (REG) Respectively its regulator core has three parallel, independent regulation loops (REG1,REG2 and REG3).
Page 503 Voltage Regulator (S12VREGL3V3V1) corresponding deassertion levels, signal LVR deasserts. The LVR function is available only in Full Performance Mode. 17.4.6 HTD - High Temperature Detect Subblock HTD is responsible for generating the high temperature interrupt (HTI). HTD monitors the die temperature T and continuously updates the status ﬂag HTDS.
Page 504 Voltage Regulator (S12VREGL3V3V1) It is possible to generate with the API a waveform at an external pin by enabling the API by setting APIFE and enabling the external access with setting APIEA. By setting APIES the waveform can be selected. If APIES is set, then at the external pin a clock is visible with 2 times the selected API Period (Table 17-10).
Page 505 Voltage Regulator (S12VREGL3V3V1) 17.4.11.1 Low-Voltage Interrupt (LVI) In FPM, VREG_3V3 monitors the input voltage V . Whenever V drops below level V LVIA, status bit LVDS is set to 1. On the other hand, LVDS is reset to 0 when V rises above level V .
Page 506 Voltage Regulator (S12VREGL3V3V1) S12XS Family Reference Manual, Rev. 1.13 Freescale Semiconductor...
Page 507: Chapter 18 256 Kbyte Flash Module (S12Xftmr256K1V1)
Chapter 18 256 KByte Flash Module (S12XFTMR256K1V1) Table 18-1. Revision History Revision Revision Sections Description of Changes Number Date Affected V01.04 03 Jan 2008 - Cosmetic changes V01.05 19 Dec 2008 18.1/18-507 - Clarify single bit fault correction for P-Flash phrase 18.4.2.4/18-542 - Add statement concerning code runaway when executing Read Once, 18.4.2.6/18-544...
Page 508 256 KByte Flash Module (S12XFTMR256K1V1) CAUTION A Flash word or phrase must be in the erased state before being programmed. Cumulative programming of bits within a Flash word or phrase is not allowed. The Flash memory may be read as bytes, aligned words, or misaligned words. Read access time is one bus cycle for bytes and aligned words, and two bus cycles for misaligned words.
Page 509 256 KByte Flash Module (S12XFTMR256K1V1) • Automated program and erase algorithm with verify and generation of ECC parity bits • Fast sector erase and phrase program operation • Flexible protection scheme to prevent accidental program or erase of P-Flash memory 18.1.2.2 D-Flash Features •...
Page 510 256 KByte Flash Module (S12XFTMR256K1V1) Flash Interface 16bit Command P-Flash Registers Interrupt internal 32Kx72 Request 16Kx72 16Kx72 sector 0 sector 0 Error Protection sector 1 sector 1 Interrupt Request sector 127 sector 127 Security Oscillator Clock (XTAL) Clock Divider FCLK Memory Controller D-Flash...
Page 511: Description
256 KByte Flash Module (S12XFTMR256K1V1) 18.3.1 Module Memory Map The S12X architecture places the P-Flash memory between global addresses 0x7C_0000 and 0x7F_FFFF as shown in Table 18-2. The P-Flash memory map is shown in Figure 18-2. Table 18-2. P-Flash Memory Addressing Size Global Address Description...
Page 512 256 KByte Flash Module (S12XFTMR256K1V1) P-Flash START = 0x7C_0000 Flash Protected/Unprotected Region 224 Kbytes 0x7F_8000 0x7F_8400 0x7F_8800 Flash Protected/Unprotected Lower Region 0x7F_9000 1, 2, 4, 8 Kbytes 0x7F_A000 Flash Protected/Unprotected Region 8 Kbytes (up to 29 Kbytes) 0x7F_C000 Flash Protected/Unprotected Higher Region 0x7F_E000 2, 4, 8, 16 Kbytes 0x7F_F000...
Page 513 256 KByte Flash Module (S12XFTMR256K1V1) Table 18-4. Program IFR Fields Global Address Size Field Description (PGMIFRON) (Bytes) 0x40_0000 – 0x40_0007 Device ID 0x40_0008 – 0x40_00E7 Reserved 0x40_00E8 – 0x40_00E9 Version ID 0x40_00EA – 0x40_00FF Reserved Program Once Field 0x40_0100 – 0x40_013F Refer to Section 18.4.2.6, “Program Once Command”...
Page 514 256 KByte Flash Module (S12XFTMR256K1V1) D-Flash START = 0x10_0000 D-Flash Memory 8 Kbytes D-Flash END = 0x10_1FFF 0x12_0000 D-Flash Nonvolatile Information Register (DFIFRON) 128 bytes 0x12_1000 0x12_2000 Memory Controller Scratch RAM (MGRAMON) 0x12_4000 768 bytes 0x12_E800 0x12_FFFF Figure 18-3. D-Flash and Memory Controller Resource Memory Map 18.3.2 Register Descriptions The Flash module contains a set of 20 control and status registers located between Flash module base +...
Page 515 256 KByte Flash Module (S12XFTMR256K1V1) Address & Name 0x0002 CCOBIX2 CCOBIX1 CCOBIX0 FCCOBIX 0x0003 ECCRIX2 ECCRIX1 ECCRIX0 FECCRIX 0x0004 CCIE IGNSF FDFD FSFD FCNFG 0x0005 DFDIE SFDIE FERCNFG MGBUSY RSVD MGSTAT1 MGSTAT0 0x0006 CCIF ACCERR FPVIOL FSTAT 0x0007 DFDIF SFDIF FERSTAT RNV6 0x0008...
Page 516 256 KByte Flash Module (S12XFTMR256K1V1) Address & Name 0x0010 FOPT 0x0011 FRSV2 0x0012 FRSV3 0x0013 FRSV4 = Unimplemented or Reserved Figure 18-4. FTMR256K1 Register Summary (continued) 18.3.2.1 Flash Clock Divider Register (FCLKDIV) The FCLKDIV register is used to control timed events in program and erase algorithms. Offset Module Base + 0x0000 FDIVLD FDIV[6:0]...
Page 517 256 KByte Flash Module (S12XFTMR256K1V1) CAUTION The FCLKDIV register should never be written while a Flash command is executing (CCIF=0). The FCLKDIV register is writable during the Flash reset sequence even though CCIF is clear. S12XS Family Reference Manual, Rev. 1.13 Freescale Semiconductor...
Page 518 256 KByte Flash Module (S12XFTMR256K1V1) Table 18-7. FDIV vs OSCCLK Frequency OSCCLK Frequency OSCCLK Frequency (MHz) (MHz) FDIV[6:0] FDIV[6:0] 1.60 2.10 0x01 33.60 34.65 0x20 2.40 3.15 0x02 34.65 35.70 0x21 3.20 4.20 0x03 35.70 36.75 0x22 4.20 5.25 0x04 36.75 37.80 0x23...
Page 519 256 KByte Flash Module (S12XFTMR256K1V1) 18.3.2.2 Flash Security Register (FSEC) The FSEC register holds all bits associated with the security of the MCU and Flash module. Offset Module Base + 0x0001 KEYEN[1:0] RNV[5:2] SEC[1:0] Reset = Unimplemented or Reserved Figure 18-6. Flash Security Register (FSEC) All bits in the FSEC register are readable but not writable.
Page 520 256 KByte Flash Module (S12XFTMR256K1V1) Preferred SEC state to set MCU to secured state. The security function in the Flash module is described in Section 18.5. 18.3.2.3 Flash CCOB Index Register (FCCOBIX) The FCCOBIX register is used to index the FCCOB register for Flash memory operations. Offset Module Base + 0x0002 CCOBIX[2:0] Reset...
Page 521 256 KByte Flash Module (S12XFTMR256K1V1) 18.3.2.5 Flash Conﬁguration Register (FCNFG) The FCNFG register enables the Flash command complete interrupt and forces ECC faults on Flash array read access from the CPU or XGATE. Offset Module Base + 0x0004 CCIE IGNSF FDFD FSFD Reset...
Page 522 256 KByte Flash Module (S12XFTMR256K1V1) Offset Module Base + 0x0005 DFDIE SFDIE Reset = Unimplemented or Reserved Figure 18-10. Flash Error Conﬁguration Register (FERCNFG) All assigned bits in the FERCNFG register are readable and writable. Table 18-14. FERCNFG Field Descriptions Field Description Double Bit Fault Detect Interrupt Enable —...
Page 523 256 KByte Flash Module (S12XFTMR256K1V1) Table 18-15. FSTAT Field Descriptions Field Description Command Complete Interrupt Flag — The CCIF ﬂag indicates that a Flash command has completed. The CCIF CCIF ﬂag is cleared by writing a 1 to CCIF to launch a command and CCIF will stay low until command completion or command violation.
Page 524 256 KByte Flash Module (S12XFTMR256K1V1) Table 18-16. FERSTAT Field Descriptions Field Description Double Bit Fault Detect Interrupt Flag — The setting of the DFDIF ﬂag indicates that a double bit fault was DFDIF detected in the stored parity and data bits during a Flash array read operation or that a Flash array read operation was attempted on a Flash block that was under a Flash command operation.
Page 525 256 KByte Flash Module (S12XFTMR256K1V1) Table 18-17. FPROT Field Descriptions Field Description Flash Protection Operation Enable — The FPOPEN bit determines the protection function for program or FPOPEN erase operations as shown in Table 18-18 for the P-Flash block. 0 When FPOPEN is clear, the FPHDIS and FPLDIS bits deﬁne unprotected address ranges as speciﬁed by the corresponding FPHS and FPLS bits 1 When FPOPEN is set, the FPHDIS and FPLDIS bits enable protection for the address range speciﬁed by the corresponding FPHS and FPLS bits...
Page 526 256 KByte Flash Module (S12XFTMR256K1V1) Table 18-20. P-Flash Protection Lower Address Range FPLS[1:0] Global Address Range Protected Size 0x7F_8000–0x7F_83FF 1 Kbyte 0x7F_8000–0x7F_87FF 2 Kbytes 0x7F_8000–0x7F_8FFF 4 Kbytes 0x7F_8000–0x7F_9FFF 8 Kbytes All possible P-Flash protection scenarios are shown in Figure 18-14. Although the protection scheme is loaded from the Flash memory at global address 0x7F_FF0C during the reset sequence, it can be changed by the user.
Page 527 256 KByte Flash Module (S12XFTMR256K1V1) FPHDIS = 1 FPHDIS = 1 FPHDIS = 0 FPHDIS = 0 FPLDIS = 1 FPLDIS = 0 FPLDIS = 1 FPLDIS = 0 Scenario FLASH START 0x7F_8000 0x7F_FFFF Scenario FLASH START 0x7F_8000 0x7F_FFFF Protected region with size Unprotected region defined by FPLS Protected region...
Page 528 256 KByte Flash Module (S12XFTMR256K1V1) 18.3.2.9.1 P-Flash Protection Restrictions The general guideline is that P-Flash protection can only be added and not removed. Table 18-21 specifies all valid transitions between P-Flash protection scenarios. Any attempt to write an invalid scenario to the FPROT register will be ignored.
Page 529 256 KByte Flash Module (S12XFTMR256K1V1) P-Flash phrase containing the D-Flash protection byte during the reset sequence, the DPOPEN bit will be cleared and DPS bits will be set to leave the D-Flash memory fully protected. Trying to alter data in any protected area in the D-Flash memory will result in a protection violation error and the FPVIOL bit will be set in the FSTAT register.
Page 530 256 KByte Flash Module (S12XFTMR256K1V1) Table 18-23. D-Flash Protection Address Range DPS[4:0] Global Address Range Protected Size 1_0110 0x10_0000 – 0x10_16FF 5888 bytes 1_0111 0x10_0000 – 0x10_17FF 6144 bytes 1_1000 0x10_0000 – 0x10_18FF 6400 bytes 1_1001 0x10_0000 – 0x10_19FF 6656 bytes 1_1010 0x10_0000 –...
Page 531 256 KByte Flash Module (S12XFTMR256K1V1) (as evidenced by the Memory Controller returning CCIF to 1). Some commands return information to the FCCOB register array. The generic format for the FCCOB parameter fields in NVM command mode is shown in Table 18-24.
Page 532 256 KByte Flash Module (S12XFTMR256K1V1) 18.3.2.13 Flash Reserved1 Register (FRSV1) This Flash register is reserved for factory testing. Offset Module Base + 0x000D Reset = Unimplemented or Reserved Figure 18-19. Flash Reserved1 Register (FRSV1) All bits in the FRSV1 register read 0 and are not writable. 18.3.2.14 Flash ECC Error Results Register (FECCR) The FECCR registers contain the result of a detected ECC fault for both single bit and double bit faults.
Page 533: Bit
256 KByte Flash Module (S12XFTMR256K1V1) Table 18-25. FECCR Index Settings ECCRIX[2:0] FECCR Register Content Bits [15:8] Bit[7] Bits[6:0] Parity bits read from Global address Flash block [22:16] Global address [15:0] Data 0 [15:0] Data 1 [15:0] (P-Flash only) Data 2 [15:0] (P-Flash only) Data 3 [15:0] (P-Flash only) Not used, returns 0x0000 when read Not used, returns 0x0000 when read...
Page 534 256 KByte Flash Module (S12XFTMR256K1V1) During the reset sequence, the FOPT register is loaded from the Flash nonvolatile byte in the Flash configuration field at global address 0x7F_FF0E located in P-Flash memory (see Table 18-3) as indicated by reset condition F in Figure 18-22.
Page 535 256 KByte Flash Module (S12XFTMR256K1V1) Offset Module Base + 0x0013 Reset = Unimplemented or Reserved Figure 18-25. Flash Reserved4 Register (FRSV4) All bits in the FRSV4 register read 0 and are not writable. 18.4 Functional Description 18.4.1 Flash Command Operations Flash command operations are used to modify Flash memory contents.
Page 536 256 KByte Flash Module (S12XFTMR256K1V1) 18.4.1.2 Command Write Sequence The Memory Controller will launch all valid Flash commands entered using a command write sequence. Before launching a command, the ACCERR and FPVIOL bits in the FSTAT register must be clear (see Section 18.3.2.7) and the CCIF flag should be tested to determine the status of the current command write sequence.
Page 537 256 KByte Flash Module (S12XFTMR256K1V1) START Read: FCLKDIV register Clock Register FDIVLD Written Set? Check Note: FCLKDIV must be set after Write: FCLKDIV register each reset Read: FSTAT register FCCOB CCIF Availability Check Set? Results from previous Command ACCERR/ Access Error and Write: FSTAT register FPVIOL Protection Violation...
Page 538 256 KByte Flash Module (S12XFTMR256K1V1) 18.4.1.3 Valid Flash Module Commands Table 18-28. Flash Commands by Mode Unsecured Secured FCMD Command ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ 0x01 Erase Verify All Blocks ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗...
Page 539 256 KByte Flash Module (S12XFTMR256K1V1) Table 18-29. P-Flash Commands FCMD Command Function on P-Flash Memory Erase Verify All Verify that all P-Flash (and D-Flash) blocks are erased. 0x01 Blocks 0x02 Erase Verify Block Verify that a P-Flash block is erased. Erase Verify Verify that a given number of words starting at the address provided are erased.
Page 540 256 KByte Flash Module (S12XFTMR256K1V1) Table 18-30. D-Flash Commands FCMD Command Function on D-Flash Memory Supports a method of releasing MCU security by erasing all D-Flash (and P-Flash) blocks 0x0B Unsecure Flash and verifying that all D-Flash (and P-Flash) blocks are erased. Set User Margin Speciﬁes a user margin read level for the D-Flash block.
Page 541 256 KByte Flash Module (S12XFTMR256K1V1) Upon clearing CCIF to launch the Erase Verify All Blocks command, the Memory Controller will verify that the entire Flash memory space is erased. The CCIF ﬂag will set after the Erase Verify All Blocks operation has completed.
Page 542 256 KByte Flash Module (S12XFTMR256K1V1) Table 18-35. Erase Verify P-Flash Section Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters Global address [22:16] of 0x03 a P-Flash block Global address [15:0] of the ﬁrst phrase to be veriﬁed Number of phrases to be veriﬁed Upon clearing CCIF to launch the Erase Verify P-Flash Section command, the Memory Controller will verify the selected section of Flash memory is erased.
Page 543 256 KByte Flash Module (S12XFTMR256K1V1) phrase index values for the Read Once command range from 0x0000 to 0x0007. During execution of the Read Once command, any attempt to read addresses within P-Flash block will return invalid data. Table 18-38. Read Once Command Error Handling Register Error Bit Error Condition...
Page 544 256 KByte Flash Module (S12XFTMR256K1V1) Table 18-40. Program P-Flash Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 101 at command launch Set if command not available in current mode (see Table 18-28) ACCERR Set if an invalid global address [22:0] is supplied Set if a misaligned phrase address is supplied (global address [2:0] != 000) FSTAT FPVIOL...
Page 545 256 KByte Flash Module (S12XFTMR256K1V1) Table 18-42. Program Once Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 101 at command launch Set if command not available in current mode (see Table 18-28) ACCERR Set if an invalid phrase index is supplied Set if the requested phrase has already been programmed FSTAT FPVIOL...
Page 546 256 KByte Flash Module (S12XFTMR256K1V1) Table 18-45. Erase Flash Block Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters Global address [22:16] to 0x09 identify Flash block Global address [15:0] in Flash block to be erased Upon clearing CCIF to launch the Erase Flash Block command, the Memory Controller will erase the selected Flash block and verify that it is erased.
Page 547 256 KByte Flash Module (S12XFTMR256K1V1) Table 18-48. Erase P-Flash Sector Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch Set if command not available in current mode (see Table 18-28) ACCERR Set if an invalid global address [22:16] is supplied Set if a misaligned phrase address is supplied (global address [2:0] != 000) FSTAT FPVIOL...
Page 548 256 KByte Flash Module (S12XFTMR256K1V1) Table 18-3). The Verify Backdoor Access Key command must not be executed from the Flash block containing the backdoor comparison key to avoid code runaway. Table 18-51. Verify Backdoor Access Key Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 0x0C Not required...
Page 549 256 KByte Flash Module (S12XFTMR256K1V1) Upon clearing CCIF to launch the Set User Margin Level command, the Memory Controller will set the user margin level for the targeted block and then set the CCIF ﬂag. Valid margin level settings for the Set User Margin Level command are deﬁned in Table 18-54.
Page 550 256 KByte Flash Module (S12XFTMR256K1V1) Upon clearing CCIF to launch the Set Field Margin Level command, the Memory Controller will set the ﬁeld margin level for the targeted block and then set the CCIF ﬂag. Valid margin level settings for the Set Field Margin Level command are deﬁned in Table 18-57.
Page 551 256 KByte Flash Module (S12XFTMR256K1V1) Table 18-59. Erase Verify D-Flash Section Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters Global address [22:16] to 0x10 identify the D-Flash block Global address [15:0] of the ﬁrst word to be veriﬁed Number of words to be veriﬁed Upon clearing CCIF to launch the Erase Verify D-Flash Section command, the Memory Controller will verify the selected section of D-Flash memory is erased.
Page 552 256 KByte Flash Module (S12XFTMR256K1V1) Table 18-61. Program D-Flash Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters Word 3 program value, if desired Upon clearing CCIF to launch the Program D-Flash command, the user-supplied words will be transferred to the Memory Controller and be programmed if the area is unprotected. The CCOBIX index value at Program D-Flash command launch determines how many words will be programmed in the D-Flash block.
Page 553 256 KByte Flash Module (S12XFTMR256K1V1) Table 18-64. Erase D-Flash Sector Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch Set if command not available in current mode (see Table 18-28) ACCERR Set if an invalid global address [22:0] is supplied Set if a misaligned word address is supplied (global address [0] != 0) FSTAT FPVIOL...
Page 554 256 KByte Flash Module (S12XFTMR256K1V1) CCIE Flash Command Interrupt Request CCIF DFDIE DFDIF Flash Error Interrupt Request SFDIE SFDIF Figure 18-27. Flash Module Interrupts Implementation 18.4.4 Wait Mode The Flash module is not affected if the MCU enters wait mode. The Flash module can recover the MCU from wait via the CCIF interrupt (see Section 18.4.3, “Interrupts”).
Page 555 256 KByte Flash Module (S12XFTMR256K1V1) keys stored in the Flash memory via the Memory Controller. If the keys presented in the Verify Backdoor Access Key command match the backdoor keys stored in the Flash memory, the SEC bits in the FSEC register (see Table 18-10) will be changed to unsecure the MCU.
Page 556 256 KByte Flash Module (S12XFTMR256K1V1) erased the MCU will be unsecured. All BDM commands will be enabled and the Flash security byte may be programmed to the unsecure state by the following method: • Send BDM commands to execute a ‘Program P-Flash’ command sequence to program the Flash security byte to the unsecured state and reset the MCU.
Page 557: Chapter 19 128 Kbyte Flash Module (S12Xftmr128K1V1)
Chapter 19 128 KByte Flash Module (S12XFTMR128K1V1) Table 19-1. Revision History Revision Revision Sections Description of Changes Number Date Affected V01.04 03 Jan 2008 - Cosmetic changes V01.05 19 Dec 2008 19.1/19-557 - Clarify single bit fault correction for P-Flash phrase 19.4.2.4/19-592 - Add statement concerning code runaway when executing Read Once, 19.4.2.6/19-594...
Page 558 128 KByte Flash Module (S12XFTMR128K1V1) CAUTION A Flash word or phrase must be in the erased state before being programmed. Cumulative programming of bits within a Flash word or phrase is not allowed. The Flash memory may be read as bytes, aligned words, or misaligned words. Read access time is one bus cycle for bytes and aligned words, and two bus cycles for misaligned words.
Page 559 128 KByte Flash Module (S12XFTMR128K1V1) • Automated program and erase algorithm with verify and generation of ECC parity bits • Fast sector erase and phrase program operation • Flexible protection scheme to prevent accidental program or erase of P-Flash memory 19.1.2.2 D-Flash Features •...
Page 560 128 KByte Flash Module (S12XFTMR128K1V1) Flash Interface 16bit Command Registers Interrupt internal P-Flash Request 16Kx72 sector 0 Error Protection sector 1 Interrupt Request sector 127 Security Oscillator Clock (XTAL) Clock Divider FCLK Memory Controller D-Flash 4Kx22 Scratch RAM sector 0 384x16bits sector 1 sector 31...
Page 561 128 KByte Flash Module (S12XFTMR128K1V1) 19.3.1 Module Memory Map The S12X architecture places the P-Flash memory between global addresses 0x7E_0000 and 0x7F_FFFF as shown in Table 19-2. The P-Flash memory map is shown in Figure 19-2. Table 19-2. P-Flash Memory Addressing Size Global Address Description...
Page 562 128 KByte Flash Module (S12XFTMR128K1V1) P-Flash START = 0x7E_0000 Flash Protected/Unprotected Region 96 Kbytes 0x7F_8000 0x7F_8400 0x7F_8800 Flash Protected/Unprotected Lower Region 0x7F_9000 1, 2, 4, 8 Kbytes 0x7F_A000 Flash Protected/Unprotected Region 8 Kbytes (up to 29 Kbytes) 0x7F_C000 Flash Protected/Unprotected Higher Region 0x7F_E000 2, 4, 8, 16 Kbytes 0x7F_F000...
Page 563 128 KByte Flash Module (S12XFTMR128K1V1) Table 19-4. Program IFR Fields Global Address Size Field Description (PGMIFRON) (Bytes) 0x40_0000 – 0x40_0007 Device ID 0x40_0008 – 0x40_00E7 Reserved 0x40_00E8 – 0x40_00E9 Version ID 0x40_00EA – 0x40_00FF Reserved Program Once Field 0x40_0100 – 0x40_013F Refer to Section 19.4.2.6, “Program Once Command”...
Page 564 128 KByte Flash Module (S12XFTMR128K1V1) D-Flash START = 0x10_0000 D-Flash Memory 8 Kbytes D-Flash END = 0x10_1FFF 0x12_0000 D-Flash Nonvolatile Information Register (DFIFRON) 128 bytes 0x12_1000 0x12_2000 Memory Controller Scratch RAM (MGRAMON) 0x12_4000 768 bytes 0x12_E800 0x12_FFFF Figure 19-3. D-Flash and Memory Controller Resource Memory Map 19.3.2 Register Descriptions The Flash module contains a set of 20 control and status registers located between Flash module base +...
Page 565 128 KByte Flash Module (S12XFTMR128K1V1) Address & Name 0x0002 CCOBIX2 CCOBIX1 CCOBIX0 FCCOBIX 0x0003 ECCRIX2 ECCRIX1 ECCRIX0 FECCRIX 0x0004 CCIE IGNSF FDFD FSFD FCNFG 0x0005 DFDIE SFDIE FERCNFG MGBUSY RSVD MGSTAT1 MGSTAT0 0x0006 CCIF ACCERR FPVIOL FSTAT 0x0007 DFDIF SFDIF FERSTAT RNV6 0x0008...
Page 566 128 KByte Flash Module (S12XFTMR128K1V1) Address & Name 0x0010 FOPT 0x0011 FRSV2 0x0012 FRSV3 0x0013 FRSV4 = Unimplemented or Reserved Figure 19-4. FTMR128K1 Register Summary (continued) 19.3.2.1 Flash Clock Divider Register (FCLKDIV) The FCLKDIV register is used to control timed events in program and erase algorithms. Offset Module Base + 0x0000 FDIVLD FDIV[6:0]...
Page 567 128 KByte Flash Module (S12XFTMR128K1V1) CAUTION The FCLKDIV register should never be written while a Flash command is executing (CCIF=0). The FCLKDIV register is writable during the Flash reset sequence even though CCIF is clear. S12XS Family Reference Manual, Rev. 1.13 Freescale Semiconductor...
Page 568 128 KByte Flash Module (S12XFTMR128K1V1) Table 19-7. FDIV vs OSCCLK Frequency OSCCLK Frequency OSCCLK Frequency (MHz) (MHz) FDIV[6:0] FDIV[6:0] 1.60 2.10 0x01 33.60 34.65 0x20 2.40 3.15 0x02 34.65 35.70 0x21 3.20 4.20 0x03 35.70 36.75 0x22 4.20 5.25 0x04 36.75 37.80 0x23...
Page 569 128 KByte Flash Module (S12XFTMR128K1V1) 19.3.2.2 Flash Security Register (FSEC) The FSEC register holds all bits associated with the security of the MCU and Flash module. Offset Module Base + 0x0001 KEYEN[1:0] RNV[5:2] SEC[1:0] Reset = Unimplemented or Reserved Figure 19-6. Flash Security Register (FSEC) All bits in the FSEC register are readable but not writable.
Page 570 128 KByte Flash Module (S12XFTMR128K1V1) Preferred SEC state to set MCU to secured state. The security function in the Flash module is described in Section 19.5. 19.3.2.3 Flash CCOB Index Register (FCCOBIX) The FCCOBIX register is used to index the FCCOB register for Flash memory operations. Offset Module Base + 0x0002 CCOBIX[2:0] Reset...
Page 571 128 KByte Flash Module (S12XFTMR128K1V1) 19.3.2.5 Flash Conﬁguration Register (FCNFG) The FCNFG register enables the Flash command complete interrupt and forces ECC faults on Flash array read access from the CPU or XGATE. Offset Module Base + 0x0004 CCIE IGNSF FDFD FSFD Reset...
Page 572 128 KByte Flash Module (S12XFTMR128K1V1) Offset Module Base + 0x0005 DFDIE SFDIE Reset = Unimplemented or Reserved Figure 19-10. Flash Error Conﬁguration Register (FERCNFG) All assigned bits in the FERCNFG register are readable and writable. Table 19-14. FERCNFG Field Descriptions Field Description Double Bit Fault Detect Interrupt Enable —...
Page 573 128 KByte Flash Module (S12XFTMR128K1V1) Table 19-15. FSTAT Field Descriptions Field Description Command Complete Interrupt Flag — The CCIF ﬂag indicates that a Flash command has completed. The CCIF CCIF ﬂag is cleared by writing a 1 to CCIF to launch a command and CCIF will stay low until command completion or command violation.
Page 574 128 KByte Flash Module (S12XFTMR128K1V1) Table 19-16. FERSTAT Field Descriptions Field Description Double Bit Fault Detect Interrupt Flag — The setting of the DFDIF ﬂag indicates that a double bit fault was DFDIF detected in the stored parity and data bits during a Flash array read operation or that a Flash array read operation was attempted on a Flash block that was under a Flash command operation.
Page 575 128 KByte Flash Module (S12XFTMR128K1V1) Table 19-17. FPROT Field Descriptions Field Description Flash Protection Operation Enable — The FPOPEN bit determines the protection function for program or FPOPEN erase operations as shown in Table 19-18 for the P-Flash block. 0 When FPOPEN is clear, the FPHDIS and FPLDIS bits deﬁne unprotected address ranges as speciﬁed by the corresponding FPHS and FPLS bits 1 When FPOPEN is set, the FPHDIS and FPLDIS bits enable protection for the address range speciﬁed by the corresponding FPHS and FPLS bits...
Page 576 128 KByte Flash Module (S12XFTMR128K1V1) Table 19-20. P-Flash Protection Lower Address Range FPLS[1:0] Global Address Range Protected Size 0x7F_8000–0x7F_83FF 1 Kbyte 0x7F_8000–0x7F_87FF 2 Kbytes 0x7F_8000–0x7F_8FFF 4 Kbytes 0x7F_8000–0x7F_9FFF 8 Kbytes All possible P-Flash protection scenarios are shown in Figure 19-14. Although the protection scheme is loaded from the Flash memory at global address 0x7F_FF0C during the reset sequence, it can be changed by the user.
Page 577 128 KByte Flash Module (S12XFTMR128K1V1) FPHDIS = 1 FPHDIS = 1 FPHDIS = 0 FPHDIS = 0 FPLDIS = 1 FPLDIS = 0 FPLDIS = 1 FPLDIS = 0 Scenario FLASH START 0x7F_8000 0x7F_FFFF Scenario FLASH START 0x7F_8000 0x7F_FFFF Protected region with size Unprotected region defined by FPLS Protected region...
Page 578 128 KByte Flash Module (S12XFTMR128K1V1) 19.3.2.9.1 P-Flash Protection Restrictions The general guideline is that P-Flash protection can only be added and not removed. Table 19-21 specifies all valid transitions between P-Flash protection scenarios. Any attempt to write an invalid scenario to the FPROT register will be ignored.
Page 579 128 KByte Flash Module (S12XFTMR128K1V1) P-Flash phrase containing the D-Flash protection byte during the reset sequence, the DPOPEN bit will be cleared and DPS bits will be set to leave the D-Flash memory fully protected. Trying to alter data in any protected area in the D-Flash memory will result in a protection violation error and the FPVIOL bit will be set in the FSTAT register.
Page 580 128 KByte Flash Module (S12XFTMR128K1V1) Table 19-23. D-Flash Protection Address Range DPS[4:0] Global Address Range Protected Size 1_0110 0x10_0000 – 0x10_16FF 5888 bytes 1_0111 0x10_0000 – 0x10_17FF 6144 bytes 1_1000 0x10_0000 – 0x10_18FF 6400 bytes 1_1001 0x10_0000 – 0x10_19FF 6656 bytes 1_1010 0x10_0000 –...
Page 581 128 KByte Flash Module (S12XFTMR128K1V1) (as evidenced by the Memory Controller returning CCIF to 1). Some commands return information to the FCCOB register array. The generic format for the FCCOB parameter fields in NVM command mode is shown in Table 19-24.
Page 582 128 KByte Flash Module (S12XFTMR128K1V1) 19.3.2.13 Flash Reserved1 Register (FRSV1) This Flash register is reserved for factory testing. Offset Module Base + 0x000D Reset = Unimplemented or Reserved Figure 19-19. Flash Reserved1 Register (FRSV1) All bits in the FRSV1 register read 0 and are not writable. 19.3.2.14 Flash ECC Error Results Register (FECCR) The FECCR registers contain the result of a detected ECC fault for both single bit and double bit faults.
Page 583: Bit
128 KByte Flash Module (S12XFTMR128K1V1) Table 19-25. FECCR Index Settings ECCRIX[2:0] FECCR Register Content Bits [15:8] Bit[7] Bits[6:0] Parity bits read from Global address Flash block [22:16] Global address [15:0] Data 0 [15:0] Data 1 [15:0] (P-Flash only) Data 2 [15:0] (P-Flash only) Data 3 [15:0] (P-Flash only) Not used, returns 0x0000 when read Not used, returns 0x0000 when read...
Page 584 128 KByte Flash Module (S12XFTMR128K1V1) During the reset sequence, the FOPT register is loaded from the Flash nonvolatile byte in the Flash configuration field at global address 0x7F_FF0E located in P-Flash memory (see Table 19-3) as indicated by reset condition F in Figure 19-22.
Page 585 128 KByte Flash Module (S12XFTMR128K1V1) Offset Module Base + 0x0013 Reset = Unimplemented or Reserved Figure 19-25. Flash Reserved4 Register (FRSV4) All bits in the FRSV4 register read 0 and are not writable. 19.4 Functional Description 19.4.1 Flash Command Operations Flash command operations are used to modify Flash memory contents.
Page 586 128 KByte Flash Module (S12XFTMR128K1V1) 19.4.1.2 Command Write Sequence The Memory Controller will launch all valid Flash commands entered using a command write sequence. Before launching a command, the ACCERR and FPVIOL bits in the FSTAT register must be clear (see Section 19.3.2.7) and the CCIF flag should be tested to determine the status of the current command write sequence.
Page 587 128 KByte Flash Module (S12XFTMR128K1V1) START Read: FCLKDIV register Clock Register FDIVLD Written Set? Check Note: FCLKDIV must be set after Write: FCLKDIV register each reset Read: FSTAT register FCCOB CCIF Availability Check Set? Results from previous Command ACCERR/ Access Error and Write: FSTAT register FPVIOL Protection Violation...
Page 588 128 KByte Flash Module (S12XFTMR128K1V1) 19.4.1.3 Valid Flash Module Commands Table 19-28. Flash Commands by Mode Unsecured Secured FCMD Command ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ 0x01 Erase Verify All Blocks ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗...
Page 589 128 KByte Flash Module (S12XFTMR128K1V1) Table 19-29. P-Flash Commands FCMD Command Function on P-Flash Memory Erase Verify All Verify that all P-Flash (and D-Flash) blocks are erased. 0x01 Blocks 0x02 Erase Verify Block Verify that a P-Flash block is erased. Erase Verify Verify that a given number of words starting at the address provided are erased.
Page 590 128 KByte Flash Module (S12XFTMR128K1V1) Table 19-30. D-Flash Commands FCMD Command Function on D-Flash Memory Supports a method of releasing MCU security by erasing all D-Flash (and P-Flash) blocks 0x0B Unsecure Flash and verifying that all D-Flash (and P-Flash) blocks are erased. Set User Margin Speciﬁes a user margin read level for the D-Flash block.
Page 591 128 KByte Flash Module (S12XFTMR128K1V1) Upon clearing CCIF to launch the Erase Verify All Blocks command, the Memory Controller will verify that the entire Flash memory space is erased. The CCIF ﬂag will set after the Erase Verify All Blocks operation has completed.
Page 592 128 KByte Flash Module (S12XFTMR128K1V1) Table 19-35. Erase Verify P-Flash Section Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters Global address [22:16] of 0x03 a P-Flash block Global address [15:0] of the ﬁrst phrase to be veriﬁed Number of phrases to be veriﬁed Upon clearing CCIF to launch the Erase Verify P-Flash Section command, the Memory Controller will verify the selected section of Flash memory is erased.
Page 593 128 KByte Flash Module (S12XFTMR128K1V1) phrase index values for the Read Once command range from 0x0000 to 0x0007. During execution of the Read Once command, any attempt to read addresses within P-Flash block will return invalid data. Table 19-38. Read Once Command Error Handling Register Error Bit Error Condition...
Page 594 128 KByte Flash Module (S12XFTMR128K1V1) Table 19-40. Program P-Flash Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 101 at command launch Set if command not available in current mode (see Table 19-28) ACCERR Set if an invalid global address [22:0] is supplied Set if a misaligned phrase address is supplied (global address [2:0] != 000) FSTAT FPVIOL...
Page 595 128 KByte Flash Module (S12XFTMR128K1V1) Table 19-42. Program Once Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 101 at command launch Set if command not available in current mode (see Table 19-28) ACCERR Set if an invalid phrase index is supplied Set if the requested phrase has already been programmed FSTAT FPVIOL...
Page 596 128 KByte Flash Module (S12XFTMR128K1V1) Table 19-45. Erase Flash Block Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters Global address [22:16] to 0x09 identify Flash block Global address [15:0] in Flash block to be erased Upon clearing CCIF to launch the Erase Flash Block command, the Memory Controller will erase the selected Flash block and verify that it is erased.
Page 597 128 KByte Flash Module (S12XFTMR128K1V1) Table 19-48. Erase P-Flash Sector Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch Set if command not available in current mode (see Table 19-28) ACCERR Set if an invalid global address [22:16] is supplied Set if a misaligned phrase address is supplied (global address [2:0] != 000) FSTAT FPVIOL...
Page 598 128 KByte Flash Module (S12XFTMR128K1V1) Table 19-3). The Verify Backdoor Access Key command must not be executed from the Flash block containing the backdoor comparison key to avoid code runaway. Table 19-51. Verify Backdoor Access Key Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 0x0C Not required...
Page 599 128 KByte Flash Module (S12XFTMR128K1V1) Upon clearing CCIF to launch the Set User Margin Level command, the Memory Controller will set the user margin level for the targeted block and then set the CCIF ﬂag. Valid margin level settings for the Set User Margin Level command are deﬁned in Table 19-54.
Page 600 128 KByte Flash Module (S12XFTMR128K1V1) Upon clearing CCIF to launch the Set Field Margin Level command, the Memory Controller will set the ﬁeld margin level for the targeted block and then set the CCIF ﬂag. Valid margin level settings for the Set Field Margin Level command are deﬁned in Table 19-57.
Page 601 128 KByte Flash Module (S12XFTMR128K1V1) Table 19-59. Erase Verify D-Flash Section Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters Global address [22:16] to 0x10 identify the D-Flash block Global address [15:0] of the ﬁrst word to be veriﬁed Number of words to be veriﬁed Upon clearing CCIF to launch the Erase Verify D-Flash Section command, the Memory Controller will verify the selected section of D-Flash memory is erased.
Page 602 128 KByte Flash Module (S12XFTMR128K1V1) Table 19-61. Program D-Flash Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters Word 3 program value, if desired Upon clearing CCIF to launch the Program D-Flash command, the user-supplied words will be transferred to the Memory Controller and be programmed if the area is unprotected. The CCOBIX index value at Program D-Flash command launch determines how many words will be programmed in the D-Flash block.
Page 603 128 KByte Flash Module (S12XFTMR128K1V1) Table 19-64. Erase D-Flash Sector Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch Set if command not available in current mode (see Table 19-28) ACCERR Set if an invalid global address [22:0] is supplied Set if a misaligned word address is supplied (global address [0] != 0) FSTAT FPVIOL...
Page 604 128 KByte Flash Module (S12XFTMR128K1V1) CCIE Flash Command Interrupt Request CCIF DFDIE DFDIF Flash Error Interrupt Request SFDIE SFDIF Figure 19-27. Flash Module Interrupts Implementation 19.4.4 Wait Mode The Flash module is not affected if the MCU enters wait mode. The Flash module can recover the MCU from wait via the CCIF interrupt (see Section 19.4.3, “Interrupts”).
Page 605 128 KByte Flash Module (S12XFTMR128K1V1) keys stored in the Flash memory via the Memory Controller. If the keys presented in the Verify Backdoor Access Key command match the backdoor keys stored in the Flash memory, the SEC bits in the FSEC register (see Table 19-10) will be changed to unsecure the MCU.
Page 606 128 KByte Flash Module (S12XFTMR128K1V1) erased the MCU will be unsecured. All BDM commands will be enabled and the Flash security byte may be programmed to the unsecure state by the following method: • Send BDM commands to execute a ‘Program P-Flash’ command sequence to program the Flash security byte to the unsecured state and reset the MCU.
Page 607: Chapter 20 64 Kbyte Flash Module (S12Xftmr64K1V1)
Chapter 20 64 KByte Flash Module (S12XFTMR64K1V1) Table 20-1. Revision History Revision Revision Sections Description of Changes Number Date Affected V01.04 03 Jan 2008 - Cosmetic changes V01.05 19 Dec 2008 20.1/20-607 - Clarify single bit fault correction for P-Flash phrase 20.4.2.4/20-642 - Add statement concerning code runaway when executing Read Once, 20.4.2.6/20-644...
Page 608 64 KByte Flash Module (S12XFTMR64K1V1) CAUTION A Flash word or phrase must be in the erased state before being programmed. Cumulative programming of bits within a Flash word or phrase is not allowed. The Flash memory may be read as bytes, aligned words, or misaligned words. Read access time is one bus cycle for bytes and aligned words, and two bus cycles for misaligned words.
Page 609 64 KByte Flash Module (S12XFTMR64K1V1) • Automated program and erase algorithm with verify and generation of ECC parity bits • Fast sector erase and phrase program operation • Flexible protection scheme to prevent accidental program or erase of P-Flash memory 20.1.2.2 D-Flash Features •...
Page 610 64 KByte Flash Module (S12XFTMR64K1V1) 20.1.3 Block Diagram The block diagram of the Flash module is shown in Figure 20-1. Figure 20-1. FTMR64K1 Block Diagram Flash Interface 16bit Command Registers Interrupt internal P-Flash Request 8Kx72 sector 0 Error Protection sector 1 Interrupt Request sector 63...
Page 611 64 KByte Flash Module (S12XFTMR64K1V1) 20.3 Memory Map and Registers This section describes the memory map and registers for the Flash module. Read data from unimplemented memory space in the Flash module is undeﬁned. Write access to unimplemented or reserved memory space in the Flash module will be ignored by the Flash module.
Page 612 64 KByte Flash Module (S12XFTMR64K1V1) 0x7FF08 - 0x7F_FF0F form a Flash phrase and must be programmed in a single command write sequence. Each byte in the 0x7F_FF08 - 0x7F_FF0B reserved ﬁeld should be programmed to 0xFF. S12XS Family Reference Manual, Rev. 1.13 Freescale Semiconductor...
Page 613 64 KByte Flash Module (S12XFTMR64K1V1) P-Flash START = 0x7F_0000 Flash Protected/Unprotected Region 32 Kbytes 0x7F_8000 0x7F_8400 0x7F_8800 Flash Protected/Unprotected Lower Region 0x7F_9000 1, 2, 4, 8 Kbytes 0x7F_A000 Flash Protected/Unprotected Region 8 Kbytes (up to 29 Kbytes) 0x7F_C000 Flash Protected/Unprotected Higher Region 0x7F_E000 2, 4, 8, 16 Kbytes 0x7F_F000...
Page 614 64 KByte Flash Module (S12XFTMR64K1V1) Table 20-4. Program IFR Fields Global Address Size Field Description (PGMIFRON) (Bytes) 0x40_0000 – 0x40_0007 Device ID 0x40_0008 – 0x40_00E7 Reserved 0x40_00E8 – 0x40_00E9 Version ID 0x40_00EA – 0x40_00FF Reserved Program Once Field 0x40_0100 – 0x40_013F Refer to Section 20.4.2.6, “Program Once Command”...
Page 615 64 KByte Flash Module (S12XFTMR64K1V1) D-Flash START = 0x10_0000 D-Flash Memory 4 Kbytes D-Flash END = 0x10_0FFF 0x12_0000 D-Flash Nonvolatile Information Register (DFIFRON) 128 bytes 0x12_1000 0x12_2000 Memory Controller Scratch RAM (MGRAMON) 0x12_4000 768 bytes 0x12_E800 0x12_FFFF Figure 20-3. D-Flash and Memory Controller Resource Memory Map 20.3.2 Register Descriptions The Flash module contains a set of 20 control and status registers located between Flash module base +...
Page 616 64 KByte Flash Module (S12XFTMR64K1V1) Address & Name 0x0002 CCOBIX2 CCOBIX1 CCOBIX0 FCCOBIX 0x0003 ECCRIX2 ECCRIX1 ECCRIX0 FECCRIX 0x0004 CCIE IGNSF FDFD FSFD FCNFG 0x0005 DFDIE SFDIE FERCNFG MGBUSY RSVD MGSTAT1 MGSTAT0 0x0006 CCIF ACCERR FPVIOL FSTAT 0x0007 DFDIF SFDIF FERSTAT RNV6 0x0008...
Page 617 64 KByte Flash Module (S12XFTMR64K1V1) Address & Name 0x0010 FOPT 0x0011 FRSV2 0x0012 FRSV3 0x0013 FRSV4 = Unimplemented or Reserved Figure 20-4. FTMR64K1 Register Summary (continued) 20.3.2.1 Flash Clock Divider Register (FCLKDIV) The FCLKDIV register is used to control timed events in program and erase algorithms. Offset Module Base + 0x0000 FDIVLD FDIV[6:0]...
Page 618 64 KByte Flash Module (S12XFTMR64K1V1) CAUTION The FCLKDIV register should never be written while a Flash command is executing (CCIF=0). The FCLKDIV register is writable during the Flash reset sequence even though CCIF is clear. S12XS Family Reference Manual, Rev. 1.13 Freescale Semiconductor...
Page 619 64 KByte Flash Module (S12XFTMR64K1V1) Table 20-7. FDIV vs OSCCLK Frequency OSCCLK Frequency OSCCLK Frequency (MHz) (MHz) FDIV[6:0] FDIV[6:0] 1.60 2.10 0x01 33.60 34.65 0x20 2.40 3.15 0x02 34.65 35.70 0x21 3.20 4.20 0x03 35.70 36.75 0x22 4.20 5.25 0x04 36.75 37.80 0x23...
Page 620 64 KByte Flash Module (S12XFTMR64K1V1) 20.3.2.2 Flash Security Register (FSEC) The FSEC register holds all bits associated with the security of the MCU and Flash module. Offset Module Base + 0x0001 KEYEN[1:0] RNV[5:2] SEC[1:0] Reset = Unimplemented or Reserved Figure 20-6. Flash Security Register (FSEC) All bits in the FSEC register are readable but not writable.
Page 621 64 KByte Flash Module (S12XFTMR64K1V1) Preferred SEC state to set MCU to secured state. The security function in the Flash module is described in Section 20.5. 20.3.2.3 Flash CCOB Index Register (FCCOBIX) The FCCOBIX register is used to index the FCCOB register for Flash memory operations. Offset Module Base + 0x0002 CCOBIX[2:0] Reset...
Page 622 64 KByte Flash Module (S12XFTMR64K1V1) 20.3.2.5 Flash Conﬁguration Register (FCNFG) The FCNFG register enables the Flash command complete interrupt and forces ECC faults on Flash array read access from the CPU or XGATE. Offset Module Base + 0x0004 CCIE IGNSF FDFD FSFD Reset...
Page 623 64 KByte Flash Module (S12XFTMR64K1V1) Offset Module Base + 0x0005 DFDIE SFDIE Reset = Unimplemented or Reserved Figure 20-10. Flash Error Conﬁguration Register (FERCNFG) All assigned bits in the FERCNFG register are readable and writable. Table 20-14. FERCNFG Field Descriptions Field Description Double Bit Fault Detect Interrupt Enable —...
Page 624 64 KByte Flash Module (S12XFTMR64K1V1) Table 20-15. FSTAT Field Descriptions Field Description Command Complete Interrupt Flag — The CCIF ﬂag indicates that a Flash command has completed. The CCIF CCIF ﬂag is cleared by writing a 1 to CCIF to launch a command and CCIF will stay low until command completion or command violation.
Page 625 64 KByte Flash Module (S12XFTMR64K1V1) Table 20-16. FERSTAT Field Descriptions Field Description Double Bit Fault Detect Interrupt Flag — The setting of the DFDIF ﬂag indicates that a double bit fault was DFDIF detected in the stored parity and data bits during a Flash array read operation or that a Flash array read operation was attempted on a Flash block that was under a Flash command operation.
Page 626 64 KByte Flash Module (S12XFTMR64K1V1) Table 20-17. FPROT Field Descriptions Field Description Flash Protection Operation Enable — The FPOPEN bit determines the protection function for program or FPOPEN erase operations as shown in Table 20-18 for the P-Flash block. 0 When FPOPEN is clear, the FPHDIS and FPLDIS bits deﬁne unprotected address ranges as speciﬁed by the corresponding FPHS and FPLS bits 1 When FPOPEN is set, the FPHDIS and FPLDIS bits enable protection for the address range speciﬁed by the corresponding FPHS and FPLS bits...
Page 627 64 KByte Flash Module (S12XFTMR64K1V1) Table 20-20. P-Flash Protection Lower Address Range FPLS[1:0] Global Address Range Protected Size 0x7F_8000–0x7F_83FF 1 Kbyte 0x7F_8000–0x7F_87FF 2 Kbytes 0x7F_8000–0x7F_8FFF 4 Kbytes 0x7F_8000–0x7F_9FFF 8 Kbytes All possible P-Flash protection scenarios are shown in Figure 20-14. Although the protection scheme is loaded from the Flash memory at global address 0x7F_FF0C during the reset sequence, it can be changed by the user.
Page 628 64 KByte Flash Module (S12XFTMR64K1V1) FPHDIS = 1 FPHDIS = 1 FPHDIS = 0 FPHDIS = 0 FPLDIS = 1 FPLDIS = 0 FPLDIS = 1 FPLDIS = 0 Scenario FLASH START 0x7F_8000 0x7F_FFFF Scenario FLASH START 0x7F_8000 0x7F_FFFF Protected region with size Unprotected region defined by FPLS Protected region...
Page 629 64 KByte Flash Module (S12XFTMR64K1V1) 20.3.2.9.1 P-Flash Protection Restrictions The general guideline is that P-Flash protection can only be added and not removed. Table 20-21 specifies all valid transitions between P-Flash protection scenarios. Any attempt to write an invalid scenario to the FPROT register will be ignored.
Page 630 64 KByte Flash Module (S12XFTMR64K1V1) P-Flash phrase containing the D-Flash protection byte during the reset sequence, the DPOPEN bit will be cleared and DPS bits will be set to leave the D-Flash memory fully protected. Trying to alter data in any protected area in the D-Flash memory will result in a protection violation error and the FPVIOL bit will be set in the FSTAT register.
Page 631 64 KByte Flash Module (S12XFTMR64K1V1) Offset Module Base + 0x000A CCOB[15:8] Reset Figure 20-16. Flash Common Command Object High Register (FCCOBHI) Offset Module Base + 0x000B CCOB[7:0] Reset Figure 20-17. Flash Common Command Object Low Register (FCCOBLO) 20.3.2.11.1 FCCOB - NVM Command Mode NVM command mode uses the indexed FCCOB register to provide a command code and its relevant parameters to the Memory Controller.
Page 632 64 KByte Flash Module (S12XFTMR64K1V1) Table 20-24. FCCOB - NVM Command Mode (Typical Usage) CCOBIX[2:0] Byte FCCOB Parameter Fields (NVM Command Mode) Data 1 [15:8] Data 1 [7:0] Data 2 [15:8] Data 2 [7:0] Data 3 [15:8] Data 3 [7:0] 20.3.2.12 Flash Reserved0 Register (FRSV0) This Flash register is reserved for factory testing.
Page 633 64 KByte Flash Module (S12XFTMR64K1V1) fault information will be recorded until the specific ECC fault flag has been cleared. In the event of simultaneous ECC faults the priority for fault recording is double bit fault over single bit fault. Offset Module Base + 0x000E ECCR[15:8] Reset = Unimplemented or Reserved...
Page 634 64 KByte Flash Module (S12XFTMR64K1V1) The P-Flash word addressed by ECCRIX = 001 contains the lower 16 bits of the global address. The following four words addressed by ECCRIX = 010 to 101 contain the 64-bit wide data phrase. The four data words and the parity byte are the uncorrected data read from the P-Flash block.
Page 635 64 KByte Flash Module (S12XFTMR64K1V1) 20.3.2.17 Flash Reserved3 Register (FRSV3) This Flash register is reserved for factory testing. Offset Module Base + 0x0012 Reset = Unimplemented or Reserved Figure 20-24. Flash Reserved3 Register (FRSV3) All bits in the FRSV3 register read 0 and are not writable. 20.3.2.18 Flash Reserved4 Register (FRSV4) This Flash register is reserved for factory testing.
Page 636 64 KByte Flash Module (S12XFTMR64K1V1) 20.4.1.1 Writing the FCLKDIV Register Prior to issuing any Flash program or erase command after a reset, the user is required to write the FCLKDIV register to divide OSCCLK down to a target FCLK of 1 MHz. Table 20-7 shows recommended values for the FDIV ﬁeld based on OSCCLK frequency.
Page 637 64 KByte Flash Module (S12XFTMR64K1V1) START Read: FCLKDIV register Clock Register FDIVLD Written Set? Check Note: FCLKDIV must be set after Write: FCLKDIV register each reset Read: FSTAT register FCCOB CCIF Availability Check Set? Results from previous Command ACCERR/ Access Error and Write: FSTAT register FPVIOL Protection Violation...
Page 638 64 KByte Flash Module (S12XFTMR64K1V1) 20.4.1.3 Valid Flash Module Commands Table 20-28. Flash Commands by Mode Unsecured Secured FCMD Command ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ 0x01 Erase Verify All Blocks ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗...
Page 639 64 KByte Flash Module (S12XFTMR64K1V1) Table 20-29. P-Flash Commands FCMD Command Function on P-Flash Memory Erase Verify All Verify that all P-Flash (and D-Flash) blocks are erased. 0x01 Blocks 0x02 Erase Verify Block Verify that a P-Flash block is erased. Erase Verify Verify that a given number of words starting at the address provided are erased.
Page 640 64 KByte Flash Module (S12XFTMR64K1V1) Table 20-30. D-Flash Commands FCMD Command Function on D-Flash Memory Supports a method of releasing MCU security by erasing all D-Flash (and P-Flash) blocks 0x0B Unsecure Flash and verifying that all D-Flash (and P-Flash) blocks are erased. Set User Margin Speciﬁes a user margin read level for the D-Flash block.
Page 641 64 KByte Flash Module (S12XFTMR64K1V1) Upon clearing CCIF to launch the Erase Verify All Blocks command, the Memory Controller will verify that the entire Flash memory space is erased. The CCIF ﬂag will set after the Erase Verify All Blocks operation has completed.
Page 642 64 KByte Flash Module (S12XFTMR64K1V1) Table 20-35. Erase Verify P-Flash Section Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters Global address [22:16] of 0x03 a P-Flash block Global address [15:0] of the ﬁrst phrase to be veriﬁed Number of phrases to be veriﬁed Upon clearing CCIF to launch the Erase Verify P-Flash Section command, the Memory Controller will verify the selected section of Flash memory is erased.
Page 643 64 KByte Flash Module (S12XFTMR64K1V1) Upon clearing CCIF to launch the Read Once command, a Read Once phrase is fetched and stored in the FCCOB indexed register. The CCIF ﬂag will set after the Read Once operation has completed. Valid phrase index values for the Read Once command range from 0x0000 to 0x0007.
Page 644 64 KByte Flash Module (S12XFTMR64K1V1) Table 20-40. Program P-Flash Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 101 at command launch Set if command not available in current mode (see Table 20-28) ACCERR Set if an invalid global address [22:0] is supplied Set if a misaligned phrase address is supplied (global address [2:0] != 000) FSTAT FPVIOL...
Page 645 64 KByte Flash Module (S12XFTMR64K1V1) Table 20-42. Program Once Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 101 at command launch Set if command not available in current mode (see Table 20-28) ACCERR Set if an invalid phrase index is supplied Set if the requested phrase has already been programmed FSTAT FPVIOL...
Page 646 64 KByte Flash Module (S12XFTMR64K1V1) Table 20-45. Erase Flash Block Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters Global address [22:16] to 0x09 identify Flash block Global address [15:0] in Flash block to be erased Upon clearing CCIF to launch the Erase Flash Block command, the Memory Controller will erase the selected Flash block and verify that it is erased.
Page 647 64 KByte Flash Module (S12XFTMR64K1V1) Table 20-48. Erase P-Flash Sector Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch Set if command not available in current mode (see Table 20-28) ACCERR Set if an invalid global address [22:16] is supplied Set if a misaligned phrase address is supplied (global address [2:0] != 000) FSTAT FPVIOL...
Page 648 64 KByte Flash Module (S12XFTMR64K1V1) 20.4.2.11 Verify Backdoor Access Key Command The Verify Backdoor Access Key command will only execute if it is enabled by the KEYEN bits in the FSEC register (see Table 20-9). The Verify Backdoor Access Key command releases security if user-supplied keys match those stored in the Flash security bytes of the Flash configuration field (see Table 20-3).
Page 649 64 KByte Flash Module (S12XFTMR64K1V1) Table 20-53. Set User Margin Level Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters Global address [22:16] to identify the 0x0D Flash block Margin level setting Upon clearing CCIF to launch the Set User Margin Level command, the Memory Controller will set the user margin level for the targeted block and then set the CCIF ﬂag.
Page 650 64 KByte Flash Module (S12XFTMR64K1V1) 20.4.2.13 Set Field Margin Level Command The Set Field Margin Level command, valid in special modes only, causes the Memory Controller to set the margin level specified for future read operations of a specific P-Flash or D-Flash block. Table 20-56.
Page 651 64 KByte Flash Module (S12XFTMR64K1V1) NOTE Field margin levels can be used to check that Flash memory contents have adequate margin for data retention at the normal level setting. If unexpected results are encountered when checking Flash memory contents at ﬁeld margin levels, the Flash memory contents should be erased and reprogrammed.
Page 652 64 KByte Flash Module (S12XFTMR64K1V1) CAUTION A Flash word must be in the erased state before being programmed. Cumulative programming of bits within a Flash word is not allowed. Table 20-61. Program D-Flash Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters Global address [22:16] to 0x11 identify the D-Flash block Global address [15:0] of word to be programmed...
Page 653: Bit
64 KByte Flash Module (S12XFTMR64K1V1) Table 20-63. Erase D-Flash Sector Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters Global address [15:0] anywhere within the sector to be erased. Section 20.1.2.2 for D-Flash sector size. Upon clearing CCIF to launch the Erase D-Flash Sector command, the Memory Controller will erase the selected Flash sector and verify that it is erased.
Page 654 64 KByte Flash Module (S12XFTMR64K1V1) the DFDIE and SFDIE interrupt enable bits to generate the Flash error interrupt request. For a detailed description of the register bits involved, refer to Section 20.3.2.5, “Flash Configuration Register (FCNFG)”, Section 20.3.2.6, “Flash Error Configuration Register (FERCNFG)”, Section 20.3.2.7, “Flash Status Register...
Page 655 64 KByte Flash Module (S12XFTMR64K1V1) 20.5.1 Unsecuring the MCU using Backdoor Key Access The MCU may be unsecured by using the backdoor key access feature which requires knowledge of the contents of the backdoor keys (four 16-bit words programmed at addresses 0x7F_FF00–0x7F_FF07). If the KEYEN[1:0] bits are in the enabled state (see Section 20.3.2.2), the Verify Backdoor Access Key...
Page 656 64 KByte Flash Module (S12XFTMR64K1V1) • Reset the MCU into special expanded wide mode, disable protection in the P-Flash and D-Flash memory and run code from external memory to execute the Erase All Blocks command write sequence to erase the P-Flash and D-Flash memory. After the CCIF ﬂag sets to indicate that the Erase All Blocks operation has completed, reset the MCU into special single chip mode.
Page 657: Appendix A Electrical Characteristics
Appendix A Electrical Characteristics General NOTE The electrical characteristics given in this section should be used as a guide only. Values cannot be guaranteed by Freescale and are subject to change without notice. Data are currently based on characterization data of 9S12XS128 material only unless marked differently.
Page 658 Electrical Characteristics The VDDX, VSSX pin pairs [2:1] supply the I/O pins. VDDR supplies the internal voltage regulator. VDDPLL, VSSPLL pin pair supply the oscillator and the PLL. VSS1, VSS2 and VSS3 are internally connected by metal. All VDDX pins are internally connected by metal. All VSSX pins are internally connected by metal.
Page 659 Electrical Characteristics A.1.3.4 TEST This pin is used for production testing only. The TEST pin must be tied to V in all applications. A.1.4 Current Injection Power supply must maintain regulation within operating V or V range during instantaneous and DD35 operating maximum current conditions.
Page 660 Electrical Characteristics Table A-1. Absolute Maximum Ratings Rating Symbol Unit I/O, regulator and analog supply voltage –0.3 DD35 Digital logic supply voltage –0.3 2.16 PLL supply voltage –0.3 2.16 DDPLL NVM supply voltage –0.3 ∆ Voltage difference V to V –6.0 VDDX ∆...
Page 661 Electrical Characteristics Table A-2. ESD and Latch-up Test Conditions Model Description Symbol Value Unit Human Body Series resistance 1500 Storage capacitance Number of pulse per pin Positive — Negative — Charged Device Number of pulse per pin Positive — Negative —...
Page 662 Electrical Characteristics Table A-4. Operating Conditions ∆ Voltage difference V to V -0.1 VDDR ∆ Voltage difference V to V refer to Table A-14 VSSX ∆ Voltage difference V to V -0.1 SSPLL Digital logic supply voltage 1.72 1.98 PLL supply voltage 1.72 1.98 DDPLL...
Page 663 Electrical Characteristics The total power dissipation can be calculated from: Chip Internal Power Dissipation, [W] ∑ ⋅ DSON IO i is the sum of all output currents on I/O ports associated with V , whereby ----------- - for outputs driven low DSON –...
Page 664 Electrical Characteristics Table A-5. Thermal Package Characteristics (9S12XS256) Rating Symbol Unit LQFP 112 θ °C/W Thermal resistance LQFP 112, single sided PCB — — θ °C/W Thermal resistance LQFP 112, double sided PCB — — with 2 internal planes θ °C/W Junction to Board LQFP 112 —...
Page 665 Electrical Characteristics Table A-6. Thermal Package Characteristics (9S12XS128) Rating Symbol Unit LQFP 112 θ °C/W Thermal resistance LQFP 112, single sided PCB — — θ °C/W Thermal resistance LQFP 112, double sided PCB — — with 2 internal planes θ °C/W Junction to Board LQFP 112 —...
Page 666 Electrical Characteristics A.1.9 I/O Characteristics This section describes the characteristics of all I/O pins except EXTAL, XTAL, TEST and supply pins. Table A-7. 3.3-V I/O Characteristics Conditions are 3.13 V < V < 3.6 V junction temperature from –40°C to +150°C, unless otherwise noted DD35 I/O Characteristics for all I/O pins except EXTAL, XTAL,TEST and supply pins.
Page 667 Electrical Characteristics Table A-7. 3.3-V I/O Characteristics Conditions are 3.13 V < V < 3.6 V junction temperature from –40°C to +150°C, unless otherwise noted DD35 I/O Characteristics for all I/O pins except EXTAL, XTAL,TEST and supply pins. µs P Port H, J, P interrupt input pulse ﬁltered (STOP) —...
Page 668 Electrical Characteristics Table A-8. 5-V I/O Characteristics Conditions are 4.5 V < V < 5.5 V junction temperature from –40°C to +150°C, unless otherwise noted DD35 I/O Characteristics for all I/O pins except EXTAL, XTAL,TEST and supply pins. Num C Rating Symbol Unit...
Page 669 Electrical Characteristics Table A-8. 5-V I/O Characteristics Conditions are 4.5 V < V < 5.5 V junction temperature from –40°C to +150°C, unless otherwise noted DD35 I/O Characteristics for all I/O pins except EXTAL, XTAL,TEST and supply pins. D Port H, J, P interrupt input pulse passed (STOP) —...
Page 670 Electrical Characteristics 4MHz loop controlled Pierce oscillator. Production test parameters are tested with a 4MHz square wave oscillator. Table A-10 shows the conﬁguration of the peripherals for maximum run current =5.5V Table A-10. Module Conﬁgurations for Maximum Run Supply (VDDR+VDDA) Current DD35 Peripheral Conﬁguration...
Page 671 Electrical Characteristics Table A-12. Run and Wait Current Characteristics Conditions are shown in Table A-4 unless otherwise noted Rating Symbol Unit Run supply current (No external load, Peripheral Conﬁguration see Table A-10.) Peripheral Set DD35 =4MHz, f =40MHz — — Peripheral Set Device 9S12XS256 DD35...
Page 672 Electrical Characteristics Table A-13. Pseudo Stop and Full Stop Current Conditions are shown in Table A-4 unless otherwise noted Rating Symbol Unit Pseudo stop current (API, RTI, and COP disabled) PLL off, LCP mode µA –40°C — DDPS 27°C — 70°C —...
Page 673 Electrical Characteristics ATD Characteristics This section describes the characteristics of the analog-to-digital converter. A.2.1 ATD Operating Characteristics Table A-14 Table A-15 show conditions under which the ATD operates. The following constraints exist to obtain full-scale, full range results: ≤ V ≤...
Page 674 Electrical Characteristics is recommended to conﬁgure PortAD pins as outputs only for low frequency, low load outputs. The impact on ATD accuracy is load dependent and not speciﬁed. The values speciﬁed are valid under condition that no PortAD output drivers switch during conversion. A.2.2.2 Source Resistance Due to the input pin leakage current as speciﬁed in...
Page 675 Electrical Characteristics Table A-15. ATD Electrical Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C Rating Symbol Unit C Max input source resistance — — KΩ D Total input capacitance Non sampling — — Total input capacitance Sampling —...
Page 676 Electrical Characteristics A.2.3.1 ATD Accuracy Deﬁnitions For the following deﬁnitions see also Figure A-1. Differential non-linearity (DNL) is deﬁned as the difference between two adjacent switching steps. – – DNL i ( ) -------------------------- - 1 – 1LSB The integral non-linearity (INL) is deﬁned as the sum of all DNLs: ∑...
Page 677 Electrical Characteristics 10-Bit Absolute Error Boundary Vi-1 $3FF 8-Bit Absolute Error Boundary $3FE $3FD $3FC $3FB $3FA $3F9 $3F8 $3F7 $3F6 $3F5 $3F4 $3F3 Ideal Transfer Curve 10-Bit Transfer Curve 8-Bit Transfer Curve 95 100 105 110 115 120 5000 + Figure A-1.
Page 678 Electrical Characteristics Table A-16. ATD Conversion Performance 5V range Conditions are shown in Table A-4. unless otherwise noted. V = 5.12V. f = 8.0MHz ATDCLK The values are tested to be valid with no PortAD output drivers switching simultaneous with conversions. Num C Rating Symbol...
Page 679 Electrical Characteristics NVM, Flash A.3.1 Timing Parameters The time base for all NVM program or erase operations is derived from the oscillator. A minimum oscillator frequency f is required for performing program or erase operations. The NVM modules NVMOSC do not have any means to monitor the frequency and will not prevent program or erase operation at frequencies above or below the speciﬁed minimum.
Page 680 Electrical Characteristics A.3.1.4 Read Once (FCMD=0x04) The maximum read once time is given by ⋅ -------------------- - NVMBUS A.3.1.5 Program P-Flash (FCMD=0x06) The programming time for a single phrase of four P-Flash words + associated eight ECC bits is dependant on the bus frequency as a well as on the frequency f and can be calculated according to the NVMOP...
Page 681 Electrical Characteristics A.3.1.8 Erase P-Flash Block (FCMD=0x09) Erasing a 256K NVM block takes ≈ ⋅ ⋅ t mass 100100 70000 --------------------------- - ------------------------ - f NVMOP f NVMBUS Erasing a 128K NVM block takes ≈ ⋅ ⋅ t mass 100100 35000 --------------------------- - ------------------------ -...
Page 682 Electrical Characteristics ⋅ --------------------------- - f NVMBUS A.3.1.14 Erase Verify D-Flash Section (FCMD=0x10) Erase Verify D-Flash for a given number of words N is given by . ≈ ⋅ t check --------------------------- - NVMBUS A.3.1.15 D-Flash Programming (FCMD=0x11) D-Flash programming time is dependent on the number of words being programmed and their location with respect to a row boundary, because programming across a row boundary requires extra steps.
Page 683 Electrical Characteristics Table A-18. NVM Timing Characteristics Conditions are as shown in Table A-4, with 40MHz bus and f = 1MHz unless otherwise noted. NVMOP Num C Rating Symbol Unit D External oscillator clock — NVMOSC D Bus frequency for programming or erase operations —...
Page 684 Electrical Characteristics Table A-19. NVM Reliability Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C Rating Symbol Unit P-Flash Array C Data retention at an average junction temperature of T — Years Javg PNVMRET 85°C after up to 10,000 program/erase cycles C Data retention at an average junction temperature of T —...
Page 685 Electrical Characteristics Voltage Regulator Table A-20. Voltage Regulator Electrical Characteristics Conditions are shown in Table A-4 unless otherwise noted Characteristic Symbol Typical Unit Input Voltages 3.13 — 5.50 VDDR,A Output Voltage Core Full Performance Mode 1.72 1.84 1.98 Reduced Power Mode (MCU STOP mode) —...
Page 686 Electrical Characteristics Output Loads A.5.1 Resistive Loads The voltage regulator is intended to supply the internal logic and oscillator. It allows no external DC loads. A.5.2 Capacitive Loads The capacitive loads are speciﬁed in Table A-21. Ceramic capacitors with X7R dielectricum are required. Table A-21.
Page 687 Electrical Characteristics DDR, >= 0 Figure A-3. S12XS family Power Sequencing During power sequencing V can be powered up before V and V must be powered up together adhering to the operating conditions differential. power up must follow V to avoid current injection. S12XS Family Reference Manual, Rev.
Page 688 Electrical Characteristics Reset, Oscillator and PLL This section summarizes the electrical characteristics of the various startup scenarios for oscillator and phase-locked loop (PLL). A.6.1 Startup Table A-22 summarizes several startup characteristics explained in this section. Detailed description of the startup behavior can be found in the Clock and Reset Generator (CRG) block description Table A-22.
Page 689 Electrical Characteristics A.6.1.5 Pseudo Stop and Wait Recovery The recovery from pseudo stop and wait is essentially the same since the oscillator is not stopped in both modes. The controller can be woken up by internal or external interrupts. After t the CPU starts fetching the interrupt vector.
Page 690 Electrical Characteristics A.6.2 Oscillator Table A-23. Oscillator Characteristics Conditions are shown in Table A-4. unless otherwise noted Num C Rating Symbol Unit C Crystal oscillator range (loop controlled Pierce) — C Crystal oscillator range (full swing Pierce) — µA P Startup Current —...
Page 691 Electrical Characteristics A.6.3 Phase Locked Loop A.6.3.1 Jitter Information With each transition of the clock f , the deviation from the reference clock f is measured and input voltage to the VCO is adjusted accordingly.The adjustment is done continuously with no abrupt changes in the clock output frequency.
Page 692 Electrical Characteristics For N < 1000, the following equation is a good ﬁt for the maximum jitter: ------- - J(N) Figure A-5. Maximum bus clock jitter approximation NOTE On timers and serial modules a prescaler will eliminate the effect of the jitter to a large extent.
Page 693 Electrical Characteristics MSCAN Table A-25. MSCAN Wake-up Pulse Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C Rating Symbol Unit µs P MSCAN wakeup dominant pulse ﬁltered — — µs P MSCAN wakeup dominant pulse pass — —...
Page 694 Electrical Characteristics SPI Timing This section provides electrical parametrics and ratings for the SPI. In Table A-26 the measurement conditions are listed. Table A-26. Measurement Conditions Description Value Unit Drive mode Full drive mode — Load capacitance C on all outputs LOAD Thresholds for delay measurement points (20% / 80%) V...
Page 695 Electrical Characteristics Figure A-7 the timing diagram for master mode with transmission format CPHA=1 is depicted. (Output) (CPOL = 0) (Output) (CPOL = 1) (Output) MISO Bit MSB-1. . . 1 MSB IN2 LSB IN (Input) MOSI Port Data Bit MSB-1. . . 1 Master LSB OUT Port Data Master MSB OUT2...
Page 696 Electrical Characteristics [MHz] Figure A-8. D erating of maximum f to f ratio in Master Mode A.8.2 Slave Mode Figure A-9 the timing diagram for slave mode with transmission format CPHA = 0 is depicted. (Input) (CPOL = 0) (Input) (CPOL = 1) (Input) MISO...
Page 697 Electrical Characteristics Figure A-10 the timing diagram for slave mode with transmission format CPHA = 1 is depicted. (Input) (CPOL = 0) (Input) (CPOL = 1) (Input) MISO Bit MSB-1 . . . 1 Slave MSB OUT Slave LSB OUT Note (Output) MOSI...
Page 698: Appendix B Package Information
Package Information Appendix B Package Information This section provides the physical dimensions of the S12XS family packages. S12XS Family Reference Manual, Rev. 1.13 Freescale Semiconductor...
Page 699 Package Information 112-pin LQFP Mechanical Dimensions Figure B-1. 112-pin LQFP (case no. 987) - page 1 S12XS Family Reference Manual, Rev. 1.13 Freescale Semiconductor...
Page 700 Package Information Figure B-2. 112-pin LQFP (case no. 987) - page 2 S12XS Family Reference Manual, Rev. 1.13 Freescale Semiconductor...
Page 701 Package Information Figure B-3. 112-pin LQFP (case no. 987) - page 3 S12XS Family Reference Manual, Rev. 1.13 Freescale Semiconductor...
Page 702 Package Information 80-Pin QFP Mechanical Dimensions Figure B-4. 80-pin QFP (case no. 841B) - page 1 S12XS Family Reference Manual, Rev. 1.13 Freescale Semiconductor...
Page 703 Package Information Figure B-5. 80-pin QFP (case no. 841B) - page 2 S12XS Family Reference Manual, Rev. 1.13 Freescale Semiconductor...
Page 704 Package Information Figure B-6. 80-pin QFP (case no. 841B) - page 3 S12XS Family Reference Manual, Rev. 1.13 Freescale Semiconductor...
Page 705 Package Information 64-Pin LQFP Mechanical Dimensions S12XS Family Reference Manual, Rev. 1.13 Freescale Semiconductor...
Page 706 Package Information 64-pin LQFP (case no. 840F) Figure B-7. - page 2 S12XS Family Reference Manual, Rev. 1.13 Freescale Semiconductor...
Page 707 Package Information 64-pin LQFP (case no. 840F) Figure B-8. - page 3 S12XS Family Reference Manual, Rev. 1.13 Freescale Semiconductor...
Page 708: Appendix Cpcb Layout Guidelines
PCB Layout Guidelines Appendix C PCB Layout Guidelines General The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as of the MCU itself. The following rules must be observed: • Every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the corresponding pins .
Page 709 PCB Layout Guidelines C.1.1 112-Pin LQFP Recommended PCB Layout Figure C-1. 112-Pin LQFP Recommended PCB Layout (Loop Controlled Pierce Oscillator) S12XS Family Reference Manual, Rev. 1.13 Freescale Semiconductor...
Page 710 PCB Layout Guidelines C.1.2 80-Pin QFP Recommended PCB Layout Figure C-2. 80-Pin QFP Recommended PCB Layout (Loop Controlled Pierce Oscillator) S12XS Family Reference Manual, Rev. 1.13 Freescale Semiconductor...
Page 711 PCB Layout Guidelines C.1.3 64-Pin LQFP Recommended PCB Layout Figure C-3. 64-Pin LQFP Recommended PCB Layout (Loop Controlled Pierce Oscillator) S12XS Family Reference Manual, Rev. 1.13 Freescale Semiconductor...
Page 712: Appendix D Derivative Differences
Derivative Differences Appendix D Derivative Differences Memory Sizes and Package Options S12XS family Table D-1. Package and Memory Options of S12XS family Device Package Flash RAM Data Flash 9S12XS256 112 LQFP 256K 80 QFP 64 LQFP 9S12XS128 112 LQFP 128K 80 QFP 64 LQFP 9S12XS64...
Page 713: Appendix E Detailed Register Address Map
Detailed Register Address Map Appendix E Detailed Register Address Map Detailed Register Map The following tables show the detailed register map of the S12XS family. 0x0000–0x0009 Port Integration Module (PIM) Map 1 of 5 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3...
Page 714 Detailed Register Address Map 0x000E–0x000F Reserved Register Space Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x000E Reserved 0x000F Reserved 0x0010–0x0017 Module Mapping Control (S12XMMC) Map 2 of 2 Address Name Bit 7 Bit 6...
Page 715 Detailed Register Address Map 0x001E–0x001F Port Integration Module (PIM) Map 3 of 5 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x001E IRQCR IRQE IRQEN 0x001F Reserved 0x0020–0x002F Debug Module (S12XDBG) Map Address Name Bit 7...
Page 716 Detailed Register Address Map 0x0030–0x0031 Reserved Register Space Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0030 Reserved 0x0031 Reserved 0x0032–0x0033 Port Integration Module (PIM) Map 4 of 5 Address Name Bit 7 Bit 6...
Page 717 Detailed Register Address Map 0x0040–0x006F Timer Module (TIM) Map Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0040 TIOS IOS7 IOS6 IOS5 IOS4 IOS3 IOS2 IOS1 IOS0 0x0041 CFORC FOC7 FOC6 FOC5 FOC4...
Page 718 Detailed Register Address Map 0x0040–0x006F Timer Module (TIM) Map Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0057 TC3L Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0058...
Page 719 Detailed Register Address Map 0x00C8–0x00CF Asynchronous Serial Interface (SCI0) Map Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x00C8 SCI0BDH IREN TNP1 TNP0 SBR12 SBR11 SBR10 SBR9 SBR8 0x00C9 SCI0BDL SBR7 SBR6 SBR5...
Page 720 Detailed Register Address Map 0x00D0–0x00D7 Asynchronous Serial Interface (SCI1) Map (continued) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x00D5 SCI1SR2 AMAP TXPOL RXPOL BRK13 TXDIR 0x00D6 SCI1DRH 0x00D7 SCI1DRL Those registers are accessible if the AMAP bit in the SCI1SR2 register is set to zero Those registers are accessible if the AMAP bit in the SCI1SR2 register is set to one 0x00D8–0x00DF Serial Peripheral Interface (SPI0) Map...
Page 721 Detailed Register Address Map 0x0100–0x0113 NVM Control Register (FTMR) Map (continued) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0104 FCNFG CCIE IGNSF FDFD FSFD 0x0105 FERCNFG DFDIE SFDIE MGBUSY RSVD MGSTAT1 MGSTAT0 0x0106...
Page 722 Detailed Register Address Map 0x0120–0x012F Interrupt Module (S12XINT) Map Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0120 Reserved 0x0121 IVBR IVB_ADDR[7:0] 0x0122 Reserved 0x0123 Reserved 0x0124 Reserved 0x0125 Reserved 0x0126 INT_XGPRIO XILVL[2:0]...
Page 723 Detailed Register Address Map 0x0140–0x017F MSCAN (CAN0) Map (continued) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0142 CAN0BTR0 SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 0x0143 CAN0BTR1 SAMP TSEG22 TSEG21 TSEG20...
Page 724 Detailed Register Address Map Detailed MSCAN Foreground Receive and Transmit Buffer Layout Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Extended ID ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 0xXXX0 Standard ID ID10...
Page 725 Detailed Register Address Map Detailed MSCAN Foreground Receive and Transmit Buffer Layout (continued) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TSR7 TSR6 TSR5 TSR4 TSR3 TSR2 TSR1 TSR0 0xXX1F CANxTTSRL 0x0180–0x023F Reserved Register Space Address...
Page 726 Detailed Register Address Map 0x0240–0x027F Port Integration Module (PIM) Map 5 of 5 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0248 PTS7 PTS6 PTS5 PTS4 PTS3 PTS2 PTS1 PTS0 PTIS7 PTIS6 PTIS5...
Page 727 Detailed Register Address Map 0x0240–0x027F Port Integration Module (PIM) Map 5 of 5 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0260 PTH7 PTH6 PTH5 PTH4 PTH3 PTH2 PTH1 PTH0 PTIH7 PTIH6 PTIH5...
Page 728 Detailed Register Address Map 0x0240–0x027F Port Integration Module (PIM) Map 5 of 5 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R PER0AD0 PER0AD0 PER0AD0 PER0AD0 PER0AD0 PER0AD0 PER0AD0 PER0AD0 0x0276 PER0AD0 R PER1AD0...
Page 729 Detailed Register Address Map 0x02C0–0x02EF Analog-to-Digital Converter 12-Bit 16-Channel (ATD0) Map (continued) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x02CF ATD0CMPHTL CMPHT7 CMPHT6 CMPHT5 CMPHT4 CMPHT3 CMPHT2 CMPHT1 CMPHT0 Bit15 Bit8 0x02D0...
Page 730 Detailed Register Address Map 0x02C0–0x02EF Analog-to-Digital Converter 12-Bit 16-Channel (ATD0) Map (continued) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit15 Bit8 0x02E6 ATD0DR11H Bit7 Bit6 0x02E7 ATD0DR11L Bit15 Bit8 0x02E8 ATD0DR12H Bit7...
Page 731 Detailed Register Address Map 0x0300–0x0327 Pulse Width Modulator 8-Bit 8-Channel (PWM) Map Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0300 PWME PWME7 PWME6 PWME5 PWME4 PWME3 PWME2 PWME1 PWME0 0x0301 PWMPOL PPOL7...
Page 732 Detailed Register Address Map 0x0300–0x0327 Pulse Width Modulator 8-Bit 8-Channel (PWM) Map Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0317 PWMPER3 Bit 7 Bit 0 0x0318 PWMPER4 Bit 7 Bit 0 0x0319 PWMPER5...
Page 733 Detailed Register Address Map 0x00340–0x0367 – Periodic Interrupt Timer (PIT) Map Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0340 PITCFLMT PITE PITSWAI PITFRZ PFLMT1 PFLMT0 0x0341 PITFLT PFLT3 PFLT2 PFLT1 PFLT0 0x0342...
Page 734 Detailed Register Address Map Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0356 PITCNT3 (hi) PCNT15 PCNT14 PCNT13 PCNT12 PCNT11 PCNT10 PCNT9 PCNT8 0x0357 PITCNT3 (lo) PCNT7 PCNT6 PCNT5 PCNT4 PCNT3 PCNT2 PCNT1...
Page 735: Appendix F Ordering Information
Ordering Information Appendix F Ordering Information Ordering Information The following ﬁgure provides an ordering part number example for the devices covered by this data book. There are two options when ordering a device. Customers must choose between ordering either the mask- speciﬁc part number or the generic / mask-independent part number.
Page 736 Ordering Information S12XS Family Reference Manual, Rev. 1.13 Freescale Semiconductor...
Page 738 How to Reach Us: Home Page: www.freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 1-800-521-6274 or 480-768-2130 Europe, Middle East, and Africa: +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) Japan:...
Page 739 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Freescale Semiconductor S9S12XS256J0VAER LFSMPBS12XSCM LFSMPBS12XSDM LFSMPBS12XSFM MC9S12XS256CAE LFSMPBS12XSIM LFSMPBS12XSE2M S9S12XS128J1CAER S9S12XS256J0MAAR S9S12XS128J1VAER S9S12XS256J0CAER S9S12XS64J1MAL S9S12XS256J0VAAR S9S12XS256J0VAA S9S12XS256J0CAL S9S12XS128J1CAA S9S12XS128J1CAL S9S12XS128J1CALR S9S12XS128J1MAA S9S12XS128J1MAE S9S12XS128J1MAL S9S12XS64J1CAE MC9S12XS128CAE MC9S12XS128MAA MC9S12XS128MAE MC9S12XS128MAL MC9S12XS64CAE MC9S12XS64MAE S9S12XS256J0VAE S9S12XS256J0CAE S9S12XS256J0CAA MC9S12XS128MAER S9S12XS128J1CAE S9S12XS64J1MAE S9S12XS128J1VAE S9S12XS64J1VAE S9S12XS128J1CAAR S9S12XS128J1MAAR S9S12XS128J1VAAR S9S12XS256J0CAAR S9S12XS256J0VAL S9S12XS128J1MALR S9S12XS256J0MAER S9S12XS128J1MAER...

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