Chip Specific Pulse Width Modulator - NXP Semiconductors MC9S08SU16 Reference Manual

Chapter 26
Pulse Width Modulator (PWM)

26.1 Chip specific pulse width modulator

This device has one pulse width modulator (PWM).
The PWM can be configured as three complementary pairs, six independent PWM
signals or their combinations, such as one complementary and four independent. Both
edge- and center-aligned synchronous pulse width control, from 0 to 100% modulation,
are supported.
A 15-bit common PWM counter is applied to all six channels. PWM resolution is one
clock period for edge-aligned operation and two clock periods for center-aligned
operation. The clock period is dependent on clock source frequency at HSCLK which is
up to 40 MHz and a programmable prescaler.
When generating complementary PWM signals, the module features automatic deadtime
insertion to PWM output pairs. Each PWM output can be controlled by PWM generator,
timer or software manually and separate top and bottom output polarity control.
Asymmetric PWM output is able to change PWM duty cycle alternatively at every half
cycle without software involvement.
Module
PWM
NXP Semiconductors
Table 26-1. PWM module signals connection
Fault0
Fault1
Fault2
Fault3
PWM_Synch
PWM0, PWM1
PWM2, PWM3
PWM4, PWM5
Internal Clock
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Signal
PTC0/PWM_Fault0
XBAR_OUT14
GDU OPAMP0 ACMP OUT
GDU OPAMP1 ACMP OUT
XBAR_IN4
GDU inputs, XB_IN5 2-to-1 Mux
GDU inputs, XB_IN6 2-to-1 Mux
GDU inputs, XB_IN7 2-to-1 Mux
HSCLK
Connect to
481