Mux Control Register (Cmp_Muxcr) - NXP Semiconductors MC9S08SU16 Reference Manual

Memory Map/Register Definitions

18.10.6 MUX Control Register (CMP_MUXCR)

PEN and MEN bits should be enabled or disabled together with
CR1[EN] bit.
Address: 68h base + 5h offset = 6Dh
Bit 7
Read 0
Write
Reset
0
Field
7–6 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
5–4 Plus Input MUX Control
PSEL
Determines which input is selected for the plus input of the comparator. For INx inputs, refer to CMP, DAC
and ANMUX Blocks Diagram.
NOTE: When an inappropriate operation selects the same input for both MUXes, the comparator
00 IN0
01 IN1
10 IN2
11 6-bit DAC output is selected
3–2 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
MSEL Minus Input MUX Control
Determines which input is selected for the minus input of the comparator. For INx inputs, refer to CMP,
DAC and ANMUX Blocks Diagram.
NOTE: When an inappropriate operation selects the same input for both MUXes, the comparator
00 IN0
01 IN1
10 IN2
11 6-bit DAC output is selected
300
6 5
PSEL
0 0
CMP_MUXCR field descriptions
automatically shuts down to prevent itself from becoming a noise generator.
automatically shuts down to prevent itself from becoming a noise generator.
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
NOTE
4 3
0
0 0
Description
2 1
MSEL
0 0
NXP Semiconductors
0
0