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Memory Map and Register Descriptions
Field
6
Debug Enable
DBGEN
When set to one, the PWM continues to run while the chip is in EOnCE debug mode. If the device enters
EOnCE mode and this bit is zero, then the PWM outputs are switched to their inactive state until EOnCE
mode is exited. At that point the PWM pins resume operation as programmed in the PWM registers.
For certain types of motors (such as 3-phase AC), it is imperative that this bit be left in its default state (in
which the PWM is disabled in EOnCE mode). Failure to do so could result in damaging the motor. For
other types of motors (example: DC motors), this bit might safely be set to one, enabling the PWM in
debug mode. The key point is PWM parameter updates do not occur in debug mode. Any motors requiring
such updates should be disabled during EOnCE mode. If in doubt, leave this bit cleared to zero.
5
Wait Enable
WAITEN
When set to one, the PWM continues to run while the chip is in wait mode. In this mode, the peripheral
clock continues to run but the DSC clock does not. If the device enters wait mode and this bit is zero, then
the PWM outputs are switched to their inactive state until wait mode is exited. At that point the PWM pins
resume operation as programmed in the PWM registers.
For certain types of motors (such as 3-phase AC), it is imperative that this bit be left in its default state (in
which the PWM is disabled in wait mode). Failure to do so could result in damaging the motor. For other
types of motors (example: DC motors), this bit might safely be set to one, enabling the PWM in wait mode.
The key point is PWM parameter updates do not occur in this mode. Any motors requiring such updates
should be disabled during wait mode. If in doubt, leave this bit set to zero.
4
Edge-Aligned or Center-Aligned PWMs
EDG
This write-protectable bit determines whether all PWM channels use edge-aligned or center-aligned
waveforms.
0
Center-aligned PWMs
1
Edge-aligned PWMs
3
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
TOPNEG
Top-side PWM Polarity Bit
This write-protectable bit determines the polarity for the top-side PWMs.
NOTE: Each pair of PWM channels can be configured: channel zero to one, channel two to three, and
0
Positive top-side polarity
1
Negative top-side polarity
26.4.22 PWM Channel Control Register: Low (PWM_CCTRLL)
This write-protectable register contains the configuration bits that determine PWM modes
of operation as detailed below. The ENHA bit cannot be modified after the WP bit in the
CNFG register is set. ENHA in turn provides protection for the VLMODE[1:0], SWP45,
SWP23 and SWP01 bits. The Mask bits are not write protectable.
522
PWM_CNFGH field descriptions (continued)
channel four to five.
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Description
NXP Semiconductors
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