Debug Fifo Low Register (Dbg_Fl) - NXP Semiconductors MC9S08SU16 Reference Manual

Field
F[15:8] FIFO High Data Bits
The FIFO High data bits provide access to bits [15:8] of data in the FIFO. This register is not used in event
only modes and will read a $00 for valid FIFO words.

28.3.8 Debug FIFO Low Register (DBG_FL)

All the bits in this register reset to 0 in POR or non-end-run
reset. The bits are undefined in end-run reset. In the case of an
end-trace to reset where DBGEN = 1 and BEGIN = 0, the bits
in this register do not change after reset.
Address: 18C0h base + 7h offset = 18C7h
Bit 7
Read
Write
Reset 0
Field
F[7:0] FIFO Low Data Bits
The FIFO Low data bits contain the least significant byte of data in the FIFO. When reading FIFO words,
read DBGFX and DBGFH before reading DBGFL because reading DBGFL causes the FIFO pointers to
advance to the next FIFO location. In event-only modes, there is no useful information in DBGFX and
DBGFH so it is not necessary to read them before reading DBGFL.
NXP Semiconductors
DBG_FH field descriptions
NOTE
6 5
0 0
DBG_FL field descriptions
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Description
4 3
F[7:0]
0 0
Description
Chapter 28 Debug module (DBG)
2 1
0 0
0
0
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