Port B Direction Register (Port_Ptbdd); Port C Direction Register (Port_Ptcdd) - NXP Semiconductors MC9S08SU16 Reference Manual

8.5.5 Port B Direction Register (PORT_PTBDD)

Address: 0h base + 4h offset = 4h
Bit 7
Read
Write
Reset 0
Field
PTBDD Port B Direction Register Bits
These bits control the direction of port B pins and what is read for PTBD reads.
NOTE: PTB7 pin is output only.
0 Pin is configured as general-purpose input, for the GPIO function.
1 Pin is configured as general-purpose output, for the GPIO function.

8.5.6 Port C Direction Register (PORT_PTCDD)

Address: 0h base + 5h offset = 5h
Bit 7
Read
Write
Reset 0
Field
7–1 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
0 Port C Direction Register Bits
PTCDD
These bits control the direction of port C pins and what is read for PTCD reads.
0 Pin is configured as general-purpose input, for the GPIO function.
1 Pin is configured as general-purpose output, for the GPIO function.
NXP Semiconductors
6 5
0 0
PORT_PTBDD field descriptions
6 5
0 0
PORT_PTCDD field descriptions
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
4 3
PTBDD
0 0
Description
4 3
0
0 0
Description
Chapter 8 Port Control (PORT)
2 1
0 0
2 1
PTCDD
0 0
0
0
0
0
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