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Functional description
In FLL engaged internal mode, the ICSOUT clock is derived from the FLL clock, which
is controlled by the internal reference clock. The FLL loop locks the frequency to 1024
times the internal reference frequency. The internal reference clock is enabled.
12.4.1.2 FLL engaged external (FEE)
The FLL engaged external (FEE) mode is entered when all the following conditions
occur:
• 00b is written to ICS_C1[CLKS].
• 0b is written to ICS_C1[IREFS].
• ICS_C1[RDIV] and SIM_SOPT1[RANGE] are written to divide external reference
clock to be within the range of 31.25 kHz to 39.0625 kHz.
In FLL engaged external mode, the ICSOUT clock is derived from the FLL clock which
is controlled by the external reference clock source.The FLL loop locks the frequency to
1024 times the external reference frequency, as selected by ICS_C1[RDIV] and
SIM_SOPT1[RANGE]. The external reference clock is enabled.
12.4.1.3 FLL bypassed internal (FBI)
The FLL bypassed internal (FBI) mode is entered when all the following conditions
occur:
• 01b is written to ICS_C1[CLKS].
• 1b is written to ICS_C1[IREFS].
• BDM mode is active or ICS_C2[LP] bit is written to 0.
In FLL bypassed internal mode, the ICSOUT clock is derived from the internal reference
clock. The FLL clock is controlled by the internal reference clock, and the FLL loop
locks the FLL frequency to 1024 times the internal reference frequency. The internal
reference clock is enabled.
12.4.1.4 FLL bypassed internal low power (FBILP)
The FLL bypassed internal low power (FBILP) mode is entered when all the following
conditions occur:
• 01b is written to ICS_C1[CLKS].
• 1b is written to ICS_C1[IREFS].
• BDM mode is not active and ICS_C2[LP] bit is written to 1b.
In FLL bypassed internal low-power mode, the ICSOUT clock is derived from the
internal reference clock and the FLL is disabled. The internal reference clock is enabled.
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MC9S08SU16 Reference Manual, Rev. 5, 4/2017
NXP Semiconductors
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