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Functional description
hardware trigger is set. An interrupt request will be submitted to CPU if the
ADC_SC1[AIEN] is set when the FIFO conversion completes and the
ADC_SC1[COCO] bit is set.
ADC_RL read
ADC_RH read
ADCH write
FIFO Read/Write Logic reset
FIFO Read/Write Logic
FIFO Work Logic
FIFO conversion start
If software trigger is enabled, the next analog channel is fetched from analog input
channel FIFO as soon as a conversion completes and its result is stored in the result
FIFO. When all conversions set in the analog input channel FIFO completes, the
ADC_SC1[COCO] bit is set and an interrupt request will be submitted to CPU if the
ADC_SC1[AIEN] bit is set.
If single hardware trigger mode is enabled(ADC_SC2[ADTRG]= 1 and
ADC_SC4[HTRGME]=0 ), the next analog is fetched from analog input channel FIFO
only when this conversion completes, its result is stored in the result FIFO, and the next
hardware trigger is fed to ADC module. If multi hardware tigger mode is
enabled(ADC_SC2[ADTRG]=1 and ADC_SC4[HTRGME]=1), the next analog is
fetched from analog input channel FIFO only when this conversion completes, its result
is stored in the result FIFO, and next conversion will start without waiting for next
276
AFDEP
ADCH
7
5-bit ch
5-bit ch
6
5
5-bit ch
5-bit ch
4
3
5-bit ch
5-bit ch
2
1
5-bit ch
5-bit ch
0
Result FIFO read pointer
Channel FIFO write pointer
Result FIFO write pointer
Channel FIFO read pointer
Figure 17-2. FADC FIFO structure
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
ADC_RH
ADC_RL
12-bit AD result
0
1
12-bit AD result
2
12-bit AD result
3
12-bit AD result
12-bit AD result
4
5
12-bit AD result
6
12-bit AD result
7
12-bit AD result
Result FIFO Fulfilled
COMPARE
LOGIC
Channel FIFO Fulfilled
COMPARE
LOGIC
BUS CLK
COCO
D Q
CK
D Q
CK
NXP Semiconductors
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