Interrupt Level Setting Registers N (Ipc_Ilrsn); Irq - NXP Semiconductors MC9S08SU16 Reference Manual

Field
7–6 Interrupt Priority Mask pseudo stack position 3
IPM3
This field is the pseudo stack register for IPM3. The most recent information is stored in IPM3.
5–4 Interrupt Priority Mask pseudo stack position 2
IPM2
This field is the pseudo stack register for IPM2. The most recent information is stored in IPM2.
3–2 Interrupt Priority Mask pseudo stack position 1
IPM1
This field is the pseudo stack register for IPM1. The most recent information is stored in IPM1.
IPM0 Interrupt Priority Mask pseudo stack position 0
This field is the pseudo stack register for IPM0. The most recent information is stored in IPM0.

4.2.3 Interrupt Level Setting Registers n (IPC_ILRSn)

This set of registers (ILRS0-ILRS7) contains the user specified interrupt level for each
interrupt source, and indicates the number of the register (ILRSn is ILRS0 through
ILRS7).
Address: Eh base + 1852h offset + (1d × i), where i=0d to 7d
Bit 7
Read
ILRn3
Write
Reset 0
Field
7–6 Interrupt Level Register for Source n*4+3
ILRn3
This field sets the interrupt level for interrupt source n*4+3.
5–4 Interrupt Level Register for Source n*4+2
ILRn2
This field sets the interrupt level for interrupt source n*4+2.
3–2 Interrupt Level Register for Source n*4+1
ILRn1
This field sets the interrupt level for interrupt source n*4+1.
ILRn0 Interrupt Level Register for Source n*4+0
This field sets the interrupt level for interrupt source n*4+0.

4.3 IRQ

The IRQ (interrupt request) module provides a maskable interrupt input.
NXP Semiconductors
IPC_IPMPS field descriptions
6 5
ILRn2
0 0
IPC_ILRSn field descriptions
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Description
4 3
ILRn1
0 0
Description
Chapter 4 Interrupt
2 1
ILRn0
0 0
0
0
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