Signal Description Table - NXP Semiconductors MC9S08SU16 Reference Manual

24 QFN Pin Name
20 PTB0
21 PTB1
22 PTB2
23 PTB3
24 PTB4

7.4.2 Signal description table

24 Chip Module
QFN signal
name
1 PWM_WL PWM
PTB5 PORT
2 PWM_UH PWM
3 PWM_VH PWM
4 PWM_WH PWM
5 VCALMP GDU
6 VDD All
7 VDDX PMC
8 VSS All
9 RESET_b All
NXP Semiconductors
Default/ALT0
GDU_CMP0/
ADC0AD2/
ADC1AD2
GDU_CMP1/
ADC0AD3/
ADC1AD3
GDU_CMP2/
ADC0AD4/
ADC1AD4
PWM_UL
PWM_VL
Table 7-1. Pin signal description
Module Operating
signal name voltage
range (V)
PWM5 0–5
PTB5
PWM0 0–18
PWM2 0–18
PWM4 0–18
V 0–13
o_clamp
VDD 4.5–18
VDDX 0–5
VSS 0
RESET 0–5
Table continues on the next page...
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 7 Signal multiplexing and signal descriptions
ALT1 ALT2
Alt Type State
1
function during
reset
Default O Internally
pull to low
ALT3 I/O
Default O Internally
Pull to High
Default O Internally
Pull to High
Default O Internally
Pull to High
Default S Floating 5
V regulator
output
Default S Supply
Default S 5 V
regulator
output
Default S Supply
Default I Reset,
internal
ALT3
PTB0
PTB1
PTB2
PTB3
PTB4
Signal description
PWM output 5 for driving N-
MOSFET
This GPIO pin can be
individually programmed as an
input or output pin.
PWM output 0 for driving P-
MOSFET
PWM output 2 for driving P-
MOSFET
PWM output 2 for driving P-
MOSFET
Floating 5 V regulator for
PMOS Vgs clamp. It outputs 5
V below VDD. Recommend to
connect 1 µF low ESR ceramic
capacitor, such as X7R
capacitor between VDD and
this pin to stabilize the voltage
regulator output required for
proper device operation.
Power supplies 4.5–18 V
Connect a 4.7 µF or greater
bypass capacitor between this
pin and VSS to stabilize the
voltage regulator output
required for proper device
operation.
Ground
A direct hardware reset on the
processor. When RESET is
77