I2C Smbus Control And Status Register (I2C_Smb) - NXP Semiconductors MC9S08SU16 Reference Manual

21.4.9 I2C SMBus Control and Status register (I2C_SMB)

When the SCL and SDA signals are held high for a length of
time greater than the high timeout period, the SHTF1 flag sets.
Before reaching this threshold, while the system is detecting
how long these signals are being held high, a master assumes
that the bus is free. However, the SHTF1 bit is set to 1 in the
bus transmission process with the idle bus state.
When the TCKSEL bit is set, there is no need to monitor the
SHTF1 bit because the bus speed is too high to match the
protocol of SMBus.
Address: 18B0h base + 8h offset = 18B8h
Bit 7
Read
FACK
Write
Reset 0
Field
7 Fast NACK/ACK Enable
FACK
For SMBus packet error checking, the CPU must be able to issue an ACK or NACK according to the result
of receiving data byte.
0 An ACK or NACK is sent on the following receiving data byte
1 Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a
data byte generates a NACK.
6 SMBus Alert Response Address Enable
ALERTEN
Enables or disables SMBus alert response address matching.
NOTE: After the host responds to a device that used the alert response address, you must use software
0 SMBus alert response address matching is disabled
1 SMBus alert response address matching is enabled
5 Second I2C Address Enable
SIICAEN
Enables or disables SMBus device default address.
0 I2C address register 2 matching is disabled
1 I2C address register 2 matching is enabled
NXP Semiconductors
6 5
ALERTEN SIICAEN
0 0
I2C_SMB field descriptions
to put the device's address on the bus. The alert protocol is described in the SMBus specification.
Table continues on the next page...
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 21 Inter-Integrated Circuit (I2C)
NOTE
NOTE
4 3
SLTF
TCKSEL
w1c
0 0
Description
2 1
SHTF1 SHTF2
SHTF2IE
w1c
0 0
0
0
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