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2. SDA is sampled as low when the master drives high during the acknowledge bit of a
data receive cycle.
3. A START cycle is attempted when the bus is busy.
4. A repeated START cycle is requested in slave mode.
5. A STOP condition is detected when the master did not request it.
The ARBL bit must be cleared (by software) by writing 1 to it.
21.5.6.6 Timeout interrupt in SMBus
When the IICIE bit is set, the I2C module asserts a timeout interrupt (outputs SLTF and
SHTF2) upon detection of any of the mentioned timeout conditions, with one exception.
The SCL high and SDA high TIMEOUT mechanism must not be used to influence the
timeout interrupt output, because this timeout indicates an idle condition on the bus.
SHTF1 rises when it matches the SCL high and SDA high TIMEOUT and falls
automatically just to indicate the bus status. The SHTF2's timeout period is the same as
that of SHTF1, which is short compared to that of SLTF, so another control bit,
SHTF2IE, is added to enable or disable it.
21.5.7 Address matching wake-up
When a primary, range, or general call address match occurs when the I2C module is in
slave receive mode, the MCU wakes from a low power mode where no peripheral bus is
running.
Data sent on the bus that is the same as a target device address might also wake the target
MCU.
After the address matching IAAS bit is set, an interrupt is sent at the end of address
matching to wake the core. The IAAS bit must be cleared after the clock recovery.
After the system recovers and is in Run mode, restart the I2C
module if it is needed to transfer packets. To avoid I2C transfer
problems resulting from the situation, firmware should prevent
the MCU execution of a STOP instruction when the I2C
module is in the middle of a transfer unless the Stop mode
holdoff feature is used during this period (set FLT[SHEN] to 1).
NXP Semiconductors
NOTE
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 21 Inter-Integrated Circuit (I2C)
389
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