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Memory map and register description
Address: 0h base + 0h offset = 0h
Bit
7
Read
ENBDM
Write
Reset
0
Field
7
Enable BDM (Permit Active Background Mode)
ENBDM
Typically, this bit is written to 1 by the debug host shortly after the beginning of a debug session or
whenever the debug host resets the target and remains 1 until a normal reset clears it.
0
BDM cannot be made active (non-intrusive commands still allowed).
1
BDM can be made active to allow active background mode commands.
6
Background Mode Active Status
BDMACT
This is a read-only status bit.
0
BDM not active (user application program running).
1
BDM active and waiting for serial commands.
5
BDC Breakpoint Enable
BKPTEN
If this bit is clear, the BDC breakpoint is disabled and the FTS (force tag select) control bit and BDCBKPT
match register are ignored.
0
BDC breakpoint disabled.
1
BDC breakpoint enabled.
4
Force/Tag Select
FTS
When FTS = 1, a breakpoint is requested whenever the CPU address bus matches the BDCBKPT match
register. When FTS = 0, a match between the CPU address bus and the BDCBKPT register causes the
fetched opcode to be tagged. If this tagged opcode ever reaches the end of the instruction queue, the
CPU enters active background mode rather than executing the tagged opcode.
0
Tag opcode at breakpoint address and enter active background mode if CPU attempts to execute that
instruction
1
Breakpoint match forces active background mode at next instruction boundary (address need not be
an opcode)
3
Select Source for BDC Communications Clock
CLKSW
CLKSW defaults to 0, which selects the alternate BDC clock source.
0
Alternate BDC clock source.
1
MCU MSTRCLK.
2
Wait or Stop Status
WS
When the target CPU is in wait or stop mode, most BDC commands cannot function. However, the
BACKGROUND command can be used to force the target CPU out of wait or stop and into active
background mode where all BDC commands work. Whenever the host forces the target MCU into active
background mode, the host should issue a READ_STATUS command to check that BDMACT = 1 before
attempting other BDC commands.
544
6
5
BDMACT
BKPTEN
0
0
BDC_SCR field descriptions
Table continues on the next page...
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
4
3
FTS
CLKSW
0
0
Description
2
1
WS
WSF
DVF
0
0
NXP Semiconductors
0
0
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